WO2004036587A1 - Cellule memoire d'un dispositif de stockage dynamique - Google Patents

Cellule memoire d'un dispositif de stockage dynamique Download PDF

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Publication number
WO2004036587A1
WO2004036587A1 PCT/RU2002/000458 RU0200458W WO2004036587A1 WO 2004036587 A1 WO2004036587 A1 WO 2004036587A1 RU 0200458 W RU0200458 W RU 0200458W WO 2004036587 A1 WO2004036587 A1 WO 2004036587A1
Authority
WO
WIPO (PCT)
Prior art keywords
οblasτyu
μοp
base
bus
biποlyaρnοgο
Prior art date
Application number
PCT/RU2002/000458
Other languages
English (en)
Russian (ru)
Inventor
Victor Nikolaevich Mourachev
Saito Takeshi
Original Assignee
Victor Nikolaevich Mourachev
Saito Takeshi
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Nikolaevich Mourachev, Saito Takeshi filed Critical Victor Nikolaevich Mourachev
Priority to AU2002368294A priority Critical patent/AU2002368294A1/en
Priority to PCT/RU2002/000458 priority patent/WO2004036587A1/fr
Publication of WO2004036587A1 publication Critical patent/WO2004036587A1/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
    • H01L27/0722—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with lateral bipolar transistors and diodes, or capacitors, or resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/10—DRAM devices comprising bipolar components

Definitions

  • the invention is available on a nanoelectronics and may be used in the process of using a user-friendly storage device (portable)
  • the well-known memory slots for the DZU are equipped with functionally integrated structures, which are equipped with a key [optional].
  • the invention aims to increase the reliability of the operation of the memorable devices.
  • Another task is to increase the speed of action
  • JUNE 1 18 is equivalent to an electric circuit of a known simplest cell of a dynamically memorized device.
  • ⁇ a ⁇ YU 1 ⁇ azana e ⁇ vivalen ⁇ naya s ⁇ ema izves ⁇ n ⁇ y yachey ⁇ i ⁇ amya ⁇ i D ⁇ ZU P ⁇
  • the electrical circuit of the dynamic-memory storage device is according to the invention, which is indicated on June 3 for an optional transformer 9 and non-linear 10.
  • E ⁇ vivalen ⁇ naya s ⁇ ema ⁇ edlagaem ⁇ y yachey ⁇ i ⁇ amya ⁇ i D ⁇ ZU P ⁇ , s ⁇ de ⁇ zhi ⁇ ⁇ P ⁇ anzis ⁇ , is ⁇ 1 ⁇ g ⁇ s ⁇ edinen with ⁇ e ⁇ vym vyv ⁇ d ⁇ m ⁇ ndensa ⁇ a 2 v ⁇ y vyv ⁇ d ⁇ g ⁇ s ⁇ edinen with ⁇ bschey shin ⁇ y 3 and ⁇ lle ⁇ m 11 bi ⁇ lya ⁇ n ⁇ g ⁇ ⁇ anzis ⁇ a, s ⁇ 4 ⁇ P ⁇ anzis ⁇ a s ⁇ edinen with apel ⁇ y 12 bi ⁇ lya ⁇ n ⁇ g ⁇ ⁇ anzis ⁇ a and ⁇ e ⁇ vym output 10 of the second output of the resistor 10, connected to an emitter of a bi-polarized transformer and a discharge bus 5.
  • a dynamic DZU cell works as follows:
  • the device must be connected to the receiver.
  • the optional bus 5 is equipped with a potential “0” (low potential bus 3) or the optional no voltage ⁇ master ⁇
  • the ⁇ 08 transformer is turned off and the memorized compensation 2 is charged after 10 potentials available at a speed of 5 or more.
  • This current is amplified by a bipolar factor by an amount equal to its coefficient of amplification of the base current (L2e ⁇ 100).
  • the active information signal on the decoupled bus increases, which increases the reliability of the operation of the ROM drive. It is important that, at the same time, the charge of the parti- In the case of negative potential at capacitance 2, the base through ⁇ - ⁇ - ⁇ is used to convert to potential and the potential of the common bus is shared.
  • ⁇ The mode of storage of information on the shutter is 7/08;

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)

Abstract

La présente invention relève du domaine de la nanoélectronique. Selon cette invention, la mise en place dans une cellule mémoire d'un transistor bipolaire et d'une résistance non linéaire permet d'accroître la fiabilité et la vitesse de fonctionnement de ladite cellule mémoire. Cette cellule mémoire se présente sous la forme d'un élément fonctionnel intégré dans lequel la région du collecteur du transistor bipolaire sert simultanément de région de grille d'un transistor MOS, la région drain (D) du transistor MOS forme la région (B) du transistor bipolaire, la résistance étant formée par la partie quasi-neutre de la région active de la base (p-) du transistor bipolaire. L'intégration fonctionnelle du transistor MOS, du transistor bipolaire et de la résistance dans une seule structure permet d'obtenir une structure de cellule mémoire conforme aux paramètres topologiques et à la technologie de production de cellules mémoires à un seul transistor de dispositifs de stockage opérationnels dynamiques à génération aléatoire de données.
PCT/RU2002/000458 2002-10-21 2002-10-21 Cellule memoire d'un dispositif de stockage dynamique WO2004036587A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU2002368294A AU2002368294A1 (en) 2002-10-21 2002-10-21 Memory cell for a dynamic storing device
PCT/RU2002/000458 WO2004036587A1 (fr) 2002-10-21 2002-10-21 Cellule memoire d'un dispositif de stockage dynamique

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/RU2002/000458 WO2004036587A1 (fr) 2002-10-21 2002-10-21 Cellule memoire d'un dispositif de stockage dynamique

Publications (1)

Publication Number Publication Date
WO2004036587A1 true WO2004036587A1 (fr) 2004-04-29

Family

ID=32105764

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/RU2002/000458 WO2004036587A1 (fr) 2002-10-21 2002-10-21 Cellule memoire d'un dispositif de stockage dynamique

Country Status (2)

Country Link
AU (1) AU2002368294A1 (fr)
WO (1) WO2004036587A1 (fr)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3387286A (en) * 1967-07-14 1968-06-04 Ibm Field-effect transistor memory
SU483710A1 (ru) * 1973-05-29 1975-09-05 Московский институт электронной техники Ячейка пам ти
US4181981A (en) * 1977-12-30 1980-01-01 International Business Machines Corporation Bipolar two device dynamic memory cell
US4309716A (en) * 1979-10-22 1982-01-05 International Business Machines Corporation Bipolar dynamic memory cell
SU1275545A1 (ru) * 1981-10-19 1986-12-07 Организация П/Я Х-5263 Ячейка пам ти
RU2032944C1 (ru) * 1992-10-20 1995-04-10 Королев Сергей Анатольевич Элемент памяти
EP0971360A1 (fr) * 1992-12-10 2000-01-12 Sony Corporation Cellule de mémoire semi-conducteur

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3387286A (en) * 1967-07-14 1968-06-04 Ibm Field-effect transistor memory
SU483710A1 (ru) * 1973-05-29 1975-09-05 Московский институт электронной техники Ячейка пам ти
US4181981A (en) * 1977-12-30 1980-01-01 International Business Machines Corporation Bipolar two device dynamic memory cell
US4309716A (en) * 1979-10-22 1982-01-05 International Business Machines Corporation Bipolar dynamic memory cell
SU1275545A1 (ru) * 1981-10-19 1986-12-07 Организация П/Я Х-5263 Ячейка пам ти
RU2032944C1 (ru) * 1992-10-20 1995-04-10 Королев Сергей Анатольевич Элемент памяти
EP0971360A1 (fr) * 1992-12-10 2000-01-12 Sony Corporation Cellule de mémoire semi-conducteur

Also Published As

Publication number Publication date
AU2002368294A1 (en) 2004-05-04

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