WO2004021409A3 - Procede et systeme destines a ameliorer l'extraction de materiaux dielectriques a coefficient k eleve - Google Patents
Procede et systeme destines a ameliorer l'extraction de materiaux dielectriques a coefficient k eleve Download PDFInfo
- Publication number
- WO2004021409A3 WO2004021409A3 PCT/US2003/026496 US0326496W WO2004021409A3 WO 2004021409 A3 WO2004021409 A3 WO 2004021409A3 US 0326496 W US0326496 W US 0326496W WO 2004021409 A3 WO2004021409 A3 WO 2004021409A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- plasma
- enhance
- removal
- dielectric materials
- layer
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 7
- 239000003989 dielectric material Substances 0.000 title abstract 2
- 239000000463 material Substances 0.000 abstract 2
- 239000007789 gas Substances 0.000 abstract 1
- 239000011261 inert gas Substances 0.000 abstract 1
- 238000009832 plasma treatment Methods 0.000 abstract 1
- 238000001039 wet etching Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
- H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004532965A JP2005537668A (ja) | 2002-08-27 | 2003-08-26 | 高誘電率誘電体材料の除去を改良する方法及びシステム |
AU2003269995A AU2003269995A1 (en) | 2002-08-27 | 2003-08-26 | A method and system to enhance the removal of high-k-dielectric materials |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US40603102P | 2002-08-27 | 2002-08-27 | |
US60/406,031 | 2002-08-27 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2004021409A2 WO2004021409A2 (fr) | 2004-03-11 |
WO2004021409A3 true WO2004021409A3 (fr) | 2004-07-01 |
Family
ID=31978257
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2003/026496 WO2004021409A2 (fr) | 2002-08-27 | 2003-08-26 | Procede et systeme destines a ameliorer l'extraction de materiaux dielectriques a coefficient k eleve |
Country Status (4)
Country | Link |
---|---|
US (1) | US20040129674A1 (fr) |
JP (1) | JP2005537668A (fr) |
AU (1) | AU2003269995A1 (fr) |
WO (1) | WO2004021409A2 (fr) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6537844B1 (en) * | 2001-05-31 | 2003-03-25 | Kabushiki Kaisha Toshiba | Manufacturing method for exposure mask, generating method for mask substrate information, mask substrate, exposure mask, manufacturing method for semiconductor device and server |
DE10237696B3 (de) | 2002-08-15 | 2004-04-15 | Infineon Technologies Ag | Verfahren und Einrichtung zum Melden eines Übertragungsfehlers auf einer Datenleitung |
JP2006501651A (ja) * | 2002-09-27 | 2006-01-12 | 東京エレクトロン株式会社 | High−k誘電材料をエッチングするための方法及びシステム |
US20050064716A1 (en) * | 2003-04-14 | 2005-03-24 | Hong Lin | Plasma removal of high k metal oxide |
US7413996B2 (en) * | 2003-04-14 | 2008-08-19 | Lsi Corporation | High k gate insulator removal |
JP2005039015A (ja) * | 2003-07-18 | 2005-02-10 | Hitachi High-Technologies Corp | プラズマ処理方法および装置 |
US7037845B2 (en) * | 2003-08-28 | 2006-05-02 | Intel Corporation | Selective etch process for making a semiconductor device having a high-k gate dielectric |
US7115530B2 (en) * | 2003-12-03 | 2006-10-03 | Texas Instruments Incorporated | Top surface roughness reduction of high-k dielectric materials using plasma based processes |
US20060068603A1 (en) * | 2004-09-30 | 2006-03-30 | Tokyo Electron Limited | A method for forming a thin complete high-permittivity dielectric layer |
US7413992B2 (en) * | 2005-06-01 | 2008-08-19 | Lam Research Corporation | Tungsten silicide etch process with reduced etch rate micro-loading |
EP1969619A1 (fr) * | 2005-10-20 | 2008-09-17 | INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC) | Procede de fabrication de couche a constante dielectrique elevee |
KR100998417B1 (ko) * | 2007-08-20 | 2010-12-03 | 주식회사 하이닉스반도체 | 반도체 메모리 소자의 유전체막 형성 방법 |
US20090253268A1 (en) * | 2008-04-03 | 2009-10-08 | Honeywell International, Inc. | Post-contact opening etchants for post-contact etch cleans and methods for fabricating the same |
US8598027B2 (en) * | 2010-01-20 | 2013-12-03 | International Business Machines Corporation | High-K transistors with low threshold voltage |
CN102064103A (zh) * | 2010-12-02 | 2011-05-18 | 上海集成电路研发中心有限公司 | 高k栅介质层的制备方法 |
JP6980406B2 (ja) * | 2017-04-25 | 2021-12-15 | 株式会社日立ハイテク | 半導体製造装置及び半導体装置の製造方法 |
JP6905149B2 (ja) | 2019-02-14 | 2021-07-21 | 株式会社日立ハイテク | 半導体製造装置 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4690728A (en) * | 1986-10-23 | 1987-09-01 | Intel Corporation | Pattern delineation of vertical load resistor |
US4940509A (en) * | 1988-03-25 | 1990-07-10 | Texas Instruments, Incorporated | Isotropic etchant for capped silicide processes |
US6258608B1 (en) * | 1999-01-20 | 2001-07-10 | Samsung Electronics Co., Ltd. | Method for forming a crystalline perovskite ferroelectric material in a semiconductor device |
US20020043340A1 (en) * | 1989-02-27 | 2002-04-18 | Masayuki Kojima | Apparatus for processing samples |
US20030104706A1 (en) * | 2001-12-04 | 2003-06-05 | Matsushita Electric Industrial Co., Ltd. | Wet-etching method and method for manufacturing semiconductor device |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US104706A (en) * | 1870-06-28 | Improved device for tendering or chopping meat | ||
US43340A (en) * | 1864-06-28 | Improved leather-paper for floor-cloths | ||
WO1999026277A1 (fr) * | 1997-11-17 | 1999-05-27 | Mattson Technology, Inc. | Systemes et procedes pour traitement au plasma de tranches de semi-conducteur |
KR20010062209A (ko) * | 1999-12-10 | 2001-07-07 | 히가시 데쓰로 | 고내식성 막이 내부에 형성된 챔버를 구비하는 처리 장치 |
US6656852B2 (en) * | 2001-12-06 | 2003-12-02 | Texas Instruments Incorporated | Method for the selective removal of high-k dielectrics |
US6806095B2 (en) * | 2002-03-06 | 2004-10-19 | Padmapani C. Nallan | Method of plasma etching of high-K dielectric materials with high selectivity to underlying layers |
US6818553B1 (en) * | 2002-05-15 | 2004-11-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Etching process for high-k gate dielectrics |
US6579809B1 (en) * | 2002-05-16 | 2003-06-17 | Advanced Micro Devices, Inc. | In-situ gate etch process for fabrication of a narrow gate transistor structure with a high-k gate dielectric |
US6764898B1 (en) * | 2002-05-16 | 2004-07-20 | Advanced Micro Devices, Inc. | Implantation into high-K dielectric material after gate etch to facilitate removal |
-
2003
- 2003-08-21 US US10/644,957 patent/US20040129674A1/en not_active Abandoned
- 2003-08-26 AU AU2003269995A patent/AU2003269995A1/en not_active Abandoned
- 2003-08-26 WO PCT/US2003/026496 patent/WO2004021409A2/fr active Application Filing
- 2003-08-26 JP JP2004532965A patent/JP2005537668A/ja not_active Withdrawn
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4690728A (en) * | 1986-10-23 | 1987-09-01 | Intel Corporation | Pattern delineation of vertical load resistor |
US4940509A (en) * | 1988-03-25 | 1990-07-10 | Texas Instruments, Incorporated | Isotropic etchant for capped silicide processes |
US20020043340A1 (en) * | 1989-02-27 | 2002-04-18 | Masayuki Kojima | Apparatus for processing samples |
US6258608B1 (en) * | 1999-01-20 | 2001-07-10 | Samsung Electronics Co., Ltd. | Method for forming a crystalline perovskite ferroelectric material in a semiconductor device |
US20030104706A1 (en) * | 2001-12-04 | 2003-06-05 | Matsushita Electric Industrial Co., Ltd. | Wet-etching method and method for manufacturing semiconductor device |
Non-Patent Citations (1)
Title |
---|
THOMAS D J ET AL: "A practical PZT dry etching process that increases the top electrode contact reliability in pyroelectric detector arrays by using a M0RIhigh density plasma system", 2001 PROCEEDINGS IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE AND WORKSHOP. (ASMC). MUNICH, GERMANY, APRIL 23 - 24, 2001, IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE AND WORKSHOP, NEW YORK, NY: IEEE, US, vol. CONF. 12, 23 April 2001 (2001-04-23), pages 81 - 83, XP010544803, ISBN: 0-7803-6555-0 * |
Also Published As
Publication number | Publication date |
---|---|
US20040129674A1 (en) | 2004-07-08 |
AU2003269995A1 (en) | 2004-03-19 |
JP2005537668A (ja) | 2005-12-08 |
AU2003269995A8 (en) | 2004-03-19 |
WO2004021409A2 (fr) | 2004-03-11 |
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