WO2004015672A1 - Afficheurs couleur a cristaux liquides sequentiels integres - Google Patents

Afficheurs couleur a cristaux liquides sequentiels integres Download PDF

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Publication number
WO2004015672A1
WO2004015672A1 PCT/US2003/025164 US0325164W WO2004015672A1 WO 2004015672 A1 WO2004015672 A1 WO 2004015672A1 US 0325164 W US0325164 W US 0325164W WO 2004015672 A1 WO2004015672 A1 WO 2004015672A1
Authority
WO
WIPO (PCT)
Prior art keywords
display
row
pixel values
driver die
display substrate
Prior art date
Application number
PCT/US2003/025164
Other languages
English (en)
Inventor
Howard V. Goetz
Steven H. Linn
David L. Keith
Philip Odom
Original Assignee
Iljin Diamond Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Iljin Diamond Co., Ltd. filed Critical Iljin Diamond Co., Ltd.
Priority to AU2003258175A priority Critical patent/AU2003258175A1/en
Publication of WO2004015672A1 publication Critical patent/WO2004015672A1/fr

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0235—Field-sequential colour display

Definitions

  • the disclosure pertains to color-sequential liquid crystal displays.
  • Prior art projection display systems using three panels suffer from a need for accurate alignment (convergence) of the three displays. They also require complex, expensive optical systems to combine the images from the three displays into a focused, converged image. In addition, three channels of electronics are typically required to drive the three displays. In view of these shortcomings, improved projection display systems and methods are needed.
  • Sequential color displays comprise a display substrate and at least one video driver die mounted to the display substrate.
  • the display substrate includes a plurality of pixels arranged in rows and columns. Each column is associated with a column conductor and a column FET, and the at least one video driver die is configured to communicate pixel values to the column FETs.
  • at least a first video driver die and a second video driver die are mounted to the display substrate. The first video driver die is associated with a first set of pixel columns and the second video driver die is associated with a second set of pixel columns.
  • the first set of pixel columns are interleaved with the second set of pixel columns
  • four video driver die are attached to the display substrate, and each of the driver die is associated with a respective set of pixel columns.
  • a first through fourth video driver die are bonded to the display substrate.
  • the first video driver die and the second video driver die are configured to provide image data to a first set of column conductors
  • the third video driver die and the fourth video driver die are configured to provide image data to a second set of column conductors.
  • the column conductors of the first set and the second set are interleaved.
  • interconnect conductors on the display substrate are configured to electrically connect the video driver die to the column conductors.
  • row scanners are situated on the display substrate.
  • Display substrates comprise a set of row conductors and a set of column conductors, wherein intersections of the row conductors and the column conductors are associated with pixel locations. At least one bond pad is configured to receive a display driver die.
  • Display methods comprise directing a video signal to at least one video processor die mounted on a display substrate.
  • the video signal is processed with the video processor to determine pixel values for at least a row of display pixels.
  • a row scanner signal is produced on the display substrate and pixel values for the row of display pixels are established based on the row scanner signal and the determined pixel values, hi other examples, the video signal is processed to identify pixel values for the row of display pixels associated with red, blue, and green color components, and row scanner signals are configured to sequentially establish the pixel values associated with the red, blue, and green color components at the display pixels, h other examples, the pixel values associated with at least one of the color components are stored, and the stored values are retrieved after the pixel values associated with at least one other color component are scanned to the row of display pixels.
  • the video processor is configured to determine pixel values associated with red, green, and blue color components. Pixel values associated with at least one of the color components are stored until pixel values associated with a different color component are delivered to at least one row of display pixels. In other representative examples, pixel values associated with at least one of the color components are stored until pixel values associated with a different color component are delivered to a plurality of rows of display pixels, hi other examples, pixel values associated with at least one of the color components are stored until pixel values associated with a different color component are delivered to all rows of display pixels.
  • FIG. 1 is a schematic block diagram of a display substrate that includes a polysilicon display and digital drive die attached to the substrate.
  • FIG. 2 is a schematic block diagram of a display control system for the display substrate of FIG. 1.
  • FIG. 3 is a plan view of a circuit board layout that includes a display substrate as shown in FIG. 1.
  • FIGS. 4A-4E illustrate image formation using banded illumination with the display substrate of FIG. 1.
  • FIG. 5 is a schematic diagram of a portion of a line scan, sample and hold
  • a representative display includes a silicon CMOS digital die that is mounted on a polysilicon display substrate.
  • the CMOS die is configured to handle high-speed data to drive the display, so that only lower speed functions such as row scanning and a pixel thin film transistor (TFT) array are implemented in polysilicon.
  • a CMOS digital die can be configured to generate outputs that directly drive column FETs associated with each display column.
  • the die can be modular so that, for example, four such die can be used to drive a WVGA panel, six can be used to drive a WXGA panel, etc.
  • the die can be attached via an array of pads on a top surface that connect to a similar array of pads on the polysilicon display using, for example, a "flip-chip" process. Electrical connections are preferably made using an anisotropic adhesive connection, but solder or gold bumps or other connection schemes can be used. Interconnects between flip-chips can be handled by polysilicon or metal lines on the display substrate.
  • the display and drive electronics are preferably kept close together.
  • Traditional interconnects such as flexible cables are also generally not preferred as it is difficult to make high quality transmission lines on such cables.
  • the display can be mounted on a small circuit board with the drive electronics also mounted to the circuit board and close to the display.
  • the circuit board can include a cut-out behind the active area of the display to transmit light and the display can be electrically connected to the circuit board with wire bonds or Z-axis conductive strips.
  • FIG. 5 illustrates a portion of such a display that includes a drive die 502 and a row buffer 504.
  • a polysilicon/quartz display substrate 100 includes a pixel array 102, drive die 104-107, and bond pad areas 110, 111.
  • the pixel array is 864 pixels wide by 480 pixels high. Display columns can be interleaved so that, for example, even columns are driven by the top drive die 104, 105, and odd columns are driven from the bottom drive die 106, 107.
  • Each pair of die can be connected to a 16-bit digital data path or other data path with wirebonds or other interconnects, hi a representative example, the substrate 100 is about 15.6 mm by about 8.6 mm, and pixel pitch is 18 ⁇ m.
  • a row scanner 112 is also provided on the display substrate 100.
  • Digital line scan, sample and hold (LSSH)-systems can be used to drive such a display.
  • Such digital LSSH systems are described in, for example, PCT Publication WO 02/50810.
  • This disclosure describes an integrated full color display that, in some examples, can use such digital LSSH systems.
  • Representative drive electronics configured for placement on a circuit board are illustrated in FIG. 2.
  • a digital gate array 202, a frame buffer 204, a digital-to-analog converter 206, a buffer op-amp (not shown), and an EEPROM 210 are situated on a circuit board.
  • the frame buffer 204 is configured for frame sequential refresh of three colors.
  • a row buffer (not shown) can be used for row-sequential or segmented refresh.
  • the DAC 206 produces dataramp signal (DR) at an output 212 based on digital values from the gate array 202, and the op-amp buffers the dataramp voltages to levels needed to drive the display.
  • the EEPROM 210 can be used to store display-dependent calibrations, as needed.
  • RGB video input 216 encoded as, for example, low voltage differential signaling (LVDS) pairs, and power supply connections.
  • LVDS low voltage differential signaling
  • HS horizontal synch
  • CLK clock input
  • FIG. 3 is a plan view of a representative display/display driver combination.
  • a circuit board 302 is configured to retain a DAC, a gate array, a frame buffer (BUFF), an EEPROM, and a display assembly 303.
  • An input 304 is configured to receive video and power.
  • Bond pad regions 306 are provided, and flip chip drivers are provided for connection to drive die 311-314.
  • the flip chips include inputs/outputs for a variety of signals such as frame synch, clock, digital video, and others, and can be implemented in a substrate area of about 3.5 mm by 0.8 mm. In a representative example, such a display is operated with co-called
  • FIGS. 4A-4E illustrate banded illumination.
  • a green band is written beginning at row 1, a blue band at row 160, and a red band at row 320.
  • green band is written at row 40, blue band at row 200, and a red band at row 360.
  • a green band is written at row 80, a blue band at row 240, and a red band at row 400.
  • a red band is written at row 1, a green band at row 240, and a blue band at row 400.
  • the writing process continues in the same manner.
  • Image data associated with red (R), green (G), and blue (B) are written down the display panel at rows spaced by 160 rows.
  • green begins at row 1, blue at row 160, and red at row 320.
  • rows 1-480 are written with red data, and the image data for the remaining colors will have written 480 rows, starting at row 160 and ending at row 159 (blue), and starting at row 320 and ending at row 319.
  • a full image (480 rows of all colors) requires 6.0 ⁇ s.

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  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

La présente invention concerne un afficheur couleur séquentiel comprenant une matrice de circuit d'attaque d'afficheur (104-107) montée sur un substrat de polysilicium ou sur un autre substrat (100) d'afficheur à matrice active. Cette matrice de circuit d'attaque (104-107) est agencée de façon à commander des transistors FET en colonne associés aux colonnes de l'afficheur. Des balayeurs (112) de rang sont prévus sur le substrat de polysilicium. Cet afficheur est monté sur un porteur de carte de circuit qui comprend une ouverture agencée de façon à être optiquement transmissive.
PCT/US2003/025164 2002-08-12 2003-08-11 Afficheurs couleur a cristaux liquides sequentiels integres WO2004015672A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003258175A AU2003258175A1 (en) 2002-08-12 2003-08-11 Integrated sequential color liquid crystal displays

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US40295802P 2002-08-12 2002-08-12
US60/402,958 2002-08-12

Publications (1)

Publication Number Publication Date
WO2004015672A1 true WO2004015672A1 (fr) 2004-02-19

Family

ID=31715913

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/025164 WO2004015672A1 (fr) 2002-08-12 2003-08-11 Afficheurs couleur a cristaux liquides sequentiels integres

Country Status (3)

Country Link
AU (1) AU2003258175A1 (fr)
TW (1) TW200419497A (fr)
WO (1) WO2004015672A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4740782A (en) * 1982-07-12 1988-04-26 Hosiden Electronics Co., Ltd. Dot-matrix liquid crystal display
US5798744A (en) * 1994-07-29 1998-08-25 Hitachi, Ltd. Liquid crystal display apparatus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4740782A (en) * 1982-07-12 1988-04-26 Hosiden Electronics Co., Ltd. Dot-matrix liquid crystal display
US5798744A (en) * 1994-07-29 1998-08-25 Hitachi, Ltd. Liquid crystal display apparatus

Also Published As

Publication number Publication date
TW200419497A (en) 2004-10-01
AU2003258175A1 (en) 2004-02-25

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