WO2004012256A1 - Process for manufacturing mosfets using amorphous carbon replacement gate and structures formed in accordance therewith - Google Patents

Process for manufacturing mosfets using amorphous carbon replacement gate and structures formed in accordance therewith Download PDF

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Publication number
WO2004012256A1
WO2004012256A1 PCT/US2003/021107 US0321107W WO2004012256A1 WO 2004012256 A1 WO2004012256 A1 WO 2004012256A1 US 0321107 W US0321107 W US 0321107W WO 2004012256 A1 WO2004012256 A1 WO 2004012256A1
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WIPO (PCT)
Prior art keywords
gate
amorphous carbon
dummy gate
substrate
layer
Prior art date
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Ceased
Application number
PCT/US2003/021107
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French (fr)
Inventor
Douglas J. Bonser
Marina V. Plat
Chih Yuh Yang
Scott A. Bell
Darin A. Chan
Philip A. Fischer
Christopher F. Lyons
Mark S. Chang
Pei-Yuan Gao
Marilyn I. Wright
Lu You
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to AU2003249717A priority Critical patent/AU2003249717A1/en
Publication of WO2004012256A1 publication Critical patent/WO2004012256A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes

Definitions

  • Embodiments of the invention pertain to metal oxide semiconductor field effect transistors (MOSFETs), and in particular to the manufacture of MOSFETs using a replacement gate process.
  • MOSFETs metal oxide semiconductor field effect transistors
  • FIG. 1 shows an example of a typical MOSFET 10.
  • the MOSFET 10 includes gate structure comprised of a gate line 12 (hereinafter "gate Line” or “gate”), a gate insulator 14 and spacers 16.
  • the gate line 12 and gate insulator 14 are formed over a channel region 18 of a semiconductor substrate 20.
  • the gate structure is surrounded by an interlevel dielectric layer (ILD) 22 such as silicon oxide.
  • the MOSFET 10 further includes composite source and drain diffusions comprised of overlapping lightly doped source and drain regions 24 and heavily doped source and drain regions 26.
  • replacement gate in which the initial polysilicon gate is used as a "dummy" gate that is replaced with metal after formation of other MOSFET features. This is typically done by forming a MOSFET gate structure including a polysilicon dummy gate, depositing an ILD over the substrate and the gate structure, polishing back the ILD to expose the polysilicon dummy gate, etching to remove some or all of the polysilicon dummy gate, and then inlaying metal in place of the removed polysilicon to form a metal gate.
  • the replacement gate process improves over the conventional polysilicon gate MOSFET, the process has undesirable features.
  • One undesirable feature is that it is relatively difficult to pattern polysilicon with good profiles, particularly at small dimensions, and so formation of the polysilicon dummy gate is relatively difficult.
  • Another undesirable feature is the difficulty of preventing damage to the gate insulator. Because the gate insulator is so thin, any damage to the gate insulator during removal of the polysilicon gate requires complete removal and replacement of the gate insulator. Thus it would be desirable to have a replacement gate process that avoids the difficulties of polysilicon dummy gate formation and removal.
  • the replacement gate process is improved by the use of an amorphous carbon dummy gate.
  • Amorphous carbon is easily and accurately patterned and removed through the use of a dry anisotropic oxygen or hydrogen plasma etch, referred to herein as "ashing.” This treatment provides rapid removal and high selectivity.
  • Figures 2a, 2b, 2c, 2d, 2e, 2f and 2g show structures formed during processing in accordance with a preferred embodiment.
  • Figure 3 shows a process flow encompassing the preferred embodiment and alternatives thereto.
  • Figure 2a shows a semiconductor substrate 30 having formed thereon a gate insulating layer 32 such as Si0 2 or SiON. Overlying the gate insulating layer 32 are an amorphous carbon layer 34, a hardmask layer 36 such as SiN, and a photoresist pattern 38.
  • the amorphous carbon layer 34 is formed by a PECVD process using carbon containing precursors.
  • the hardmask layer 36, and the amorphous carbon layer 34 are sequentially anisotropically etched to form an amorphous carbon dummy gate 40 on the gate insulator 32.
  • the hardmask layer is typically patterned using a combination of Ar and CF 4 .
  • the amorphous carbon layer is typically patterned using a combination of HBr, oxygen, and argon.
  • lightly doped source and drain regions 44 are formed by implantation using the amorphous carbon dummy gate 40 to mask a channel region 46 in the substrate. Other areas of the substrate are suitably masked during implantation to define the lightly doped source and drain regions 44.
  • Figure 2c shows the structure of Figure 2b after formation of spacers 48 surrounding the amorphous carbon dummy gate 40.
  • the spacers 48 are typically made of silicon oxide or silicon nitride and are formed by depositing a conformal layer of silicon oxide over the substrate, followed by anisotropically etching the silicon oxide to leave spacers 48 as shown.
  • heavily doped source and drain regions 50 are formed by an implantation process that uses the dummy gate 40 and spacers 48 to mask the channel region 46 and extension portions of the lightly doped source and drain regions 44. Other areas of the substrate are suitably masked during implantation to define the heavily doped source and drain regions 50.
  • Figure 2d shows the structure of Figure 2c after formation of a conformal layer of an interlevel dielectric 52 such as silicon oxide over the substrate. As shown in Figure 2e, a portion of the interlevel dielectric layer 52 is removed by chemical mechanical polishing to expose the amorphous carbon dummy gate 40.
  • an interlevel dielectric 52 such as silicon oxide
  • Figure 2f shows the structure of Figure 2e after removal of the amorphous carbon dummy gate 40 by an ashing process to leave a void 54.
  • Ashing is preferably performed using a dry oxygen or hydrogen plasma.
  • the ashing process consumes amorphous carbon by forming volatile products such as carbon dioxide, carbon monoxide, or methane that are evacuated from the chamber.
  • Figure 2g shows the structure of Figure 2f after inlaying of a metal gate 56 into the void 54 left by the removed amorphous carbon dummy gate.
  • the metal gate 56 is preferably formed of a metal that exhibits relatively low resistivity and low diffusion, such as tungsten or aluminum. Other metals that may be used include, but are not limited to, TiN, WN, TaN, and Ru0 2 .
  • Inlaying is typically performed by depositing a conformal layer of metal by sputtering to fill the void 54, followed by polishing to remove an overburden portion of the sputtered metal to leave the inlaid metal
  • Figure 2g After the structure of Figure 2g is formed, additional conventional processing may be performed, such as formation of source and drain contacts by an inlay process and silicidation of the contacts, or formation of a protective layer over the ILD. While the process flow of Figures 2a-2g is presently considered to be the preferred embodiment of the invention, a wide variety of alternative embodiments in accordance with the invention may be formulated. For example, in one alternative embodiment, more than one set of spacers may be sequentially formed in conjunction with sequential implantations to form source and drain diffusions that are a composite of three or more implanted regions. In another alternative embodiment, source and drain contacts may be formed concurrently with inlaying of the metal gate.
  • processing tasks such as seed layer formation, seed layer enhancement, formation and removal of passivation layers or protective layers between processing tasks, formation and removal of photoresist masks and other masking layers such as antireflective layers, trimming of photoresist masks and other masking structures, formation of isolation structures, as well as other tasks, may be performed along with the tasks specifically described above. Further, the process need not be performed on an entire substrate such as an entire wafer, but rather may be performed selectively on sections of the substrate.
  • Figure 3 shows a process flow for producing a MOSFET that encompasses the preferred embodiment and its aforementioned alternatives, as well as other alternative embodiments that are not explicitly discussed here but will be apparent to those of ordinary skill in the art.
  • amorphous carbon layer is formed over a substrate (60).
  • the substrate is preferably a semiconductor layer that is covered by a gate insulating layer.
  • a gate structure comprising an amorphous carbon dummy gate is then formed from the amorphous carbon layer (62). This is preferably accomplished by patterning the amorphous carbon using a photoresist mask and a hard mask, followed by formation of spacers.
  • the dummy gate and spacers are preferably used as masks for one or more implantations that define source and drain diffusions.
  • An interlevel dielectric layer is then deposited over the substrate and gate structure (64), and a portion of the interlevel dielectric layer is then removed to expose the amorphous carbon dummy gate (66).
  • the amorphous carbon dummy gate is then removed by an ashing process (68). Ashing is preferably performed using oxygen or hydrogen plasma.
  • a metal gate is then inlaid in place of the amorphous carbon dummy gate (70).
  • the metal gate may be aluminum or tungsten, or another metal as described above.

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  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

In the manufacture of a MOSFET using a replacement gate process, a dummy gate (40) is formed of amorphous carbon. The dummy gate (40) is removed after formation of source and drain diffusions (50). Removal is accomplished by an ashing process using a dry plasma such as oxygen or hydrogen that exhibits good selectivity with respect to surrounding materials. The dummy gate (40) is replaced by an inlaid metal gate (56).

Description

PROCESS FOR MANUFACTURING MOSFETS USING
AMORPHOUS CARBON REPLACEMENT GATE AND
STRUCTURES FORMED IN ACCORDANCE THEREWITH
BACKGROUND OF THE INVENTION
Field of the Invention
Embodiments of the invention pertain to metal oxide semiconductor field effect transistors (MOSFETs), and in particular to the manufacture of MOSFETs using a replacement gate process.
Background Technology
Integrated circuits typically include large numbers of transistors such as MOSFETs. Figure 1 shows an example of a typical MOSFET 10. The MOSFET 10 includes gate structure comprised of a gate line 12 (hereinafter "gate Line" or "gate"), a gate insulator 14 and spacers 16. The gate line 12 and gate insulator 14 are formed over a channel region 18 of a semiconductor substrate 20. The gate structure is surrounded by an interlevel dielectric layer (ILD) 22 such as silicon oxide. The MOSFET 10 further includes composite source and drain diffusions comprised of overlapping lightly doped source and drain regions 24 and heavily doped source and drain regions 26.
Conventional gate lines were originally formed of polysilicon. However, in the face of increasing performance demands, polysilicon has proven to be too resistive. This led to the development of the
"replacement gate" process, in which the initial polysilicon gate is used as a "dummy" gate that is replaced with metal after formation of other MOSFET features. This is typically done by forming a MOSFET gate structure including a polysilicon dummy gate, depositing an ILD over the substrate and the gate structure, polishing back the ILD to expose the polysilicon dummy gate, etching to remove some or all of the polysilicon dummy gate, and then inlaying metal in place of the removed polysilicon to form a metal gate.
While the replacement gate process improves over the conventional polysilicon gate MOSFET, the process has undesirable features. One undesirable feature is that it is relatively difficult to pattern polysilicon with good profiles, particularly at small dimensions, and so formation of the polysilicon dummy gate is relatively difficult. Another undesirable feature is the difficulty of preventing damage to the gate insulator. Because the gate insulator is so thin, any damage to the gate insulator during removal of the polysilicon gate requires complete removal and replacement of the gate insulator. Thus it would be desirable to have a replacement gate process that avoids the difficulties of polysilicon dummy gate formation and removal.
SUMMARY OF THE INVENTION In accordance with preferred embodiments of the invention, the replacement gate process is improved by the use of an amorphous carbon dummy gate. Amorphous carbon is easily and accurately patterned and removed through the use of a dry anisotropic oxygen or hydrogen plasma etch, referred to herein as "ashing." This treatment provides rapid removal and high selectivity.
DESCRIPTION OF DRAWINGS Figure 1 shows a conventional MOSFET structure.
Figures 2a, 2b, 2c, 2d, 2e, 2f and 2g show structures formed during processing in accordance with a preferred embodiment.
Figure 3 shows a process flow encompassing the preferred embodiment and alternatives thereto.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
Structures formed during processing in accordance with a preferred embodiment of the invention are illustrated in Figures 2a-2g. Figure 2a shows a semiconductor substrate 30 having formed thereon a gate insulating layer 32 such as Si02 or SiON. Overlying the gate insulating layer 32 are an amorphous carbon layer 34, a hardmask layer 36 such as SiN, and a photoresist pattern 38. The amorphous carbon layer 34 is formed by a PECVD process using carbon containing precursors.
As shown in Figure 2b, the hardmask layer 36, and the amorphous carbon layer 34 are sequentially anisotropically etched to form an amorphous carbon dummy gate 40 on the gate insulator 32. The hardmask layer is typically patterned using a combination of Ar and CF4. The amorphous carbon layer is typically patterned using a combination of HBr, oxygen, and argon. After etching to form the dummy gate 40, lightly doped source and drain regions 44 are formed by implantation using the amorphous carbon dummy gate 40 to mask a channel region 46 in the substrate. Other areas of the substrate are suitably masked during implantation to define the lightly doped source and drain regions 44.
Figure 2c shows the structure of Figure 2b after formation of spacers 48 surrounding the amorphous carbon dummy gate 40. The spacers 48 are typically made of silicon oxide or silicon nitride and are formed by depositing a conformal layer of silicon oxide over the substrate, followed by anisotropically etching the silicon oxide to leave spacers 48 as shown. After the spacers 48 are formed, heavily doped source and drain regions 50 are formed by an implantation process that uses the dummy gate 40 and spacers 48 to mask the channel region 46 and extension portions of the lightly doped source and drain regions 44. Other areas of the substrate are suitably masked during implantation to define the heavily doped source and drain regions 50. Figure 2d shows the structure of Figure 2c after formation of a conformal layer of an interlevel dielectric 52 such as silicon oxide over the substrate. As shown in Figure 2e, a portion of the interlevel dielectric layer 52 is removed by chemical mechanical polishing to expose the amorphous carbon dummy gate 40.
Figure 2f shows the structure of Figure 2e after removal of the amorphous carbon dummy gate 40 by an ashing process to leave a void 54. Ashing is preferably performed using a dry oxygen or hydrogen plasma. The ashing process consumes amorphous carbon by forming volatile products such as carbon dioxide, carbon monoxide, or methane that are evacuated from the chamber. Figure 2g shows the structure of Figure 2f after inlaying of a metal gate 56 into the void 54 left by the removed amorphous carbon dummy gate. The metal gate 56 is preferably formed of a metal that exhibits relatively low resistivity and low diffusion, such as tungsten or aluminum. Other metals that may be used include, but are not limited to, TiN, WN, TaN, and Ru02. Inlaying is typically performed by depositing a conformal layer of metal by sputtering to fill the void 54, followed by polishing to remove an overburden portion of the sputtered metal to leave the inlaid metal gate 56 as shown in Figure 2g.
After the structure of Figure 2g is formed, additional conventional processing may be performed, such as formation of source and drain contacts by an inlay process and silicidation of the contacts, or formation of a protective layer over the ILD. While the process flow of Figures 2a-2g is presently considered to be the preferred embodiment of the invention, a wide variety of alternative embodiments in accordance with the invention may be formulated. For example, in one alternative embodiment, more than one set of spacers may be sequentially formed in conjunction with sequential implantations to form source and drain diffusions that are a composite of three or more implanted regions. In another alternative embodiment, source and drain contacts may be formed concurrently with inlaying of the metal gate.
In addition to the aforementioned alternatives, various additional combinations of the features of the preferred embodiment and its aforementioned alternatives may also be implemented. It will also be apparent to those having ordinary skill in the art that the tasks described in the preferred embodiment and the aforementioned alternatives are not necessarily exclusive of other tasks, but rather that further tasks may be incorporated in accordance with the particular structures to be formed. For example, processing tasks such as seed layer formation, seed layer enhancement, formation and removal of passivation layers or protective layers between processing tasks, formation and removal of photoresist masks and other masking layers such as antireflective layers, trimming of photoresist masks and other masking structures, formation of isolation structures, as well as other tasks, may be performed along with the tasks specifically described above. Further, the process need not be performed on an entire substrate such as an entire wafer, but rather may be performed selectively on sections of the substrate.
Figure 3 shows a process flow for producing a MOSFET that encompasses the preferred embodiment and its aforementioned alternatives, as well as other alternative embodiments that are not explicitly discussed here but will be apparent to those of ordinary skill in the art. Initially an amorphous carbon layer is formed over a substrate (60). The substrate is preferably a semiconductor layer that is covered by a gate insulating layer. A gate structure comprising an amorphous carbon dummy gate is then formed from the amorphous carbon layer (62). This is preferably accomplished by patterning the amorphous carbon using a photoresist mask and a hard mask, followed by formation of spacers. The dummy gate and spacers are preferably used as masks for one or more implantations that define source and drain diffusions. An interlevel dielectric layer is then deposited over the substrate and gate structure (64), and a portion of the interlevel dielectric layer is then removed to expose the amorphous carbon dummy gate (66). The amorphous carbon dummy gate is then removed by an ashing process (68). Ashing is preferably performed using oxygen or hydrogen plasma. A metal gate is then inlaid in place of the amorphous carbon dummy gate (70). The metal gate may be aluminum or tungsten, or another metal as described above.
While the embodiment illustrated in the figures and described above is presently preferred, it should be understood that the presently preferred embodiment and its aforementioned alternatives are offered by way of example only. The invention is not limited to a particular embodiment, but extends to various modifications, combinations, and permutations that fall within the scope and spirit of the appended claims.

Claims

CLAIMSWhat is claimed is:
1. A method of forming a transistor comprising: forming an amorphous carbon layer (34) over a substrate; forming a gate structure on the substrate from the amorphous carbon layer, the gate structure comprising an amorphous carbon dummy gate (40); depositing an interlevel dielectric layer (52) over the substrate and the gate structure; removing a portion of the interlevel dielectric layer (52) to expose the amorphous carbon dummy gate (40); removing the amorphous carbon dummy gate (40) by an ashing process; and inlaying a metal gate (56) in place of the amorphous carbon dummy gate (40).
2. The method claimed in claim 1, wherein the substrate comprises a semiconductor material and the amorphous carbon layer (34) is formed on the substrate, and wherein inlaying a metal gate (56) in place of the amorphous carbon dummy gate (40) is preceded by forming a gate insulator that separates the metal gate from the substrate.
3. The method claimed in claim 1, wherein the gate structure further comprises spacers (48) surrounding the dummy gate (40).
4. The method claimed in claim 3, wherein lightly doped source and drain regions (44) are implanted using the amorphous carbon dummy gate (40) as a mask prior to formation of the spacer (48).
5. The method claimed in claim 4, wherein heavily doped source and drain regions (50) are implanted using the amorphous carbon dummy gate (40) and the spacer (48) as a mask prior to depositing the interlevel dielectric layer (52).
6. The method claimed in claim 1, wherein removing a portion of the interlevel dielectric layer (52) to expose the amorphous carbon dummy gate (40) is performed by chemical mechanical polishing.
7. The method claimed in claim 1, wherein the ashing process comprises an oxygen atmosphere.
8. The method claimed 1, wherein the ashing process comprises a hydrogen atmosphere.
9. The method claimed in claim 1, wherein metal source and drain contacts are inlaid in the interlevel insulating layer (52) concurrently with inlaying of the metal gate (56).
10. A structure formed during manufacture of a MOSFET by a replacement gate process, comprising: a substrate including source and drain diffusions (50); a gate insulator (32) formed over the substrate; and an amorphous carbon dummy gate (40) formed on the gate insulator (32) over a channel region.
PCT/US2003/021107 2002-07-31 2003-07-03 Process for manufacturing mosfets using amorphous carbon replacement gate and structures formed in accordance therewith Ceased WO2004012256A1 (en)

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US40012302P 2002-07-31 2002-07-31
US60/400,123 2002-07-31
US33547302A 2002-12-31 2002-12-31
US10/335,473 2002-12-31

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CN102779746A (en) * 2012-08-16 2012-11-14 上海华力微电子有限公司 Method for forming metal grid
CN103390556A (en) * 2012-05-08 2013-11-13 中国科学院微电子研究所 Semiconductor device manufacturing method
CN103426754A (en) * 2012-05-14 2013-12-04 中芯国际集成电路制造(上海)有限公司 Method for forming transistor
CN104078363A (en) * 2013-03-29 2014-10-01 中国科学院微电子研究所 Semiconductor device manufacturing method
CN105185713A (en) * 2015-08-26 2015-12-23 上海华力微电子有限公司 HKMG device preparation method

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US6090672A (en) * 1998-07-22 2000-07-18 Wanlass; Frank M. Ultra short channel damascene MOS transistors
US6251763B1 (en) * 1997-06-30 2001-06-26 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing same
US6376347B1 (en) * 1999-09-27 2002-04-23 Kabushiki Kaisha Toshiba Method of making gate wiring layer over semiconductor substrate

Patent Citations (5)

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Publication number Priority date Publication date Assignee Title
US5391510A (en) * 1992-02-28 1995-02-21 International Business Machines Corporation Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps
US6251763B1 (en) * 1997-06-30 2001-06-26 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing same
EP0929105A2 (en) * 1998-01-09 1999-07-14 Sharp Kabushiki Kaisha Metal gate sub-micron mos transistor and method of making same
US6090672A (en) * 1998-07-22 2000-07-18 Wanlass; Frank M. Ultra short channel damascene MOS transistors
US6376347B1 (en) * 1999-09-27 2002-04-23 Kabushiki Kaisha Toshiba Method of making gate wiring layer over semiconductor substrate

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103390556A (en) * 2012-05-08 2013-11-13 中国科学院微电子研究所 Semiconductor device manufacturing method
WO2013166631A1 (en) * 2012-05-08 2013-11-14 中国科学院微电子研究所 Method for manufacturing semiconductor component
US20150118818A1 (en) * 2012-05-08 2015-04-30 Haizhou Yin Method for manufacturing semiconductor device
US9530861B2 (en) 2012-05-08 2016-12-27 Institute of Microelectronics, Chinese Academy of Sciences Method for manufacturing semiconductor device
CN103426754A (en) * 2012-05-14 2013-12-04 中芯国际集成电路制造(上海)有限公司 Method for forming transistor
CN102779746A (en) * 2012-08-16 2012-11-14 上海华力微电子有限公司 Method for forming metal grid
CN104078363A (en) * 2013-03-29 2014-10-01 中国科学院微电子研究所 Semiconductor device manufacturing method
CN105185713A (en) * 2015-08-26 2015-12-23 上海华力微电子有限公司 HKMG device preparation method

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AU2003249717A1 (en) 2004-02-16

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