CN105185713A - HKMG device preparation method - Google Patents
HKMG device preparation method Download PDFInfo
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- CN105185713A CN105185713A CN201510532382.7A CN201510532382A CN105185713A CN 105185713 A CN105185713 A CN 105185713A CN 201510532382 A CN201510532382 A CN 201510532382A CN 105185713 A CN105185713 A CN 105185713A
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- grid
- silicon dioxide
- dioxide film
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- semiconductor substrate
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- 238000002360 preparation method Methods 0.000 title claims abstract description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 93
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 47
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 45
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 42
- 238000005530 etching Methods 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 16
- 238000000151 deposition Methods 0.000 claims abstract description 13
- 229920005591 polysilicon Polymers 0.000 claims description 36
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 33
- 229910052760 oxygen Inorganic materials 0.000 claims description 33
- 239000001301 oxygen Substances 0.000 claims description 33
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 24
- 229910052799 carbon Inorganic materials 0.000 claims description 22
- 230000008569 process Effects 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- FRIKWZARTBPWBN-UHFFFAOYSA-N [Si].O=[Si]=O Chemical compound [Si].O=[Si]=O FRIKWZARTBPWBN-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 239000007792 gaseous phase Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 229910002092 carbon dioxide Inorganic materials 0.000 claims description 2
- 239000001569 carbon dioxide Substances 0.000 claims description 2
- 238000005137 deposition process Methods 0.000 claims description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- CSJDCSCTVDEHRN-UHFFFAOYSA-N methane;molecular oxygen Chemical compound C.O=O CSJDCSCTVDEHRN-UHFFFAOYSA-N 0.000 description 4
- 239000012212 insulator Substances 0.000 description 3
- 238000011031 large-scale manufacturing process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 239000010421 standard material Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000011513 prestressed concrete Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Formation Of Insulating Films (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention discloses an HKMG device preparation method. The method comprises the steps of 1, providing a semiconductor substrate; 2, successively depositing thick gate oxide, amorphous carbon and a silicon dioxide film on the semiconductor substrate, and depositing polycrystalline silicon on the silicon dioxide film; 3, performing the patterning treatment on the polycrystalline silicon to form an isolating layer on the polycrystalline silicon out of a region for grid formation, and forming an etching stop layer among the isolating layer, the semiconductor substrate and the grid region; 4, etching to remove the polycrystalline silicon in the grid region; 5, stripping to remove the silicon dioxide film and the amorphous carbon that remain in the grid region; 6, filling a high-k dielectric layer and the metal grid material in the grid region. According to the technical scheme of the invention, the thick gate oxide, the amorphous carbon and the silicon dioxide film can be directly applied in existing equipment, so that no extra equipment investment is required. Meanwhile, the problems of pollution and thermal instability are avoided.
Description
Technical field
The present invention relates to IC manufacturing field, particularly the preparation method of a kind of HKMG (high k gate insulator+metal gates) device.
Background technology
Along with developing rapidly of very large scale integration technology, the size of MOSFET element, in continuous reduction, generally includes: the reduction of MOSFET element channel length, and the thinning grade of gate oxide thickness is to obtain device speed faster.But be developed to sub-micro level, particularly when 45 nanometers and following technology node, cannot bear the height electric leakage continuing reduction gate oxide thickness and bring.Industry introduces the design of high k gate insulator and metal gate in 45 nanometers and following technique, after 28 nanometers, the thermal stability for high k (high dielectric radio) material considers the unified post tensioned unbonded prestressed concrete technique using HKMG (high k gate insulator+metal gates) especially.
The redundancy polysilicon forming technique that prior art utilizes industry to know prepares HKMG device, and as shown in figures 1-4, step comprises idiographic flow:
First, thick layer grid oxygen 2 is grown on semiconductor substrate 1;
Then, normal flow growing polycrystalline silicon layer 3, carries out graphical treatment to described polysilicon layer 3, forms separator 4, specifically as shown in Figure 2 with other region outside area of grid to be formed on described polysilicon layer 3.
Then, as shown in Figure 3, the polysilicon layer 3 of dry etching area of grid redundancy is adopted, and with thick grid oxygen 2 for cutoff layer.Because the requirement of HKMG device to thick grid oxygen 2 thickness is higher, it is even higher that this just needs polysilicon and silicon dioxide etching selection ratio must arrive 1:100, therefore, adjusts and control very difficult in this step to the etching of polysilicon layer 3.Also have dry etching to add wet method etch combinations in addition, but the stability of dry etching to board have high requirement.Much more very wet etching also needs to keep over etching to ensure noresidue simultaneously, larger to the loss of bottom thick grid oxygen 2.
Finally, as shown in Figure 4, thick grid oxygen 2 is graphically peeled off according to normal flow, growth initial oxide layer and deposit high-g value 5 and fill metal gate material 6.
It can thus be appreciated that above-mentioned flow process requires extremely high to the precision controlling of etching technics, crossing a little to carve to affect the thickness of initial oxide film and the surface smoothness of channel region silicon substrate, and will cause residual polycrystalline silicon after a little while, process window is minimum.
Summary of the invention
The invention provides a kind of preparation method of HKMG device, to solve the above-mentioned technical problem existed in prior art.
For solving the problems of the technologies described above, the invention provides a kind of preparation method of HKMG device, comprising:
Step 1: Semiconductor substrate is provided;
Step 2: deposition of thick grid oxygen, agraphitic carbon and silicon dioxide film successively on the semiconductor substrate, and on described silicon dioxide film deposit spathic silicon;
Step 3: carry out graphical treatment to described polysilicon, to form separator outside the region of grid to be formed on described polysilicon, is formed with etching stop layer between described separator and Semiconductor substrate and area of grid;
Step 4: etching removes the polysilicon of area of grid;
Step 5: peel off and remove the remaining silicon dioxide film of area of grid and agraphitic carbon;
Step 6: fill high-k dielectric layer and metal gate material at area of grid.
As preferably, in described step 2, adopt chemical gaseous phase depositing process to form described agraphitic carbon on described thick grid oxygen, adopt atom position deposition process deposited silicon dioxide silicon fiml on described agraphitic carbon.
As preferably, the thickness of described agraphitic carbon is 50 ~ 200 dusts, and the thickness of described silicon dioxide film is 20 ~ 100 dusts.
As preferably, described step 3 comprises:
Step 31: the region coating photoresist of grid to be formed on described polysilicon;
Step 32: with described photoresist for mask take Semiconductor substrate as cutoff layer, and the described polysilicon beyond etching grid region, silicon dioxide film, agraphitic carbon and thick grid oxygen, to form groove;
Step 33: in the described Semiconductor substrate in described groove and recess edge formed etching stop layer, and in described groove fill insulant formed separator.
As preferably, in described step 5, dry etch process is adopted to remove remaining silicon dioxide film and agraphitic carbon.
As preferably, when forming core voltage devices, described step 6 comprises: peel off and remove described thick grid oxygen, and deposit initial oxide layer successively on a semiconductor substrate, described initial oxide layer fills high-k dielectric layer, workfunction layers and metal gate material successively.
As preferably, when forming I/O device, described step 6 comprises: on described thick grid oxygen, fill high-k dielectric layer, workfunction layers and metal gate material successively.
As preferably, described metal gate material adopts aluminium, and described thick grid oxygen adopts silicon dioxide.
As preferably, in described step 4, dry etch process is adopted to remove the polysilicon layer of area of grid.
Compared with prior art, the present invention has the following advantages:
1, the present invention is by forming oxygen (thick grid oxygen)-agraphitic carbon-oxygen (silicon dioxide film) combined films on a semiconductor substrate, the deposition of each layer all can directly be carried out in existing device, there is no extra equipment investment, and oxygen-agraphitic carbon-oxygen belongs to leading portion standard material, without the need to concern of contamination or thermal stability problems;
2, in etch polysilicon step, etch-stop is on the superiors' silicon dioxide film, because the superiors' silicon dioxide film belongs to sacrifice layer, polysilicon and silicon dioxide etching selection ratio is allowed to be low to moderate 1:10, relative to prior art, etching of the present invention easily adjusts and controls, and is easier to large-scale production;
3, when peeling off remaining a small amount of the superiors silicon dioxide film and agraphitic carbon, on the thick grid oxygen impact of bottom, very little and difference is fixed, and within the thickness of general thick grid oxygen is lost in 2A, effectively can improve the stability of device;
4, in oxygen-agraphitic carbon-oxygen combined films of the present invention, the superiors' silicon dioxide film is used for the sacrifice layer of dry etching, and intermediate layer amorphous carbon film is used for protecting the thick grid oxygen of lowermost layer;
5, the preparation method of HKMG device of the present invention first dry etching polysilicon, is parked on the superiors' silicon dioxide film.Then dry method peels off a small amount of the superiors silicon dioxide film and intermediate layer amorphous carbon film, can protect the flow process that polysilicon is peeled off.
Accompanying drawing explanation
Fig. 1 is the device schematic diagram in the preparation method of existing HKMG device after deposit spathic silicon;
Fig. 2 is the device schematic diagram after forming separator in the preparation method of existing HKMG device;
Fig. 3 is the device schematic diagram in the preparation method of existing HKMG device after etch polysilicon;
Fig. 4 is the device schematic diagram after forming HKMG device in the preparation method of existing HKMG device;
Fig. 5 is the device schematic diagram in the preparation method of HKMG device of the present invention after deposit spathic silicon;
Fig. 6 is the device schematic diagram after forming separator in the preparation method of HKMG device of the present invention;
Fig. 7 etches the device schematic diagram after removing polysilicon and part of silica film in the preparation method of HKMG device of the present invention;
Fig. 8 is the device schematic diagram after removing residue silicon dioxide film and agraphitic carbon in the preparation method of HKMG device of the present invention;
Fig. 9 is the device schematic diagram after forming HKMG device in the preparation method of HKMG device of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.It should be noted that, accompanying drawing of the present invention all adopts the form of simplification and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
As shown in Figures 5 to 9, the preparation method of a kind of HKMG device of the present invention, specifically comprises the following steps:
Step 1: provide Semiconductor substrate 10, this Semiconductor substrate 10 is generally silicon base.
Step 2: deposition of thick grid oxygen 20, agraphitic carbon 30 and silicon dioxide film 40 successively in described Semiconductor substrate 10, and on described silicon dioxide film 40 deposit spathic silicon 50.Device after formation as shown in Figure 5, particularly, described thick grid oxygen 20 adopts silicon dioxide, after depositing described thick grid oxygen 20, utilize CVD (chemical gaseous phase depositing process) deposit amorphous carbon layers 30 on thick grid oxygen 20, thickness range at 50 ~ 200A, further, the agraphitic carbon 30 of deposition can bear the heat treatment of lower 30 minutes of 950 DEG C of temperature, can meet the demand of normal logic processing procedure heat budget.Then, then adopt atom position deposited silicon dioxide silicon fiml 40 in without ALD (the atom position deposition) equipment of plasma, the thickness of described silicon dioxide film 40 is 20 ~ 100 dusts.
Step 3: graphical treatment is carried out to described polysilicon 50, to form separator 70 outside the region of grid to be formed on described polysilicon 50, be formed with etching stop layer 60 between described separator 70 and Semiconductor substrate 10 and area of grid, the device architecture after formation as shown in Figure 6.
Preferably, described step 3 mainly comprises:
Step 31: the region coating photoresist of grid to be formed on described polysilicon 50;
Step 32: with described photoresist for mask, with Semiconductor substrate 10 for cutoff layer, the described polysilicon 50 beyond etching grid region, silicon dioxide film 40, agraphitic carbon 30 and thick grid oxygen 20, to form groove;
Step 33: in the described Semiconductor substrate 10 in described groove and recess edge formed etching stop layer 60, and in described groove fill insulant formed separator 70.
Further, described etching stop layer 60 adopts silicon nitride, and described etching stop layer 60 can, in the follow-up etching process to polysilicon 50, avoid etching to impact separator 70.
Step 4: as shown in Figure 7, etching removes the polysilicon 50 of area of grid; Dry etch process specifically can be adopted to remove the polysilicon 50 of area of grid, and etch-stop is on the superiors' silicon dioxide film 40, because the superiors' silicon dioxide film 40 belongs to sacrifice layer, polysilicon 50 is allowed to be low to moderate 1:10 with the etching selection ratio of silicon dioxide, relative to prior art, etching of the present invention easily adjusts and controls, and is easier to large-scale production.
Step 5: as shown in Figure 8, removes the remaining silicon dioxide film 40 of area of grid and agraphitic carbon 30, particularly, dry etch process can be adopted to remove remaining silicon dioxide film 40 and described agraphitic carbon 30.
Step 6: fill high-k dielectric layer and metal gate material at area of grid.Because the device formed is different, the structure of its grid is also different.For the distinct point of grid generation type of core voltage devices and I/O device in the present invention.
As shown in Figure 9, when forming described core voltage devices, step 6 comprises: peel off and remove described thick grid oxygen 20, and deposits initial oxide layer 80 successively over the semiconductor substrate 10, and described initial oxide layer 80 is filled high-k dielectric layer 90, workfunction layers 100 and metal gate material 110 successively.
And when forming I/O device, without the need to removing thick grid oxygen 20, therefore step 6 comprises: fill high-k dielectric layer 90, workfunction layers 100 and metal gate material 110 on described thick grid oxygen 20 successively, and further, described metal gate material 110 adopts aluminium.
In sum, the invention provides a kind of preparation method of HKMG device, comprising: step 1: Semiconductor substrate 10 is provided; Step 2: deposition of thick grid oxygen 20, agraphitic carbon 30 and silicon dioxide film 40 successively in described Semiconductor substrate 10, and on described silicon dioxide film 40 deposit spathic silicon 50; Step 3: carry out graphical treatment to described polysilicon 50, to form separator 70 outside the region of grid to be formed on described polysilicon 50, is formed with etching stop layer 60 between described separator 70 and Semiconductor substrate 10 and area of grid; Step 4: etching removes the polysilicon 50 of area of grid; Step 5: peel off and remove the remaining silicon dioxide film 40 of area of grid and agraphitic carbon 30; Step 6: fill high-k dielectric layer 90 and metal gate material 110 at area of grid.The present invention is by forming oxygen-agraphitic carbon-silica composition film over the semiconductor substrate 10, can directly carry out in existing device, there is no extra equipment investment, and oxygen-agraphitic carbon-oxygen belongs to leading portion standard material, without the need to concern of contamination or thermal stability problems; In step 4, etch-stop on the superiors' silicon dioxide film 40, because the superiors' silicon dioxide film 40 belongs to sacrifice layer, polysilicon 50 and silicon dioxide etching selection ratio is allowed to be low to moderate 1:10, relative to prior art, etching of the present invention easily adjusts and controls, and is easier to large-scale production; And when peeling off remaining a small amount of the superiors silicon dioxide film 40 and agraphitic carbon 30, affecting very little and difference to the thick grid oxygen 20 of bottom fixes, within general thick grid oxygen 20 thickness is lost in 2A, the stability of device effectively can be improved.
Obviously, those skilled in the art can carry out various change and modification to invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (9)
1. a preparation method for HKMG device, comprising:
Step 1: Semiconductor substrate is provided;
Step 2: deposition of thick grid oxygen, agraphitic carbon and silicon dioxide film successively on the semiconductor substrate, and on described silicon dioxide film deposit spathic silicon;
Step 3: carry out graphical treatment to described polysilicon, to form separator outside the region of grid to be formed on described polysilicon, is formed with etching stop layer between described separator and Semiconductor substrate and area of grid;
Step 4: etching removes the polysilicon of area of grid;
Step 5: peel off and remove the remaining silicon dioxide film of area of grid and agraphitic carbon;
Step 6: fill high-k dielectric layer and metal gate material at area of grid.
2. the preparation method of HKMG device as claimed in claim 1, it is characterized in that, in described step 2, adopt chemical gaseous phase depositing process to form described agraphitic carbon on described thick grid oxygen, adopt atom position deposition process deposited silicon dioxide silicon fiml on described agraphitic carbon.
3. the preparation method of HKMG device as claimed in claim 1 or 2, it is characterized in that, the thickness of described agraphitic carbon is 50 ~ 200 dusts, and the thickness of described silicon dioxide film is 20 ~ 100 dusts.
4. the preparation method of HKMG device as claimed in claim 1, it is characterized in that, described step 3 comprises:
Step 31: the region coating photoresist of grid to be formed on described polysilicon;
Step 32: with described photoresist for mask take Semiconductor substrate as cutoff layer, and the described polysilicon beyond etching grid region, silicon dioxide film, agraphitic carbon and thick grid oxygen, to form groove;
Step 33: in the described Semiconductor substrate in described groove and recess edge formed etching stop layer, and in described groove fill insulant formed separator.
5. the preparation method of HKMG device as claimed in claim 1, is characterized in that, in described step 5, adopts dry etch process to remove remaining silicon dioxide film and agraphitic carbon.
6. the preparation method of HKMG device as claimed in claim 1, it is characterized in that, when forming core voltage devices, described step 6 comprises: peel off and remove described thick grid oxygen, and deposit initial oxide layer successively on a semiconductor substrate, described initial oxide layer fills high-k dielectric layer, workfunction layers and metal gate material successively.
7. the preparation method of HKMG device as claimed in claim 1, is characterized in that, when forming I/O device, described step 6 comprises: on described thick grid oxygen, fill high-k dielectric layer, workfunction layers and metal gate material successively.
8. the preparation method of HKMG device as claimed in claims 6 or 7, is characterized in that, described metal gate material adopts aluminium, and described thick grid oxygen adopts silicon dioxide.
9. the preparation method of HKMG device as claimed in claim 1, is characterized in that, in described step 4, adopts dry etch process to remove the polysilicon layer of area of grid.
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| CN201510532382.7A CN105185713B (en) | 2015-08-26 | 2015-08-26 | A kind of preparation method of HKMG device |
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| CN201510532382.7A CN105185713B (en) | 2015-08-26 | 2015-08-26 | A kind of preparation method of HKMG device |
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| CN105185713B CN105185713B (en) | 2019-01-22 |
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|---|---|---|---|---|
| WO2004012256A1 (en) * | 2002-07-31 | 2004-02-05 | Advanced Micro Devices, Inc. | Process for manufacturing mosfets using amorphous carbon replacement gate and structures formed in accordance therewith |
| US7126198B2 (en) * | 2002-09-03 | 2006-10-24 | Agere Systems Inc. | Protruding spacers for self-aligned contacts |
| CN103390556A (en) * | 2012-05-08 | 2013-11-13 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN103794484A (en) * | 2012-11-05 | 2014-05-14 | 中国科学院微电子研究所 | Manufacturing method for dummy gate in gate-last process |
| CN103839808A (en) * | 2012-11-21 | 2014-06-04 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN104241109A (en) * | 2013-06-17 | 2014-12-24 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
-
2015
- 2015-08-26 CN CN201510532382.7A patent/CN105185713B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004012256A1 (en) * | 2002-07-31 | 2004-02-05 | Advanced Micro Devices, Inc. | Process for manufacturing mosfets using amorphous carbon replacement gate and structures formed in accordance therewith |
| US7126198B2 (en) * | 2002-09-03 | 2006-10-24 | Agere Systems Inc. | Protruding spacers for self-aligned contacts |
| CN103390556A (en) * | 2012-05-08 | 2013-11-13 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN103794484A (en) * | 2012-11-05 | 2014-05-14 | 中国科学院微电子研究所 | Manufacturing method for dummy gate in gate-last process |
| CN103839808A (en) * | 2012-11-21 | 2014-06-04 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN104241109A (en) * | 2013-06-17 | 2014-12-24 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
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