CN106531680A - Isolation structure and manufacturing method thereof - Google Patents
Isolation structure and manufacturing method thereof Download PDFInfo
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- CN106531680A CN106531680A CN201510569427.8A CN201510569427A CN106531680A CN 106531680 A CN106531680 A CN 106531680A CN 201510569427 A CN201510569427 A CN 201510569427A CN 106531680 A CN106531680 A CN 106531680A
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- Prior art keywords
- cushion
- insulating barrier
- lining
- isolation structure
- raceway groove
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
The invention provides an isolation structure and a manufacturing method thereof. The isolation structure comprises a buffer layer and a coating layer. The buffer layer is positioned in a channel of a base. The coating layer is positioned in the channel, and the buffer layer is coated with the coating layer in a surrounding manner, wherein the buffer layer is not exposed out and is not in contact with the channel, and the material of the buffer layer is different from that of the coating layer.
Description
Technical field
The invention relates to a kind of isolation structure and its manufacture method.
Background technology
It is integrated with semiconductor element, in order to reach high density and dynamical target, in system
During manufacturing semiconductor element, tendency manufactures the higher structure of less and integrated level.Therefore, isolation structure
Isolation effect affects to become big for the efficiency of semiconductor element.
In the manufacture process of semiconductor element, the isolation structure for being formed may be subject to subsequent technique
Impact and produce such as lattice mismatch (lattice dislocation) or bridge defects (bridge defect)
The problems such as, such issues that be probably cause semiconductor element produce leakage current the reason for one of.Therefore,
A kind of generation of the problems such as how forming isolation structure to reduce above-mentioned lattice mismatch or bridge defects, be
The problem of current desired research.
The content of the invention
The present invention provides a kind of isolation structure and its manufacture method, can reduce lattice mismatch or bridge defects
The generation of problem, and reach.
The present invention provides a kind of isolation structure.Isolation structure includes cushion and clad.Cushion position
In the raceway groove of substrate.During clad is located at raceway groove and around cladding cushion, wherein cushion is not naked
Expose and do not contact with raceway groove, and the material of cushion is different from clad.
In one embodiment of this invention, above-mentioned cushion is shaped as U-shaped or V-type.
In one embodiment of this invention, the material of above-mentioned cushion include silicon nitride, silicon oxynitride or
Its combination.
The present invention provides a kind of isolation structure.Isolation structure includes lining, cushion, the first insulating barrier
And second insulating barrier.Lining is located on the basal surface and side wall of the raceway groove of substrate.Cushion is located at lining
On the basal surface and partial sidewall of layer, another part side wall of wherein lining is exposed.First insulating barrier position
On the basal surface and side wall of cushion.Second insulating barrier is located at the top surface of the first insulating barrier, buffering
On another part side wall of the top surface and lining of layer.
In one embodiment of this invention, above-mentioned cushion is shaped as U-shaped or V-type.
In one embodiment of this invention, material stress of the material stress of above-mentioned cushion more than lining.
In one embodiment of this invention, the material of above-mentioned cushion include silicon nitride, silicon oxynitride or
Its combination.
The present invention provides a kind of manufacture method of isolation structure, and which comprises the following steps.The shape in substrate
Into raceway groove.Lining is formed, wherein lining covers the basal surface and side wall of raceway groove.Cushion is formed, its
Middle cushion covers the surface of lining.The first insulating barrier is formed, wherein the first insulating barrier covers cushion
Surface.The first insulating barrier of part and portion of buffer layer are removed, with the lining on the side wall of exposed raceway groove
Partial sidewall.The second insulating barrier is formed, wherein the top surface of the second insulating barrier the first insulating barrier of covering,
The partial sidewall of the top surface and lining of cushion.
In one embodiment of this invention, material stress of the material stress of above-mentioned cushion more than lining.
In one embodiment of this invention, the above-mentioned side for removing the first insulating barrier of part and portion of buffer layer
Method includes dry etching method, wet etching method or its combination.
Based on above-mentioned, the isolation structure that the present invention is formed is by the larger cushion of material stress in substrate
As stress-buffer layer (stress buffer layer) and insulating barrier between, can be in follow-up high-temperature technology
In avoid the insulating barrier volumetric expansion in raceway groove and cause the leakage phenomenon caused by malformation, and
As cushion can reduce the depth-to-width ratio of raceway groove, therefore can reach, and formed
Cushion can form suitable height, thickness and profile by the adjustment of technological parameter, it is to avoid bridge joint lacks
Sunken problem.Additionally, the semiconductor element with this isolation structure has more preferable electronics carrier movement
Rate (carrier mobility).Therefore, the electrical performance and process yields of semiconductor element can be lifted.
It is that the features described above and advantage of the present invention can be become apparent, special embodiment below, and match somebody with somebody
Close institute's accompanying drawings to be described in detail below.
Description of the drawings
Figure 1A to Fig. 1 G is the manufacture method according to the isolation structure depicted in embodiments of the invention
Generalized section.
Fig. 2 is the electric leakage current test of the isolation structure manufactured by experimental example and comparative example according to the present invention
Figure.
【Symbol description】
10、10a：Substrate
12、12a：Bed course
14、14a：Hard mask layer
15、15a、15b：Raceway groove
16：Lining
17：Clad
18、18a、18b、18c：Cushion
20、20a、20b、20c：First insulating barrier
22、22a：Second insulating barrier
100：Isolation structure
h、H：Highly
t：Thickness
w：Width
Specific embodiment
Figure 1A to Fig. 1 G is the manufacture method according to the isolation structure depicted in embodiments of the invention
Generalized section.
Figure 1A is refer to, substrate 10 is provided first, and is sequentially formed 12 He of bed course on the substrate 10
Hard mask layer 14.Substrate 10 may include semi-conducting material, insulating material, conductor material or above-mentioned
Any combination of material.The material of substrate 10 e.g. selected from Si, Ge, SiGe, GaP, GaAs,
Material that at least one material in the group constituted by SiC, SiGeC, InAs and InP is constituted or
Any physical arrangement for being suitable for present invention process.Substrate 10 includes single layer structure or sandwich construction.
In addition, it is possible to use silicon (silicon on insulator, SOI) substrate on insulating barrier.Substrate 10
Silicon or germanium silicide in this way.
The material of bed course 12 for example includes oxide, nitride, nitrogen oxides or its combination.Bed course
12 forming method is, for example, thermal oxidation method or chemical vapour deposition technique (CVD).Hard mask layer 14
Including single layer structure or sandwich construction.The material of hard mask layer 14 is different from bed course 12, hard mask layer
14 material is, for example, silica, silicon nitride or other suitable materials.Form hard mask layer 14
Method includes chemical vapour deposition technique.
Figure 1B is refer to, Patternized technique is carried out to hard mask layer 14 and bed course 12, and in base
Raceway groove 15 is formed in bottom 10.The method of Patternized technique is, for example, photoetching and etching method.Etching rule
Dry etching method in this way.Dry etching rule ise or reactive ion etching in this way.Raceway groove 15
Shape can be arbitrary shape, e.g. V-type, U-shaped, rhombus or its combination.
Figure 1B is continued referring to, lining 16 is formed on raceway groove 15, wherein lining 16 covers raceway groove
15 basal surface and side wall.In one embodiment, lining 16 only covers basal surface and the portion of raceway groove 15
Side wall, partial sidewall is divided to refer to the side wall of substrate 10a in raceway groove 15.That is, lining
Layer 16 does not cover the side wall of the bed course 12a and hard mask layer 14a in raceway groove 15.But this
Bright not limited to this.The material of lining 16 for example includes silica.The thickness of lining 16 be, for example, between
Between 10 angstroms to 1000 angstroms.The forming method of lining 16 is, for example, thermal oxidation method or chemical vapor deposition
Method.
Figure 1B and Fig. 1 C are refer to, cushion 18, wherein cushion 18 are formed in substrate 10a
Cover the surface of lining 16.In one embodiment, cushion 18 covers the surface of lining 16, ditch
The top surface of the residual surface and hard mask layer 14a in road 15.In one embodiment, cushion 18
Surface, the residual surface of raceway groove 15 and the hard mask layer 14a of lining 16 are conformally covered e.g.
Top surface.The residual surface of raceway groove 15 for example includes the bed course 12a in raceway groove 15 and covers firmly
The side wall of mold layer 14a.But the invention is not restricted to this.The material of cushion 18 can be any doing
For the material of stress buffer.In one embodiment, the material stress of cushion 18 is more than lining 16
Material stress.In certain embodiments, the material of cushion 18 for example includes silicon nitride, nitrogen oxidation
Silicon or its combination.Cushion 18 can be single layer structure or sandwich construction.Single layer structure can be single
One material is constituted, or a progressive layer.In an exemplary embodiment, cushion 18
Material stress near lining 16 to away from lining 16 in being incrementally incremented by.Implement in another demonstration
In example, cushion 18 is single layer structure, and the material of cushion 18 is, for example, silicon nitride.Show another
In model embodiment, cushion 18 is single layer structure, and is progressive layer, and wherein cushion 18 is near lining
The part of layer 16 is silicon oxynitride, and cushion 18 is gradually converted into nitrogen away from the part of lining 16
SiClx.In another exemplary embodiment, cushion 18 is, for example, sandwich construction, near lining 16
Cushion 18 is, for example, silicon oxynitride layer, is, for example, silicon nitride layer away from the cushion 18 of lining 16.
The forming method of cushion 18 is, for example, chemical vapour deposition technique.
Fig. 1 C are continued referring to, the first insulating barrier 20 is formed in substrate 10a, wherein the first insulation
Layer 20 covers the surface of cushion 18.The material of the first insulating barrier 20 for example includes oxide, rotation
Painting formula dielectric (spin-on dielectric, SOD) material or its combination.In an exemplary embodiment,
The material of the first insulating barrier 20 is, for example, silica.The thickness of the first insulating barrier 20 is for example between 500
Angstrom between 3500 angstroms.The forming method of the first insulating barrier 20 is, for example, high-density plasma chemical
Vapour deposition process (high density plasma chemical vapor deposition, HDP-CVD),
Spin-on-glass (spin on glass, SOG) or high-aspect-ratio fill out ditch technique (high aspect ratio
Process, HARP).The material of the first insulating barrier 20 is different from the material of cushion 18.First is exhausted
The material of edge layer 20 can be identical with the material of lining 16 or different.The material of the first insulating barrier 20
Consistency can be different from the consistency of the material of lining 16.In certain embodiments, the first insulating barrier
20 material is identical with the material of lining 16, but forming method is different.In an exemplary case, the
The film synthesis speed (sedimentation rate or growth rate) of one insulating barrier 20 is formed more than the film of lining 16
Speed.In an exemplary case, the first insulating barrier 20 is formed with chemical vapour deposition technique；Lining
16 are formed with thermal oxidation method.
Fig. 1 C and Fig. 1 D are refer to, technique is performed etching, to remove on the side wall of raceway groove 15a
The first insulating barrier 20 and portion of buffer layer 18, with the cushion 18b on the side wall of exposed raceway groove 15a
With the partial sidewall of lining 16.Etching technics for example include dry etching method, wet etching method or its
Combination.The etching gas of dry etching method for example include Nitrogen trifluoride (NF3).The quarter of wet etching method
Erosion liquid for example includes phosphoric acid (H3PO4), hydrofluoric acid (HF) or its combination.In one embodiment,
The etching technics of wet etching rule two-stage in this way.In an exemplary embodiment, the etching of two-stage
Technique can first carry out etching for the first time using hydrofluoric acid to remove on the side wall of raceway groove 15a
First insulating barrier 20, makes cushion 18 exposed out.The etching technics of two-stage then can be made again
Second etching is carried out with phosphoric acid, portion of buffer layer 18 is removed with the side wall of exposed raceway groove 15b
The partial sidewall of lining 16.The etching technics of two-stage can be by different etching liquid to cushion 18
It is different with the etching selection ratio of the first insulating barrier 20, reach the difference of side wall and bottom etching speed.
But the invention is not restricted to this.In another embodiment, first (can ascend the throne in the lower surface of raceway groove 15a
In the basal surface of the first insulating barrier 20 in raceway groove 15a) on form photoresist (not illustrating), then
Perform etching technique to remove the first insulating barrier 20 and partial buffer on the side wall of raceway groove 15a
Layer 18, finally removes photoresist again.
As shown in figure ip, cushion 18 it is above-mentioned remove step after can be divided into cushion 18a and slow
Rush layer 18b.Cushion 18a covers the top surface of the lining 16 positioned at raceway groove 15b bottoms and part side
Wall.Cushion 18b cover positioned at raceway groove 15b side wall on bed course 12a and hard mask layer 14a with
And the top surface of hard mask layer 14a.Gap between cushion 18a and cushion 18b exposes lining
The partial sidewall of layer 16.The shape of cushion 18a is, for example, U-shaped or V-type.But the present invention is not limited
In this.Additionally, the first insulating barrier 20 it is above-mentioned remove step after can also be divided into the first insulating barrier 20a
And the first insulating barrier 20b.First insulating barrier 20a is located at raceway groove 15b bottoms and covers cushion 18a.
First insulating barrier 20b covers cushion 18b.
It is noted that the height h of cushion 18a is (near the cushion of the side wall of raceway groove 15b
The height of 18a) can pass through to adjust the technological parameter or the above-mentioned step that removes for forming first insulating barrier 20
Technological parameter is come the height of the cushion 18a required for reaching.In one embodiment, cushion 18a
Near the top surface (i.e. two ends of the U-shaped or V-type of cushion 18a) of the side wall of raceway groove 15b
Less than the top surface of substrate 10a.In the case, as cushion 18a will not protrude substrate 10a
Top surface, therefore the generation of bridge defects problem can be avoided.
Fig. 1 E are refer to, the second insulating barrier 22 is formed in substrate 10a, the second insulating barrier 22 is covered
The partial sidewall of the top surface, the top surface of cushion 18a and lining 16 of the first insulating barrier 20a.
In one embodiment, the partial sidewall of lining 16 is above-mentioned to remove exposed part after step.
In another embodiment, the second insulating barrier 22 further includes the side wall and the first insulation for covering cushion 18b
The surface of layer 20b.But the invention is not restricted to this.In one embodiment, the second insulating barrier 22 is filled up
Raceway groove 15b.The material of the second insulating barrier 22 for example includes oxide, spun-on dielectric or its group
Close.In an exemplary embodiment, the material of the second insulating barrier 22 is, for example, silica.Second insulation
The thickness of layer 22 is for example between 2000 angstroms to 10000 angstroms.The formation side of the second insulating barrier 22
High density plasma CVD method, spin-on-glass or high-aspect-ratio fill out ditch to rule in this way
Technique.In one embodiment, the material of the material of the second insulating barrier 22 and the first insulating barrier 20 is identical.
In another embodiment, the material of the material of the second insulating barrier 22 and the first insulating barrier 20 is different.But
The invention is not restricted to this.
Fig. 1 F are refer to, the first insulating barrier 20b and the second insulating barrier of more than cushion 18b is removed
22, make the top surface and the cushion 18b for covering hard mask layer 14a of remaining second insulating barrier 22a
The substantial copline of top surface.But the invention is not restricted to this.Remove the first of more than cushion 18b
The method of insulating barrier 20b and the second insulating barrier 22 is, for example, flatening process.The side of flatening process
Rule chemical mechanical milling method (chemical mechanical polishing, CMP) in this way.
Fig. 1 G are refer to, hard mask layer 14a is removed, and remove the cushion 18b of more than bed course 12a,
Leave cushion 18c.In one embodiment, the top surface of the second insulating barrier 22a, cushion 18c
Top surface and bed course 12a the substantial non-co-planar of top surface, that is to say, that the second insulating barrier 22a
Top surface, cushion 18c top surface higher than bed course 12a top surface.But the invention is not restricted to
This.The method for removing hard mask layer 14a and cushion 18b is, for example, etching technics.Etching technics example
Wet etching method in this way.The etch liquids that wet etching method is used are, for example, hydrofluoric acid.
The structure of the isolation structure of the present invention is illustrated hereinafter with reference to Fig. 1 G.Such as Fig. 1 G institutes
Show, the isolation structure 100 of the present invention includes cushion 18a and clad 17.Cushion 18a is located at
In the raceway groove 15 of substrate 10a.During clad 17 is located at raceway groove 15 and around cladding cushion 18a,
Wherein cushion 18a is not exposed out and not to be contacted with raceway groove 15, and the material of cushion 18a with
Clad 17 is different.In one embodiment, clad 17 includes lining 16, the first insulating barrier again
20a and the second insulating barrier 22a.Lining 16 is located on the basal surface and side wall of raceway groove 15, wherein delaying
Rush layer 18a to be located on the basal surface and partial sidewall of lining 16, wherein another part side of lining 16
Wall is exposed.First insulating barrier 20a is on the basal surface and side wall of cushion 18a.Second insulating barrier
22a is located at the another of top surface, the top surface of cushion 18a and the lining 16 of the first insulating barrier 20a
In partial sidewall.
As shown in Figure 1 G, in one embodiment, (15 bottom of raceway groove is to base for the height H of raceway groove 15
The height of the top surface of bottom 12a) for example between 1000 angstroms to 10000 angstroms.In another enforcement
In example, height h (near the height of the cushion 18a of the side wall of the raceway groove 15) example of cushion 18a
Between 1500 angstroms to 3000 angstroms.In another embodiment, the thickness t examples of cushion 18a
Between 100 angstroms to 200 angstroms.In another embodiment, the width w of raceway groove 15 (is located at
Channel width between the top surface of substrate 12a) for example between 1800 angstroms to 3600 angstroms.But
The invention is not restricted to this.
In one embodiment, the proportionality of the thickness t of the height h and cushion 18a of cushion 18a
In this way between 10% to 90%.In another embodiment, the height h and raceway groove of cushion 18a
The ratio of 15 width w is, for example, between 20% to 90%.In another embodiment, buffer
The ratio of the width w of the thickness t and raceway groove 15 of layer 18a is, for example, between 10% to 90%.
But the invention is not restricted to this.
It is noted that the height of cushion, thickness and profile can be reached by the adjustment of parameter thinking
The scope wanted.For example, in certain scope, thickness more thickness is for lattice for the thickness of cushion
The problem of dislocation improves better.However, when the thickness of cushion exceedes certain scope, then may lead
The problem that ditch ability declines and causes bridge defects is filled out in cause.Further, since stress effect (stress effect)
With the impact of dimensional effect (dimension effect), the width of raceway groove can also affect the thickness of cushion
The improvement degree that the problems such as degree and height are for lattice mismatch or bridge defects occur.Therefore, the present invention
Can be by the height of the parameter adjustment cushion of above-mentioned technique, thickness and profile to optimal scope.
Fig. 2 is the electric leakage current test of the isolation structure manufactured by experimental example and comparative example according to the present invention
Figure.
Experimental example 1
According to the isolation structure that one embodiment of the invention is manufactured, which includes between substrate and insulating barrier
Above-mentioned lining and cushion.
Experimental example 2
It is similar to the isolation structure of above-mentioned experimental example 1, but the isolation structure of experimental example 2 substrate with it is exhausted
Only include above-mentioned lining between edge layer, not including cushion.
Comparative example 1
The isolation structure of manufacture method manufacture traditionally, which does not include between substrate and insulating barrier
Above-mentioned lining and cushion.
Fig. 2 is refer to, in the leakage current results such as Fig. 2 of experimental example 1, experimental example 2 and comparative example 1
Curve shown in.Isolation structure of the isolation structure of experimental example 1 and experimental example 2 compared to comparative example 1,
The leakage phenomenon of the former two is less, and wherein again with the leakage phenomenon of the isolation structure of experimental example 1
It is minimum.That is, the isolation structure including cushion between substrate and insulating barrier can reduce electric leakage
Flow phenomenon.Further, since the material stress of insulating barrier is larger relative to substrate, its compression is also larger.
The high pressure that insulating barrier can be eliminated by the isolation structure with lining between substrate and cushion should
Engage between power and then enhancement layer.Therefore including both lining and cushion between substrate and insulating barrier
Isolation structure can efficiently reduce leakage phenomenon.
The isolation structure and its manufacture method of the present invention can be applicable to any complementary metal-oxide half
The technique of conductor (CMOS) integrated circuit, and isolation structure may be, for example, isolation structure of shallow trench or
Deep trench isolation structure.But the present invention is not limited.
In sum, the isolation structure formed in the embodiment of the present invention, due in substrate and insulating barrier
Between there is the larger cushion of material stress as stress-buffer layer, therefore in follow-up high-temperature technology
In, such as hot tempering or thermal oxidation technology can avoid the insulating barrier volumetric expansion in raceway groove and cause knot
Leakage phenomenon caused by structure deformation.Again as cushion can reduce the depth-to-width ratio of raceway groove, thus it is reachable
To preferably filling out ditch ability.Additionally, the cushion of the present invention can be formed by the adjustment of parameter properly
Height, thickness and profile, thereby avoid the problem of bridge defects.Additionally, having this isolation structure
Semiconductor element there is more preferable electronics carrier mobility.Therefore, the electricity of semiconductor element can be lifted
Sex expression and process yields.
Although the present invention is disclosed above with embodiment, so which is not limited to the present invention, Ren Hesuo
Has usually intellectual in category technical field, without departing from the spirit and scope of the present invention, when can make
A little change and retouching, therefore protection scope of the present invention ought be defined depending on appended claims scope
Be defined.
Claims (10)
1. a kind of isolation structure, including：
One cushion, in a raceway groove of a substrate；And
One clad, in the raceway groove and around the cladding cushion, wherein the cushion
It is not exposed out and not contact with the raceway groove, and the material of the cushion is different from the clad.
2. isolation structure according to claim 1, wherein being shaped as the cushion is U-shaped
Or V-type.
3. isolation structure according to claim 1, wherein the material bag of the cushion
Include silicon nitride, silicon oxynitride or its combination.
4. a kind of isolation structure, including：
One lining, on the basal surface and side wall of a raceway groove of a substrate；
One cushion, on the basal surface and partial sidewall of the lining, wherein the lining is another
A part of side wall is exposed；
One first insulating barrier, on the basal surface and side wall of the cushion；And
One second insulating barrier, the top surface of top surface, the cushion positioned at first insulating barrier
On another part side wall of the lining.
5. isolation structure according to claim 4, wherein being shaped as the cushion is U-shaped
Or V-type.
6. isolation structure according to claim 4, wherein the material stress of the cushion is big
In the material stress of the lining.
7. isolation structure according to claim 4, wherein the material of the cushion includes nitrogen
SiClx, silicon oxynitride or its combination.
8. a kind of manufacture method of isolation structure, including：
A raceway groove is formed in a substrate；
A lining is formed, wherein the lining covers the basal surface and side wall of the raceway groove；
A cushion is formed, wherein the cushion covers the surface of the lining；
One first insulating barrier is formed, wherein first insulating barrier covers the surface of the cushion；
Part first insulating barrier and the part cushion are removed, with the side wall of the exposed raceway groove
On the lining partial sidewall；And
One second insulating barrier is formed, wherein second insulating barrier covers the top table of first insulating barrier
The partial sidewall of face, the top surface of the cushion and the lining.
9. the manufacture method of isolation structure according to claim 8, wherein the cushion
Material stress of the material stress more than the lining.
10. the manufacture method of isolation structure according to claim 8, wherein removing the part
The method of first insulating barrier and the part cushion includes dry etching method, wet etching
Method or its combination.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510569427.8A CN106531680A (en) | 2015-09-09 | 2015-09-09 | Isolation structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510569427.8A CN106531680A (en) | 2015-09-09 | 2015-09-09 | Isolation structure and manufacturing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108878421A (en) * | 2017-05-08 | 2018-11-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its manufacturing method |
| WO2023245760A1 (en) * | 2022-06-23 | 2023-12-28 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
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| US20110291204A1 (en) * | 2004-06-30 | 2011-12-01 | Fujitsu Semiconductor Limited | Semiconductor device having sti with nitride liner and uv light shielding film |
| US20140073111A1 (en) * | 2012-09-09 | 2014-03-13 | Te-Lin Sun | Method of Forming Isolation Structure |
| US20150118823A1 (en) * | 2013-10-31 | 2015-04-30 | Stmicroelectronics Sa | Method of stressing a semiconductor layer |
| US20150137263A1 (en) * | 2013-11-15 | 2015-05-21 | Jae-Hwan Lee | Semiconductor device having fin-type field effect transistor and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110291204A1 (en) * | 2004-06-30 | 2011-12-01 | Fujitsu Semiconductor Limited | Semiconductor device having sti with nitride liner and uv light shielding film |
| US20140073111A1 (en) * | 2012-09-09 | 2014-03-13 | Te-Lin Sun | Method of Forming Isolation Structure |
| US20150118823A1 (en) * | 2013-10-31 | 2015-04-30 | Stmicroelectronics Sa | Method of stressing a semiconductor layer |
| US20150137263A1 (en) * | 2013-11-15 | 2015-05-21 | Jae-Hwan Lee | Semiconductor device having fin-type field effect transistor and method of manufacturing the same |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108878421A (en) * | 2017-05-08 | 2018-11-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its manufacturing method |
| CN108878421B (en) * | 2017-05-08 | 2021-07-06 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method for manufacturing the same |
| WO2023245760A1 (en) * | 2022-06-23 | 2023-12-28 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
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Application publication date: 20170322 |