WO2003077306A1 - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
WO2003077306A1
WO2003077306A1 PCT/JP2003/002787 JP0302787W WO03077306A1 WO 2003077306 A1 WO2003077306 A1 WO 2003077306A1 JP 0302787 W JP0302787 W JP 0302787W WO 03077306 A1 WO03077306 A1 WO 03077306A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor substrate
semiconductor
protective film
mesa
electrode
Prior art date
Application number
PCT/JP2003/002787
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French (fr)
Japanese (ja)
Inventor
Hideyuki Andou
Original Assignee
Sankan Electric Co., Ltd.
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Publication date
Application filed by Sankan Electric Co., Ltd. filed Critical Sankan Electric Co., Ltd.
Priority to JP2003575416A priority Critical patent/JPWO2003077306A1/en
Publication of WO2003077306A1 publication Critical patent/WO2003077306A1/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/8613Mesa PN junction diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/868PIN diodes

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a mesa groove and a method for manufacturing the same.
  • annular inclined groove (mesa groove) along the outer peripheral surface of a semiconductor substrate to partition the semiconductor element and to make the semiconductor element have a relatively high breakdown voltage.
  • a mesa diode (a mesa diode) is cited.
  • Figure 4 shows a cross section of a general mesa diode.
  • the mesa diode 51 includes a semiconductor substrate 52, a force source electrode 53 formed on one main surface (upper surface) of the semiconductor substrate 52, and the other main surface (lower surface) of the semiconductor substrate. ) Formed on the anode electrode 54.
  • the semiconductor substrate 52 includes a P + -type semiconductor region 55 forming an anode region, and an n-type semiconductor region 56 and an n + -type semiconductor region 57 forming a force source region.
  • a mesa groove 58 is formed on the upper surface of the semiconductor substrate 52 so that the p + type semiconductor region 55, the n ⁇ type semiconductor region 56, the n + type semiconductor region 57, and the pn junction are exposed.
  • a protective film 59 made of glass or the like is formed on the surface of the mesa groove 58, and the semiconductor regions 55 to 57 exposed by the mesa groove 58 are covered with the protective film 59.
  • a mesa diode having such a configuration has been manufactured by, for example, a procedure described below.
  • the upper surface of the semiconductor substrate (semiconductor wafer) 52 on which the p + type semiconductor region 55, the n ⁇ type semiconductor region 56 and the n + type semiconductor region 57 are formed is etched to have a U-shaped cross section.
  • a mesa groove 58 is formed.
  • the applied glass is fired. This allows the glass film Is formed, and the upper surface of the semiconductor wafer 52 is covered with the formed glass film.
  • the glass film on the ⁇ + type semiconductor region 57 in the region where the force source electrode 53 is to be formed is removed by etching to form a protective film 59 covering the surface of the mesa groove 58.
  • an aluminum film is formed by vacuum evaporation or the like on the portion where the glass film has been removed by etching.
  • the surface of the aluminum film is etched to form a force source electrode 53 from the aluminum film.
  • titanium, nickel, palladium and silver are sequentially vacuum-deposited to form an anode electrode 54. Then, the semiconductor wafer 52 is diced along the mesa groove 58.
  • the protective film 59 covering the mesa groove 58 is liable to cause insulation rupture if the electrical and physical properties are not stable. For this reason, in the conventional manufacturing process, the glass applied to the mesa 58 is fired at, for example, about 700 ° C. to reduce the possibility of insulation rupture of the protective film 59, and the glass film (the protective film 5 9) to stabilize the characteristics of the protective film 59.
  • the material (for example, aluminum) constituting the force source electrode 53 may be deteriorated by heat.
  • the temperature at which the material of the force sword electrode 53 deteriorates is, for example, the melting point of the material. Since the melting point of the aluminum film constituting the power source electrode 53 is about 600 ° C., after forming an aluminum film on one main surface of the semiconductor substrate 52, the protective film 59 is formed by firing. When this is generated, the aluminum film is heated at a temperature higher than the melting point. At temperatures above the melting point, the aluminum film is susceptible to substantial damage. Therefore, in the conventional manufacturing process, a protective film 59 for covering the mesa groove 9 is formed first, and then a force source electrode 53 is formed in order to make the aluminum film hard to substantially damage.
  • the protective film 59 is formed on the entire upper surface of the semiconductor wafer 52 including the mesa groove 58, the protective film 59 in the area where the force electrode 53 is to be formed is etched. In some cases, the protective film 59 may remain on the edge of the region where the force source electrode 53 is to be formed. If the aluminum film forming the power source electrode 53 is formed on the area where the power source electrode 53 is to be formed while the protective film 59 remains, the aluminum film on the remaining protective film 59 protrudes. . In this case, the projection of the aluminum film hinders the etching of the surface of the aluminum film. Also, it is difficult to etch the protruding portion of the aluminum film so that the edge of the aluminum film and the edge of the mesa groove 58 are aligned in a cross section. For this reason, it was difficult to perform etching with high accuracy.
  • the present invention has been made in view of the above problems, and has as its object to provide a semiconductor element capable of improving productivity and a method for manufacturing the same. Disclosure of the invention
  • a method for manufacturing a semiconductor device includes a semiconductor substrate (2) and a semiconductor substrate (2) formed in a predetermined region on one main surface of the semiconductor substrate (2).
  • a metal film forming the electrode is formed in a predetermined region on one main surface of the semiconductor substrate (2).
  • the mesa groove (9) is formed along an outer periphery of a negative main surface of the semiconductor substrate (2), and the metal film ( 11. Cover the inner surface of the mesa groove (9) with a material that is cured by heat at a temperature lower than the temperature at which Forming the protective film (3), and dicing the semiconductor substrate (2) along the mesa groove (9) ′ covered with the protective film (3). It is characterized by. According to this configuration, after a metal film forming an electrode is formed in a predetermined region on one main surface of the semiconductor substrate, a groove is formed on one main surface of the semiconductor substrate, and the metal film is heated by heat.
  • a protective film covering the inner surface of the groove is formed from a material that cures at a temperature lower than the temperature at which substantial damage is caused. Therefore, it is not necessary to repeat the etching process a plurality of times to form the protective film and the metal film. Therefore, the manufacturing process of the semiconductor device can be simplified, and the productivity of the semiconductor device can be improved. Further, since the protective film is formed using a material that is cured by heat at a temperature lower than the temperature at which the metal film deteriorates, the formation of the protective film does not substantially damage the metal film.
  • the electrode (4) is formed using aluminum, and the electrode (4) is formed using a material that is cured by heat at a temperature of 100 ° C. to 400 ° C. lower than the melting point of aluminum-palladium.
  • a protective film (3) may be formed.
  • a semiconductor element in order to solve the above problem so as to form the protective film (3) from a polyimide resin, includes a semiconductor substrate (2), A first electrode (4) formed on a predetermined area on one main surface of the semiconductor substrate (2), and a second electrode (5) formed on the other main surface of the semiconductor substrate (2).
  • the first electrode (4) is composed of a metal film (1 1)
  • the protective film (3) is composed of the metal film (1 1). It is characterized by comprising a material that is cured by heat at a temperature lower than the temperature at which it deteriorates.
  • the protective film is made of a material that is cured by heat at a temperature lower than the temperature at which the metal film deteriorates, substantial damage to the electrodes is caused when the protective film is formed. Will not give.
  • the protective film can be formed after the electrode is formed, and it is not necessary to repeat a plurality of etching steps to form the protective film and the electrode. Therefore, the manufacturing process of the semiconductor device can be simplified, and the productivity of the semiconductor device can be improved.
  • the mesa groove (9) is formed by etching one main surface of the semiconductor substrate (2) using the metal film (11) constituting the first electrode (4) as a mask. It may be formed.
  • the semiconductor substrate (2) has a second conductivity type second semiconductor region in which an interface between a first conductivity type first semiconductor region (6) and the first five semiconductor region (6) forms a pn junction. (7) and a third conductive type third semiconductor region (8) in contact with the second semiconductor region (7) and having a higher concentration than the second semiconductor region (7).
  • the protective film (3) may be made of a material which is cured by heat at a temperature lower by 1100 ° C. to 400 ° C. than a melting point of the metal film constituting the first electrode (4).
  • the first electrode (4) may be made of aluminum, and the protective film (3) may be made of a material which is cured by heat at 200 to 500 ° C.
  • the protective film (3) may be made of polyimide resin.
  • FIG. 1 is a cross-sectional view showing a configuration of a mesa-type diode according to an embodiment of the present invention.
  • 2 (a) to 2 (g) are cross-sectional views for explaining a manufacturing process of the mesa diode according to the embodiment of the present invention.
  • FIG. 3 is a cross-sectional view showing a modification of the semiconductor device according to the embodiment of the present invention.
  • FIG. 4 is a cross-sectional view showing a configuration of a conventional mesa diode.
  • the mesa diode 1 has a semiconductor substrate 2 and a protective film 3 , A power source electrode 4 and an anode electrode 5.
  • the semiconductor substrate 2 includes a first semiconductor region 6, a second semiconductor region 7, and a third semiconductor region 8. A portion of the semiconductor substrate 2 excluding the second semiconductor region 7 and the third semiconductor region 8 constitutes a first semiconductor region 6.
  • the first semiconductor region 6 is formed of a semiconductor region of a first conductivity type, for example, ap + type, and functions as a cathode region.
  • the first semiconductor region 6 has 30 ⁇ ! The thickness is about 300 ⁇ m.
  • the first semiconductor region 6 is formed on the impurity concentration of about 1 X 1 0 16 cm one 3 ⁇ 1 X 1 0 21 cm- 3.
  • the second semiconductor region 7 is formed on one main surface of the first semiconductor region 6.
  • the second semiconductor region 7 is composed of a semiconductor region of the second conductivity type, for example, n-type.
  • the second semiconductor region 7 is formed with a thickness of about 10 / Xm to 200 m.
  • the second semiconductor region 7 is formed with an impurity concentration of about 1 ⁇ 10 12 cm— 3 to 1 ⁇ 10 18 cm— 3 . Therefore, the semiconductor substrate 2 has a pn junction formed at the interface between the second semiconductor region 7 and the first semiconductor region 6.
  • the third semiconductor region 8 is formed on the upper surface of the second semiconductor region 7.
  • the third semiconductor region 8 is formed of an n + -type semiconductor region having an n-type impurity concentration higher than that of the second semiconductor region 7, and functions as an anode region.
  • the third semiconductor region 8 is formed to a thickness of about 50 ⁇ to 300 / m.
  • the third semiconductor region 8 is formed on the impurity concentration of about l X 1 0 17 cm one 3 ⁇ 1 X 1 0 22 cm- 3. '
  • an inclined groove (mesa groove) 9 is formed on the upper surface of the semiconductor substrate 2.
  • the mesa groove 9 is formed in an annular shape along the outer peripheral edge of the semiconductor substrate 2.
  • the mesa groove 9 has a depth such that the first semiconductor region 6 is exposed at the bottom surface. Therefore, the third semiconductor region 8, the second semiconductor region 7, and the first semiconductor region 6 are exposed from the side and bottom surfaces of the mesa groove 9, and the pn junction between the first semiconductor region 6 and the second semiconductor region 7 is further increased. The edge is exposed.
  • the mesa groove 9 is formed in a shape inclined from the upper surface of the semiconductor substrate 2 toward the lower surface (other surface), for example, so that the upper surface side of the semiconductor substrate 2 has a reduced diameter (a divergent shape). Therefore, the mesa diode 1 has a substantially trapezoidal shape as shown in FIG.
  • the protective film 3 includes the first semiconductor region 6, the second semiconductor region 7, ⁇ Formed on the side and bottom surfaces of the mesa groove 9 so as to cover the third semiconductor region 8.
  • the protective film 3 is made of a material that cures at a lower temperature than the material constituting the cathode electrode 4 is deteriorated by heat.
  • the temperature at which the material of the cathode electrode 4 deteriorates is, for example, the melting point of the material. Therefore, it is preferable that the protective film 3 be made of a material that is cured by heat at a temperature lower by 100 ° C. to 400 ° C. than the melting point of the material forming the force source electrode 4.
  • the protective film 3 may be made of a polyimide resin.
  • the polyimide resin undergoes heat treatment at a temperature lower than the melting point of aluminum (about 600 ° C) (about 200 ° C to 500 ° C), and the solvent contained in the resin volatilizes and shrinks. Can be heat cured. Further, the polyimide resin can form a relatively hard and dense resin film by thermosetting at a temperature of 200 ° C. to 50 ° C. Therefore, when the polyimide resin is used as the material of the protective film 3, the aluminum film forming the cathode electrode 4 is not substantially damaged by heat. For this reason, in the present embodiment, a polyimide resin is used as the material of the protective film 3.
  • Force sword electrode 4 is made of a metal film such as an aluminum film. Force sword electrode 4 is formed on one main surface of semiconductor substrate 2.
  • the anode electrode 5 is composed of, for example, a metal film on which titanium, nickel, palladium and silver are sequentially deposited.
  • the anode electrode 5 is formed on the other main surface of the semiconductor substrate 2.
  • an n_ type semiconductor region (second semiconductor region 7) and a p + type semiconductor substrate 2 are formed by an epitaxial growth method, a thermal diffusion method, or the like.
  • An n + type semiconductor region (third semiconductor region 8) is formed.
  • the portion of the semiconductor substrate 2 excluding the second semiconductor region 7 and the third semiconductor region 8 constitutes the first semiconductor region 6.
  • the thicknesses of the first semiconductor region 6, the second semiconductor region 7, and the third semiconductor region 8 are 100 // ⁇ , 40 m, and ⁇ ⁇ ⁇ , respectively.
  • an aluminum film '11 is formed on one main surface of the semiconductor substrate 2 by vacuum evaporation or the like.
  • This aluminum film 11 constitutes a force source electrode 4 to be formed later.
  • the thickness of aluminum film 11 is set to 8 ⁇ m.
  • the aluminum film 12 is for preventing the other main surface of the first semiconductor region 6 from being contaminated when a tape member described later is attached to the other main surface of the first semiconductor region 6. is there.
  • the thickness of the aluminum film 12 is preferably about 1 // m to l0. In the present embodiment, the thickness is, for example, 2 ⁇ m.
  • an acid-resistant ink is printed on the aluminum film 11 using a screen technique using a nylon mesh mask or the like, thereby forming an etching mask on the aluminum film 11 as shown in FIG. 2 (c).
  • the etching mask 13 has an opening 13 a at a portion corresponding to a region where a mesa groove 9 is to be formed (a region where a mesa groove is to be formed). 3A is exposed through.
  • the opening 13. A is formed in the form of a stitch on the main surface of the semiconductor substrate 2 when viewed two-dimensionally. For this reason, the etching mask 13 is formed in an island shape on one main surface of the semiconductor substrate 2.
  • etching mask 13 As a mask, as shown in FIG. 2D, a portion of the aluminum film 11 corresponding to the opening 13a not covered with the etching mask 13 Is etched. That is, a portion of the aluminum film 11 corresponding to the region where the mesa groove is to be formed is removed. Aqua Regie was used as the etching solution for aluminum.
  • a tape member 14 is attached to the lower surface of the aluminum film 12 (the surface not in contact with the other main surface of the semiconductor substrate 2).
  • the etching mask 13 and the aluminum film 11 are used as masks.
  • the region where the mesa groove is to be formed is etched through the opening 13a to form a mesa groove 9 having a U-shaped cross section as shown in FIG. 2 (e).
  • the mesa groove 9 is formed in an annular shape along the outer peripheral edge of the semiconductor substrate 2 when viewed in plan.
  • a mixed solution of nitric acid, hydrofluoric acid, acetic acid and sulfuric acid was used as an etching solution.
  • the depth of the mesa groove 9 is set to 1605 / zm.
  • the third semiconductor region 8, the second semiconductor region 7, the first semiconductor region 6, and the pn junction between the second semiconductor region 7 and the first semiconductor region 6 are exposed on the side surfaces of the mesa groove 9.
  • the first semiconductor region 6 having a thickness of 80 m remains on the bottom surface of the mesa groove 9.
  • the portion of the aluminum film 11 shown in FIG. Is removed by etching so that the edge of the aluminum film 11 and the edge of the mesa groove 9 are aligned in a cross section as shown in FIG. 2 (f).
  • the etching mask 13 formed on the force source electrode 4 is removed.
  • the tape member 14 attached to the lower surface of the aluminum film 12 is removed.
  • the protective film 3 is formed so as to cover the inner surface of the mesa groove 9. If, for example, a polyimide resin is used as the material of the protective film 3, the protective film 3 can be formed at a temperature of about 200 ° C. to 500 ° C.
  • a fluid polyimide resin is applied to the inner surface of the mesa groove 9 using a dispenser type applicator or the like.
  • the resin is subjected to a heat treatment at 350 ° C. for 60 minutes for 20 minutes.
  • the polyimide-based resin is heat-treated at a temperature of about 200 ° C. to 500 ° C. to evaporate a solvent contained in the resin and promote imide bond of the resin, thereby obtaining a relatively hard and dense resin.
  • a film (protective film 3) is formed.
  • the surface of the aluminum film 11 is lightly etched to form a force source electrode 4 composed of the aluminum film 11.
  • the aluminum film 12 is removed, and titanium, nickel, palladium and silver are sequentially vacuum-deposited on the other main surface of the semiconductor substrate 2 to form the anode electrode 5.
  • the semiconductor substrate 2 is formed along the mesa groove 9. Dicing.
  • the mesa diode 1 of the present embodiment is formed.
  • semiconductor substrate 2 is etched using aluminum film 11 as a mask, and A groove 9 is formed. This eliminates the need to repeat a plurality of etching steps as in the prior art, in order to form the protective film 3 and the cathode electrode 4.
  • the protective film 3 is formed after the aluminum film 11 is formed, there is a problem that the protective film 3 remains on the edge of the region where the force source electrode is to be formed as in the related art. Will not occur. Since the aluminum film 11 can be formed first, the edge of the aluminum film 11 and the edge of the mesa groove 9 are easily aligned by etching as described above. For this reason, in the present embodiment, etching for forming the force sword electrode 4 can be performed more accurately than in the conventional technique.
  • protective film 3 covering mesa groove 9 is formed by heat at a temperature lower than the temperature at which aluminum film 11 constituting force source electrode 4 deteriorates. For this reason, in the present embodiment, the heat hardly causes substantial damage to the aluminum film 11.
  • the present invention is not limited to the above-described embodiment, and various modifications and applications are possible.
  • the temperature at which the metal film forming the force source electrode 4 is degraded by heat has been described by taking the melting point as an example.
  • the temperature at which the metal film is degraded by heat is not limited to the melting point, but may be any temperature that substantially changes the properties (eg, resistivity) of the metal film.
  • the material is not limited to this, and any material may be used as the material of the protective film 3 as long as the material of the force source electrode 4 can be formed at a temperature lower than the temperature at which the film quality of the material changes. That is, if the material of the protective film 3 can be heat-treated at a temperature that does not cause substantial damage to the material constituting the force source electrode 4, Anything is fine. In this case, the material forming the protective film 3 may be appropriately changed depending on the material forming the force source electrode 4.
  • the case where the tape member 14 (and the aluminum film 12) is formed on the other main surface of the first semiconductor region 6 has been described as an example, but the tape member 14 (and the aluminum film 1 2) need not be formed.
  • the manufacturing process of the mesa-type diode 1 can be simplified as compared with the above-described embodiment, and a mesa-type diode with further improved productivity can be provided.
  • the case where the polyimide resin is applied to the mesa groove 9 using the dispenser type applicator has been described as an example, but the present invention is not limited to this, and various methods may be used. A polyimide resin may be applied to the mesa groove 9 without any problem.
  • the semiconductor element of the above embodiment is not limited to the mesa diode, but may be any other mesa semiconductor element such as a mesa transistor.
  • the mesa transistor may have the configuration shown in FIG. 3, for example.
  • the illustrated mesa transistor la has the same configuration as that shown in FIG. 1 except for the p-type semiconductor region 21 and the n-type semiconductor region 22.
  • the aluminum film 11 constituting the cathode electrode 4 is formed on one main surface of the semiconductor substrate 2 by vacuum evaporation.
  • the present invention is not limited to this.
  • the aluminum film 11 may be formed on one main surface of the semiconductor substrate 2 by sputtering.
  • the present invention can be used for a mesa type semiconductor device.

Abstract

A mesa diode (1) comprises a semiconductor substrate (2), a protection film (3), a cathode electrode (4), and an anode electrode (5). A mesa groove (9) is formed in one main face of the semiconductor substrate (2) by etching using a metal film constituting the cathode electrode (4) as a mask. The mesa groove (9) is annularly formed along the edge of the semiconductor substrate (2). The protection film (3) is constituted of a fluid polyimide resin volatilizing at a temperature lower than the melting point of the material constituting the cathode electrode (4), cures, and coats the bottom and side of the mesa groove (9). The cathode electrode (4) is formed on one main face of the semiconductor substrate (2). The anode electrode (5) is formed on the other main face of the semiconductor substrate (2).

Description

• 明細書 半導体素子及びその製造方法 技術分野 . ' 本発明は、 半導体素子及びその製造方法に関し、 特に、 メサ溝を有する半導体 素子およびその製造方法に関する。 背景技術  TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a mesa groove and a method for manufacturing the same. Background art
半導体基板の外周面に沿って環状の傾斜溝 (メサ溝) を形成して、 半導体素子 を区画するとともに半導体素子を比較的高耐圧化する手法が知られている。 この ような手法によって製造される半導体素子としては、 例えば、 メサダイオード ( メサ型ダイオード) が挙げられる。 図 4に一般的なメサ型ダイオードの断面を示 す。  It is known to form an annular inclined groove (mesa groove) along the outer peripheral surface of a semiconductor substrate to partition the semiconductor element and to make the semiconductor element have a relatively high breakdown voltage. As a semiconductor element manufactured by such a method, for example, a mesa diode (a mesa diode) is cited. Figure 4 shows a cross section of a general mesa diode.
図示するように、 メサ型ダイオード 5 1は、 半導体基板 5 2と、 半導体基板 5 2の一方の主面 (上面) に形成された力ソード電極 5 3と、 半導体基板の他方の 主面 (下面) に形成されたアノード電極 5 4とを備える。 半導体基板 5 2は、 ァ ノード領域を構成する P +型半導体領域 5 5と、 力ソード領域を構成する n一型半 導体領域 5 6及び n +型半導体領域 5 7とを備える。 半導体基板 5 2の上面には、 p +型半導体領域 5 5、 n—型半導体領域 5 6、 n +型半導体領域 5 7、 及び p n接 合が露出するように、 メサ溝 5 8が形成される。 メサ溝 5 8の表面には、 ガラス 等から構成される保護膜 5 9が形成され、. メサ溝 5 8によって露出した半導体領 域 5 5〜5 7が保護膜 5 9によって被覆されている。 As shown in the figure, the mesa diode 51 includes a semiconductor substrate 52, a force source electrode 53 formed on one main surface (upper surface) of the semiconductor substrate 52, and the other main surface (lower surface) of the semiconductor substrate. ) Formed on the anode electrode 54. The semiconductor substrate 52 includes a P + -type semiconductor region 55 forming an anode region, and an n-type semiconductor region 56 and an n + -type semiconductor region 57 forming a force source region. A mesa groove 58 is formed on the upper surface of the semiconductor substrate 52 so that the p + type semiconductor region 55, the n − type semiconductor region 56, the n + type semiconductor region 57, and the pn junction are exposed. You. A protective film 59 made of glass or the like is formed on the surface of the mesa groove 58, and the semiconductor regions 55 to 57 exposed by the mesa groove 58 are covered with the protective film 59.
このような'構成のメサ型ダイオードは、 従来、 例えば以下に説明するような手 順で製造されていた。  Conventionally, a mesa diode having such a configuration has been manufactured by, for example, a procedure described below.
まず、 p +型半導体領域 5 5、 n—型半導体領域 5 6及ぴ n +型半導体領域 5 7が 形成された半導体基板 (半導体ウェハ) 5 2の上面をエッチングし、 断面が U字 形状のメサ溝 5 8を形成する。 次に、 メサ溝 5 8を含む半導体ウェハ 5 2の上面 全体にガラスを塗布した後、 塗布したガラスを焼成する。 これによつてガラス膜 が形成されるとともに、 半導体ウェハ 5 2の上面が、 形成されたガラス膜で被覆 される。 First, the upper surface of the semiconductor substrate (semiconductor wafer) 52 on which the p + type semiconductor region 55, the n type semiconductor region 56 and the n + type semiconductor region 57 are formed is etched to have a U-shaped cross section. A mesa groove 58 is formed. Next, after applying glass to the entire upper surface of the semiconductor wafer 52 including the mesa groove 58, the applied glass is fired. This allows the glass film Is formed, and the upper surface of the semiconductor wafer 52 is covered with the formed glass film.
続いて、 η +型半導体領域 5 7上の、 力ソード電極 5 3形成予定領域のガラス膜 をエッチングして除去し、 メサ溝 5 8の表面を被覆する保護膜 5 9を形成する。 次に、 エッチングによってガラス膜を除去した部分に、 真空蒸着等により、 例え ばアルミニウム膜を形成する。 アルミニウム膜の表面をエッチングして、 アルミ ニゥム膜から力ソード電極 5 3を形成する。 また、 半導体ウェハ 5 2の下面に、 例えば、 チタン、 ニッケル、 パラジウム及ぴ銀を順次真空蒸着し、 アノード電極 5 4を形成する。 そして、 メサ溝 5 8に沿って半導体ウェハ 5 2をダイシングす る。 Subsequently, the glass film on the η + type semiconductor region 57 in the region where the force source electrode 53 is to be formed is removed by etching to form a protective film 59 covering the surface of the mesa groove 58. Next, for example, an aluminum film is formed by vacuum evaporation or the like on the portion where the glass film has been removed by etching. The surface of the aluminum film is etched to form a force source electrode 53 from the aluminum film. Further, on the lower surface of the semiconductor wafer 52, for example, titanium, nickel, palladium and silver are sequentially vacuum-deposited to form an anode electrode 54. Then, the semiconductor wafer 52 is diced along the mesa groove 58.
メサ溝 5 8を被覆する保護膜 5 9は、'電気的 ·物性的な特性が安定していない と、 絶縁破壌等を起こしやすい。 このため、 従来の製造工程では、 保護膜 5 9の 絶縁破壌等を起こりにくくするため、 メサ瑋 5 8に塗布したガラスを例えば 7 0 0 °C程度で焼成してガラス膜 (保護膜 5 9 ) を生成し、 保護膜 5 9の特性を安定 させていた。  The protective film 59 covering the mesa groove 58 is liable to cause insulation rupture if the electrical and physical properties are not stable. For this reason, in the conventional manufacturing process, the glass applied to the mesa 58 is fired at, for example, about 700 ° C. to reduce the possibility of insulation rupture of the protective film 59, and the glass film (the protective film 5 9) to stabilize the characteristics of the protective film 59.
このような温度では、 力ソード電極 5 3を構成する材料 (例えばアルミニウム ) が熱によって劣化する恐れがある。 力ソード電極 5 3の材料が劣化する温度と しては、 例えば材料の融点が挙げられる。 力ソード電極 5 3を構成するアルミ二 ゥム膜の融点が 6 6 0 °C程度のため、 半導体基板 5 2の一方の主面にアルミユウ 'ム膜を形成した後に、 焼成によって保護膜 5 9を生成すると、 アルミニウム膜が 融点以上の温度で加熱されてしまう。 融点以上の温度になると、 アルミニウム膜 は実質的なダメージ等を受けやすい。 そこで、 従来の製造工程では、 アルミユウ ム膜に実質的なダメージを与えにくくするため、 メサ溝 9を被覆する保護膜 5 9 をまず形成し、 次に力ソード電極 5 3を形成している。  At such a temperature, the material (for example, aluminum) constituting the force source electrode 53 may be deteriorated by heat. The temperature at which the material of the force sword electrode 53 deteriorates is, for example, the melting point of the material. Since the melting point of the aluminum film constituting the power source electrode 53 is about 600 ° C., after forming an aluminum film on one main surface of the semiconductor substrate 52, the protective film 59 is formed by firing. When this is generated, the aluminum film is heated at a temperature higher than the melting point. At temperatures above the melting point, the aluminum film is susceptible to substantial damage. Therefore, in the conventional manufacturing process, a protective film 59 for covering the mesa groove 9 is formed first, and then a force source electrode 53 is formed in order to make the aluminum film hard to substantially damage.
しかし、 このような手順の製造方法では、 保護膜 5 9とカソード電極 5 3とを 形成する際に、 複数回のエッチング工程が必要なので、 製造工程が比較的煩雑で あった。 また、 コストの削減等を図りにくかった。  However, in the manufacturing method of such a procedure, a plurality of etching steps are required when forming the protective film 59 and the cathode electrode 53, so that the manufacturing process is relatively complicated. It was also difficult to reduce costs.
また、.保護膜 5 9を、 メサ溝 5 8を含む半導体ウェハ 5 2の上面全体に形成し た後に、 力ソード電極 5 3形成予定領域の保護膜 5 9をエッチングしているので 、 力ソード電極 5 3形成予定領域の縁に保護膜 5 9が残存してしまう場合があつ た。 保護膜 5 9が残存した状態で、 力ソード電極 5 3を構成するアルミニウム膜 を力ソード電極 5 3形成予定領域上に形成すると、 残存した保護膜 5 9上のアル ミニゥム膜が突起してしまう。 この場合、 アルミニウム膜の突起部が妨げとなつ て、 アルミニウム膜の表面をエッチングしにくい。 また、 断面で見て、 アルミ二 ゥム膜の縁とメサ溝 5 8の縁とが揃うようにアルミニウム膜の突出部をエツチン グしにくレ、。 このため、 エッチングを精度良く行うことが困難であった。 Also, since the protective film 59 is formed on the entire upper surface of the semiconductor wafer 52 including the mesa groove 58, the protective film 59 in the area where the force electrode 53 is to be formed is etched. In some cases, the protective film 59 may remain on the edge of the region where the force source electrode 53 is to be formed. If the aluminum film forming the power source electrode 53 is formed on the area where the power source electrode 53 is to be formed while the protective film 59 remains, the aluminum film on the remaining protective film 59 protrudes. . In this case, the projection of the aluminum film hinders the etching of the surface of the aluminum film. Also, it is difficult to etch the protruding portion of the aluminum film so that the edge of the aluminum film and the edge of the mesa groove 58 are aligned in a cross section. For this reason, it was difficult to perform etching with high accuracy.
従って、 従来の製造方法では、 メサ型ダイオードの高い生産性を得られなかつ た。  Therefore, high productivity of the mesa diode cannot be obtained by the conventional manufacturing method.
一方、 アルミニウム膜をまず半導体基板 2上に形成した後に保護膜を形成する と、 アルミニウム膜にダメージを与えないように、 アルミニウム膜が劣化する温 度以下の温度でガラスを焼成して保護膜 5 9を生成しなくてはならない。 このた め、 特性の安定した保護膜 5 9を得られない。  On the other hand, if an aluminum film is first formed on the semiconductor substrate 2 and then a protective film is formed, glass is baked at a temperature lower than the temperature at which the aluminum film deteriorates so as not to damage the aluminum film. 9 must be generated. Therefore, a protective film 59 having stable characteristics cannot be obtained.
本発明は、 上記問題に鑑みてなされたものであり、 生産性を向上させることが できる半導体素子及びその製造方法を提供することを目的とする。 発明の開示  The present invention has been made in view of the above problems, and has as its object to provide a semiconductor element capable of improving productivity and a method for manufacturing the same. Disclosure of the invention
上記目的を達成するため、 本発明の第 1の観点にかかる半導体素子の製造方法 は、 半導体基板 (2 ) と、 前記半導体基板 (2 ) の一方の主面の所定の領域に形 成された電極 (4 ) と、 前記半導体基板 (2 ) の一方の主面の外周に沿って該半 『導体基板 (2 ) に形成されたメサ溝 (9 ) と、 前記メサ溝 (9 ) の内面を被覆す る保護膜 (.3 ) とを備えるメサ形状の半導体素子 (1 ) の製造方法において、 前 記半導体基板 (2 ) の一方の主面の所定の領域に、 前記電極を構成する金属膜 ( 1 1 ) を形成し、 前記金属膜 (1 1 ) をマスクとして、 前記半導体基板 (2 ) の —方の主面の外周に沿って前記メサ溝 (9 ) を形成し、 前記金属膜 (1 1 ) が劣 化する温度よりも低い温度の熱によって硬化する材料を用いて、 前記メサ溝 (9 ) の内面を被覆するように前記保護膜 (3 ) を形成し、 前記保護膜 (3 ) によつ て被覆された前記メサ溝 (9 )' に沿って前記半導体基板 (2 ) をダイシングする 、 ことを含んでいることを特徴とする。 この構成によれば、 半導体基板の一方の主面の所定の領域に電極を構成する金 属膜が形成された後、 半導体基板の一方の主面に溝が形成され、 金属膜が熱によ つて実質的なダメージを受ける温度よりも低い温度で硬化する材料から溝の内面 を被覆する保護膜が形成される。 このため、 保護膜及び金属膜を形成するために 複数回のエッチング工程を繰り返す必要がなくなる。 従って、 半導体素子の製造 工程を簡略化することができ、 半導体素子の生産性を向上させることができる。 また、 金属膜が劣化する温度よりも低い温度の熱によって硬化する材料を用いて 保護膜を形成しているので、 保護膜を形成によって金属膜に実質的なダメージを 与えない。 In order to achieve the above object, a method for manufacturing a semiconductor device according to a first aspect of the present invention includes a semiconductor substrate (2) and a semiconductor substrate (2) formed in a predetermined region on one main surface of the semiconductor substrate (2). An electrode (4), a mesa groove (9) formed on the semiconductive substrate (2) along the outer periphery of one main surface of the semiconductor substrate (2), and an inner surface of the mesa groove (9). In a method of manufacturing a mesa-shaped semiconductor element (1) having a protective film (.3) to cover, a metal film forming the electrode is formed in a predetermined region on one main surface of the semiconductor substrate (2). (11) is formed, and using the metal film (11) as a mask, the mesa groove (9) is formed along an outer periphery of a negative main surface of the semiconductor substrate (2), and the metal film ( 11. Cover the inner surface of the mesa groove (9) with a material that is cured by heat at a temperature lower than the temperature at which Forming the protective film (3), and dicing the semiconductor substrate (2) along the mesa groove (9) ′ covered with the protective film (3). It is characterized by. According to this configuration, after a metal film forming an electrode is formed in a predetermined region on one main surface of the semiconductor substrate, a groove is formed on one main surface of the semiconductor substrate, and the metal film is heated by heat. Thus, a protective film covering the inner surface of the groove is formed from a material that cures at a temperature lower than the temperature at which substantial damage is caused. Therefore, it is not necessary to repeat the etching process a plurality of times to form the protective film and the metal film. Therefore, the manufacturing process of the semiconductor device can be simplified, and the productivity of the semiconductor device can be improved. Further, since the protective film is formed using a material that is cured by heat at a temperature lower than the temperature at which the metal film deteriorates, the formation of the protective film does not substantially damage the metal film.
前記の製造方法では、 アルミニウムを用いて前記電極 (4 ) を形成し、 アルミ -ゥムの融点よりも 1 0 0 °C〜4 0 0 °C低い温度の熱によって硬化する材料を用 いて前記保護膜 (3 ) を形成するようにしてもよレ、。  In the above manufacturing method, the electrode (4) is formed using aluminum, and the electrode (4) is formed using a material that is cured by heat at a temperature of 100 ° C. to 400 ° C. lower than the melting point of aluminum-palladium. A protective film (3) may be formed.
前記の製造方法では、 ポリイミ ド系樹脂から前記保護膜 (3 ) を形成するよう 前記の課題を解決するため、 本発明の第 2の観点に係る半導体素子は、 半導体 基板 (2 ) と、 前記半導体基板 (2 ) の一方の主面の所定の領域に形成された第 1の電極 (4 ) と、 前記半導体基板 (2 ) の他方の主面に形成された第 2の電極 ( 5 ) と、 前記半導体基板 (2 ) の一方の主面の外周に沿って該半導体基板 (2 ) に形成されたメサ溝 (9 ) と、 前記メサ溝 (9 ) の内面を被覆する保護膜 (3) と、 を備えるメサ型の半導体素子 (1 ) .において、 前記第 1の電極 (4 ) は、 金属膜 (1 1 ) から構成され、 前記保護膜 (3 ) は、 前記金属膜 (1 1 ) が劣化 する温度よりも低い温度の熱によって硬化する材料から構成される、 とを特徴 とする。  In the above manufacturing method, in order to solve the above problem so as to form the protective film (3) from a polyimide resin, a semiconductor element according to a second aspect of the present invention includes a semiconductor substrate (2), A first electrode (4) formed on a predetermined area on one main surface of the semiconductor substrate (2), and a second electrode (5) formed on the other main surface of the semiconductor substrate (2). A mesa groove (9) formed in the semiconductor substrate (2) along an outer periphery of one main surface of the semiconductor substrate (2); and a protective film (3) covering an inner surface of the mesa groove (9). In the mesa-type semiconductor device (1) having the following, the first electrode (4) is composed of a metal film (1 1), and the protective film (3) is composed of the metal film (1 1). It is characterized by comprising a material that is cured by heat at a temperature lower than the temperature at which it deteriorates.
この構成によれば、 保護膜は金属膜が劣化する温度よりも低い温度の熱によつ て硬化する材料から構成されているので、 保護膜形成の際に電極に実質的なダメ ージを与えることがなくなる。 このため、 電極が形成された後に保護膜を形成す ることができ、 保護膜及び電極を形成するために複数回のェッチング工程を繰り 返す必要がなくなる。 従って、 半導体素子の製造工程を簡略化することができ、 半導体素子の生産性を向上させることができる。 前記メサ溝 (9) は、 前記第 1の電極 (4) を構成する金属膜 (1 1) をマス クとして用いて、 前記半導体基板 (2) の一方の主面をエッチングすることによ つて形成されたものであってもよい。 According to this configuration, since the protective film is made of a material that is cured by heat at a temperature lower than the temperature at which the metal film deteriorates, substantial damage to the electrodes is caused when the protective film is formed. Will not give. For this reason, the protective film can be formed after the electrode is formed, and it is not necessary to repeat a plurality of etching steps to form the protective film and the electrode. Therefore, the manufacturing process of the semiconductor device can be simplified, and the productivity of the semiconductor device can be improved. The mesa groove (9) is formed by etching one main surface of the semiconductor substrate (2) using the metal film (11) constituting the first electrode (4) as a mask. It may be formed.
前記半導体基板 (2) は、 第 1導電型の第 1半導体領域 (6) と、 前記第 1の 5半導体領域 (6) との界面が p n接合を形成する第 2導電型の第 2半導体領域 ( 7) と、 該第 2の半導体領域 (7) に接するとともに該第 2半導体領域 (7) よ りも高濃度の第 2導電型の第 3半導体領域 (8) とを備えるものであってもよい 前記保護膜 (3) は、 前記第 1の電極 (4) を構成する金属膜の融点よりも 1 10 00°C〜400°C低い温度の熱によって硬化する材料から構成されていてもよい 前記第 1の電極 (4) は、 アルミニウムから構成され、 前記保護膜 (3) は、 200°C〜500°Cの熱によって硬化する材料から構成されているものであって あよい。  The semiconductor substrate (2) has a second conductivity type second semiconductor region in which an interface between a first conductivity type first semiconductor region (6) and the first five semiconductor region (6) forms a pn junction. (7) and a third conductive type third semiconductor region (8) in contact with the second semiconductor region (7) and having a higher concentration than the second semiconductor region (7). The protective film (3) may be made of a material which is cured by heat at a temperature lower by 1100 ° C. to 400 ° C. than a melting point of the metal film constituting the first electrode (4). The first electrode (4) may be made of aluminum, and the protective film (3) may be made of a material which is cured by heat at 200 to 500 ° C.
15 前記保護膜 (3) は、 ポリイミ ド系樹脂から構成されているものであってもよ い。 図面の簡単な説明  15 The protective film (3) may be made of polyimide resin. BRIEF DESCRIPTION OF THE FIGURES
図 1は、 本発明の実施の形態に係るメサ型ダイォードの構成を示す断面図であ 20 る。  FIG. 1 is a cross-sectional view showing a configuration of a mesa-type diode according to an embodiment of the present invention.
図 2 (a) 〜 (g) は、 本発明の実施の形態に係るメサ型ダイオードの製造ェ 程を説明するための断面図である。  2 (a) to 2 (g) are cross-sectional views for explaining a manufacturing process of the mesa diode according to the embodiment of the present invention.
図 3は、 本発明の実施の形態の半導体素子の変形例を示す断面図である。  FIG. 3 is a cross-sectional view showing a modification of the semiconductor device according to the embodiment of the present invention.
図 4は、 従来のメサ型ダイオードの構成を示す断面図である。  FIG. 4 is a cross-sectional view showing a configuration of a conventional mesa diode.
25  twenty five
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
以下、 本発明の実施の形態に係る半導体素子及びその製造方法について、 メサ 型ダイォードを例とし、 図面を参照して詳細に説明する。  Hereinafter, a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the drawings using a mesa-type diode as an example.
図 1に断面で示すように、 メサ型ダイオード 1は、 半導体基板 2と、 保護膜 3 'と、 力ソード電極 4と、 アノード電極 5とを備える。 As shown in cross section in FIG. 1, the mesa diode 1 has a semiconductor substrate 2 and a protective film 3 , A power source electrode 4 and an anode electrode 5.
半導体基板 2は、 第 1半導体領域 6と、 第 2半導体領域 7と、 第 3半導体領域 8とを備える。 半導体基板 2のうち、 第 2半導体領域 7と、 第 3半導体領域 8と を除いた部分が、 第 1半導体領域 6を構成している。  The semiconductor substrate 2 includes a first semiconductor region 6, a second semiconductor region 7, and a third semiconductor region 8. A portion of the semiconductor substrate 2 excluding the second semiconductor region 7 and the third semiconductor region 8 constitutes a first semiconductor region 6.
第 1半導体領域 6は、 第 1導電型、 例えば、 p+型の半導体領域から構成され、 カソード領域として機能する。 第 1半導体領域 6は、 30 μη!〜 300 μ m程度 の厚さに形成されている。 また、 第 1半導体領域 6は、 1 X 1 016 cm一3〜 1 X 1 021 cm— 3程度の不純物濃度に形成されている。 The first semiconductor region 6 is formed of a semiconductor region of a first conductivity type, for example, ap + type, and functions as a cathode region. The first semiconductor region 6 has 30 μη! The thickness is about 300 μm. The first semiconductor region 6 is formed on the impurity concentration of about 1 X 1 0 16 cm one 3 ~ 1 X 1 0 21 cm- 3.
第 2半導体領域 7は、 第 1半導体領.域 6の一方の主面に形成されている。 第 2 半導体領域 7は、 第 2導電型、 例えば、 n一型の半導体領域から構成される。 第 2 半導体領域 7は、 1 0 /X m〜200 m程度の厚さに形成されている。 また、 第 2半導体領域 7は、 1 X 1 012cm— 3〜1 X 1 018 c m— 3程度の不純物濃度に形 成されている。 従って、 半導体基板 2は、 第 2半導体領域 7と第 1半導体領域 6 との界面が形成する p n接合を備える。 The second semiconductor region 7 is formed on one main surface of the first semiconductor region 6. The second semiconductor region 7 is composed of a semiconductor region of the second conductivity type, for example, n-type. The second semiconductor region 7 is formed with a thickness of about 10 / Xm to 200 m. The second semiconductor region 7 is formed with an impurity concentration of about 1 × 10 12 cm— 3 to 1 × 10 18 cm— 3 . Therefore, the semiconductor substrate 2 has a pn junction formed at the interface between the second semiconductor region 7 and the first semiconductor region 6.
第 3半導体領域 8は、 第 2半導体領域 7の上面に形成されている。 第 3半導体 領域 8は、 第 2半導体領域 7よりも n型不純物濃度の高い n +型の半導体領域から 構成され、 アノード領域として機能する。 第 3半導体領域 8は、 50 μηι〜3 0 0 / m程度の厚さに形成されている。 また、 第 3半導体領域 8は、 l X 1 017 c m一3〜 1 X 1 022 c m— 3程度の不純物濃度に形成されている。 ' The third semiconductor region 8 is formed on the upper surface of the second semiconductor region 7. The third semiconductor region 8 is formed of an n + -type semiconductor region having an n-type impurity concentration higher than that of the second semiconductor region 7, and functions as an anode region. The third semiconductor region 8 is formed to a thickness of about 50 μηι to 300 / m. The third semiconductor region 8 is formed on the impurity concentration of about l X 1 0 17 cm one 3 ~ 1 X 1 0 22 cm- 3. '
半導体基板 2の上面には、 傾斜溝 (メサ溝) 9が形成されている。 メサ溝 9は 、 半導体基板 2の外周縁に沿った環状に形成されている。 メサ溝 9は、 その底面 で第 1半導体領域 6が露出するよ'うな深さを備える。 このため、 メサ溝 9の側面 及び底面で、 第 3半導体領域 8、 第 2半導体領域 7及び第 1半導体領域 6が露出 し、 さらに第 1半導体領域 6と第 2半導体領域 7との p n接合の端が露出してい る。 このメサ溝 9は、 例えば、 半導体基板 2の上面側が縮径となる (末広がり状 となる) ように、 半導体基板 2の上面から下面 (他面) に向かって傾斜した形状 に形成されている。 従って、 メサ型ダイオード 1は、 図 1に示すような略台形の 形状を有する。  On the upper surface of the semiconductor substrate 2, an inclined groove (mesa groove) 9 is formed. The mesa groove 9 is formed in an annular shape along the outer peripheral edge of the semiconductor substrate 2. The mesa groove 9 has a depth such that the first semiconductor region 6 is exposed at the bottom surface. Therefore, the third semiconductor region 8, the second semiconductor region 7, and the first semiconductor region 6 are exposed from the side and bottom surfaces of the mesa groove 9, and the pn junction between the first semiconductor region 6 and the second semiconductor region 7 is further increased. The edge is exposed. The mesa groove 9 is formed in a shape inclined from the upper surface of the semiconductor substrate 2 toward the lower surface (other surface), for example, so that the upper surface side of the semiconductor substrate 2 has a reduced diameter (a divergent shape). Therefore, the mesa diode 1 has a substantially trapezoidal shape as shown in FIG.
保護膜 3は、 メサ溝 9により露出した第 1半導体領域 6、 第 2半導体領域 7及 ぴ第 3半導体領域 8を被覆するように、 メサ溝 9の側面および底面に形成されて いる。 The protective film 3 includes the first semiconductor region 6, the second semiconductor region 7, ぴ Formed on the side and bottom surfaces of the mesa groove 9 so as to cover the third semiconductor region 8.
保護膜 3は、 カソード電極 4を構成する材料が熱によって劣化するよりも低い 温度で硬化する材料から構成される。 カソード電極 4の材料が劣化する温度とし ては、 例えば材料の融点が挙げられる。 そこで、 保護膜 3は、 力ソード電極 4を 構成する材料の融点よりも、 1 0 0 °C〜4 0 0 °C低い温度の熱によって硬化する 材料から構成されると好ましい。 例えば、 力ソード電極 4がアルミニウムから構 成されるとする。 この場合、 保護膜 3は、 ポリイミ ド系樹脂から構成されるとよ い。 ポリイミ ド系樹脂は、 アルミニウムの融点 (6 0 0 °C程度) よりも低い温度 ( 2 0 0 °C〜5 0 0 °C程度) の熱処理によって樹脂中に含まれる溶剤が揮発し、 収縮して熱硬化することができる。 さらに、 ポリイミ ド系樹脂は、 2 0 0 °C〜5 0 o °cの温度での熱硬化により、 比較的硬質、 かつ緻密な樹脂膜を形成すること ができる。 このため、 ポリイミ ド系樹脂を保護膜 3の材料として用いれば、 カソ 一ド電極 4を構成するアルミニウム膜に、 熱による実質的なダメージ等を与えな い。 このようなことから、 本実施の形態では、 保護膜 3の材料に、 ポリイミ ド系 樹脂を用いるものとする。  The protective film 3 is made of a material that cures at a lower temperature than the material constituting the cathode electrode 4 is deteriorated by heat. The temperature at which the material of the cathode electrode 4 deteriorates is, for example, the melting point of the material. Therefore, it is preferable that the protective film 3 be made of a material that is cured by heat at a temperature lower by 100 ° C. to 400 ° C. than the melting point of the material forming the force source electrode 4. For example, suppose that force source electrode 4 is made of aluminum. In this case, the protective film 3 may be made of a polyimide resin. The polyimide resin undergoes heat treatment at a temperature lower than the melting point of aluminum (about 600 ° C) (about 200 ° C to 500 ° C), and the solvent contained in the resin volatilizes and shrinks. Can be heat cured. Further, the polyimide resin can form a relatively hard and dense resin film by thermosetting at a temperature of 200 ° C. to 50 ° C. Therefore, when the polyimide resin is used as the material of the protective film 3, the aluminum film forming the cathode electrode 4 is not substantially damaged by heat. For this reason, in the present embodiment, a polyimide resin is used as the material of the protective film 3.
力ソード電極 4は、 アルミニウム膜等の金属膜から構成される。 力ソード電極 4は、 半導体基板 2の一方の主面に形成されている。  Force sword electrode 4 is made of a metal film such as an aluminum film. Force sword electrode 4 is formed on one main surface of semiconductor substrate 2.
アノード電極 5は、 例えば、 チタン、 ニッケル、 パラジウム及び銀が順次蒸着 された金属膜から構成される。 アノード電極 5は、 半導体基板 2の他方の主面に 形成されている。  The anode electrode 5 is composed of, for example, a metal film on which titanium, nickel, palladium and silver are sequentially deposited. The anode electrode 5 is formed on the other main surface of the semiconductor substrate 2.
次に、 以上のような構成を有するメサ型ダイォード 1を製造する手順について 、 図 2 ( a ) 〜 (g ) を参照して詳細に説明する。 なお、 以下に示す手順は一例 であり、 同様の結果が得られるのであれば、 いかなる手順であっても差し支えな い。  Next, a procedure for manufacturing the mesa type diode 1 having the above-described configuration will be described in detail with reference to FIGS. 2 (a) to 2 (g). The following procedure is an example, and any procedure may be used as long as a similar result is obtained.
まず、 p +型の半導体基板 2に、 ェピタキシャル成長方法、 熱拡散方法等によつ て、 図 2 ( a ) に示すように、 n _型の半導体領域 (第 2半導体領域 7 ) 及ぴ n + 型の半導体領域 (第 3半導体領域 8 ) を形成する。 半導体基板 2のうち、 第 2半 導体領域 7と第 3半導体領域 8とを除いた部分が、 第 1半導体領域 6を構成して いる。 本実施の形態では、 第 1半導体領域 6、 第 2半導体領域 7、 第 3半導体領 域 8の厚さを、 それぞれ、 1 00 //πι、 40 m, Ι Ο Ο μπιとし、 半導体基板 2全体の厚さを 240 μπιとした。 First, as shown in FIG. 2 (a), an n_ type semiconductor region (second semiconductor region 7) and a p + type semiconductor substrate 2 are formed by an epitaxial growth method, a thermal diffusion method, or the like. An n + type semiconductor region (third semiconductor region 8) is formed. The portion of the semiconductor substrate 2 excluding the second semiconductor region 7 and the third semiconductor region 8 constitutes the first semiconductor region 6. I have. In the present embodiment, the thicknesses of the first semiconductor region 6, the second semiconductor region 7, and the third semiconductor region 8 are 100 // πι, 40 m, and Ι Ι μπι, respectively. Was 240 μπι.
' 次に、 真空蒸着等によって、 図 2 (b) に示すように、 半導体基板 2の一方の 主面にアルミニウム膜' 1 1を形成する。 このアルミニウム膜 1 1は、 後に形成す る力ソード電極 4を構成する。 本実施の形態では、 アルミニウム膜 1 1の厚さを 8 μ mとした。  Next, as shown in FIG. 2B, an aluminum film '11 is formed on one main surface of the semiconductor substrate 2 by vacuum evaporation or the like. This aluminum film 11 constitutes a force source electrode 4 to be formed later. In the present embodiment, the thickness of aluminum film 11 is set to 8 μm.
続いて、 半導体基板 2の他方の主面に例えばアルミニウムを真空蒸着する.こと により、 図 2 (b) に示すように、 アルミニウム膜 1 2を形成する。 このアルミ ユウム膜 1 2は、 後述するテープ部材を第 1半導体領域 6の他方の主面に貼着し たときに、 第 1半導体領域 6の他方の主面の汚染を防止するためのものである。 アルミニウム膜 1 2の厚さは、 1 //m〜l 0 程度が好ましく、 本実施の形態 では、 例えば、 2 μ mとした。  Subsequently, for example, aluminum is vacuum-deposited on the other main surface of the semiconductor substrate 2 to form an aluminum film 12 as shown in FIG. 2 (b). The aluminum film 12 is for preventing the other main surface of the first semiconductor region 6 from being contaminated when a tape member described later is attached to the other main surface of the first semiconductor region 6. is there. The thickness of the aluminum film 12 is preferably about 1 // m to l0. In the present embodiment, the thickness is, for example, 2 μm.
続いて、 ナイロンメッシュマスク等を使用するスクリーン技術等を用いて耐酸 性インクをアルミニウム膜 1 1上に印刷することにより、 図 2 (c) に示すよう に、 アルミニウム膜 1 1上にエッチング用マスク 1 3を形成する。 エッチング用 マスク 1 3は、 メサ溝 9を形成する領域 (メサ溝形成予定領域) に対応する部分 に開口 1 3 aを有しており、 アルミニウム膜 1 1のメサ溝形成予定領域は、 開口 1 3 aを通じて露出している。 開口 1 3. aは、 平面的に見ると、 半導体基板 2の —方の主面に罔目状に形成されている。 このため、 エッチング用マスク 1 3は、 半導体基板 2の一方の主面に島状に形成されている。  Subsequently, an acid-resistant ink is printed on the aluminum film 11 using a screen technique using a nylon mesh mask or the like, thereby forming an etching mask on the aluminum film 11 as shown in FIG. 2 (c). Form 1 3 The etching mask 13 has an opening 13 a at a portion corresponding to a region where a mesa groove 9 is to be formed (a region where a mesa groove is to be formed). 3A is exposed through. The opening 13. A is formed in the form of a stitch on the main surface of the semiconductor substrate 2 when viewed two-dimensionally. For this reason, the etching mask 13 is formed in an island shape on one main surface of the semiconductor substrate 2.
次に、 エッチング用マスク 1 3をマスクとして用いて、 図 2 (d) に示すよう に、 アルミニウム膜 1 1のうち、 エッチング用マスク 1 3に被覆されていない開 口 1 3 aに対応する部分をエッチングする。 すなわちアルミニウム膜 1 1のうち 、 メサ溝形成予定領域に対応する部分を除去する。 アルミニウム用エッチング液 には、 王水 (Aqua Regie) 等を用いた。  Next, using the etching mask 13 as a mask, as shown in FIG. 2D, a portion of the aluminum film 11 corresponding to the opening 13a not covered with the etching mask 13 Is etched. That is, a portion of the aluminum film 11 corresponding to the region where the mesa groove is to be formed is removed. Aqua Regie was used as the etching solution for aluminum.
また、 アルミニウム膜 1 2の下面 (半導体基板 2の他方の主面に接していない 面) に、 テープ部材 14を貼着する。  Further, a tape member 14 is attached to the lower surface of the aluminum film 12 (the surface not in contact with the other main surface of the semiconductor substrate 2).
続いて、 エッチング用マスク 1 3及ぴアルミニウム膜 1 1をマスクとして用い て、 開口 1 3 aを介してメサ溝形成予定領域をエッチングし、 図 2 ( e ) に示す ように、 断面が U字状のメサ溝 9を形成する。 かつ、 メサ溝 9を、 平面的に見て .半導体基板 2の外周縁に沿った環状に形成する。 エッチング液には、 硝酸、 弗酸 、 酢酸及び硫酸の混合液を用いた。 本実施の形態では、 メサ溝 9の深さを 1 6 0 5 /z mとした。 この結果、 メサ溝 9の側面で第 3半導体領域 8、 第 2半導体領域 7 、 第 1半導体領域 6及び第 2半導体領域 7と第 1半導体領域 6との p n接合が露 出する。 また、 メサ溝 9の底面で 8 0 mの厚さの第 1半導体領域 6が残存する 次に、 図 2 ( e ) に示すアルミニウム膜 1 1の、 メサ溝 9の縁から突出する部 10分を、 エッチングによって、 図 2 ( f ) に示すように、 断面で見て、 アルミ-ゥ ム膜 1 1の縁とメサ溝 9の縁とが揃うように除去する。 また、 力ソード電極 4上 に形成されたエッチング用マスク 1 3を除去する。 さらに、 アルミニウム膜 1 2 の下面に貼着されたテープ部材 1 4を除去する。 Subsequently, the etching mask 13 and the aluminum film 11 are used as masks. Then, the region where the mesa groove is to be formed is etched through the opening 13a to form a mesa groove 9 having a U-shaped cross section as shown in FIG. 2 (e). In addition, the mesa groove 9 is formed in an annular shape along the outer peripheral edge of the semiconductor substrate 2 when viewed in plan. A mixed solution of nitric acid, hydrofluoric acid, acetic acid and sulfuric acid was used as an etching solution. In the present embodiment, the depth of the mesa groove 9 is set to 1605 / zm. As a result, the third semiconductor region 8, the second semiconductor region 7, the first semiconductor region 6, and the pn junction between the second semiconductor region 7 and the first semiconductor region 6 are exposed on the side surfaces of the mesa groove 9. In addition, the first semiconductor region 6 having a thickness of 80 m remains on the bottom surface of the mesa groove 9. Next, the portion of the aluminum film 11 shown in FIG. Is removed by etching so that the edge of the aluminum film 11 and the edge of the mesa groove 9 are aligned in a cross section as shown in FIG. 2 (f). Further, the etching mask 13 formed on the force source electrode 4 is removed. Further, the tape member 14 attached to the lower surface of the aluminum film 12 is removed.
続いて、 図 2 ( g ) に示すように、 保護膜 3を、 メサ溝 9の内面を被覆するよ 15 うに形成する。 保護膜 3の材料として、 例えばポリイミ ド系樹脂を用いると、 2 0 0 °C〜5 0 0 °C程度の温度で保護膜 3を形成することができる。  Subsequently, as shown in FIG. 2G, the protective film 3 is formed so as to cover the inner surface of the mesa groove 9. If, for example, a polyimide resin is used as the material of the protective film 3, the protective film 3 can be formed at a temperature of about 200 ° C. to 500 ° C.
より詳細に説明すると、 まず、 デイスペンサ型の塗布器等を用いて、 メサ溝 9 の内面に流動性を有するポリイミ ド系榭脂を塗布する。 塗布したポリイミ ド系樹 脂を硬化させて保護膜 3を形成するため、 この樹脂に 3 5 0 °Cの温度で 6 0分間 20 の熱処理を施す。 ポリイミ ド系樹脂は、 2 0 0 °C〜5 0 0 °C程度の温度の熱処理 によって、 樹脂中に含まれる溶剤が揮発するとともに樹脂のイミド結合が促進し 、 比較的硬質でかつ緻密な樹脂膜 (保護膜 3 ) を形成する。  More specifically, first, a fluid polyimide resin is applied to the inner surface of the mesa groove 9 using a dispenser type applicator or the like. In order to form the protective film 3 by curing the applied polyimide resin, the resin is subjected to a heat treatment at 350 ° C. for 60 minutes for 20 minutes. The polyimide-based resin is heat-treated at a temperature of about 200 ° C. to 500 ° C. to evaporate a solvent contained in the resin and promote imide bond of the resin, thereby obtaining a relatively hard and dense resin. A film (protective film 3) is formed.
なお、 この工程において、 熱処理によってポリイミ ド系榭脂だけでなく、 アル ミニゥム膜 1 1等も加熱されるが、 このような範囲の温度では、 アルミニウム膜 In this step, not only the polyimide resin but also the aluminum film 11 and the like are heated by the heat treatment.
25 1 1に実質的なダメージが生じることはない。 There is no substantial damage to 25 1 1.
次に、 アルミニウム膜 1 1の表面をライトエッチングし、 アルミニウム膜 1 1 から構成される力ソード電極 4を形成する。 また、 アルミニウム膜 1 2を除去し 、 半導体基板' 2の他方の主面にチタン、 ニッケル、 パラジウム及ぴ銀を順次真空 蒸着し、 アノード電極 5を形成する。 最後に、 メサ溝 9に沿って半導体基板 2を ダイシングする。 Next, the surface of the aluminum film 11 is lightly etched to form a force source electrode 4 composed of the aluminum film 11. Also, the aluminum film 12 is removed, and titanium, nickel, palladium and silver are sequentially vacuum-deposited on the other main surface of the semiconductor substrate 2 to form the anode electrode 5. Finally, the semiconductor substrate 2 is formed along the mesa groove 9. Dicing.
以上の工程を経て、 本実施の形態のメサ型ダイォード 1が形成される。  Through the above steps, the mesa diode 1 of the present embodiment is formed.
以上説明したように、 本実施の形態によれば、 力ソード電極 4を構成するアル ミニゥム膜 1 1を形成したうえで、 アルミニウム膜 1 1をマスクとして用いて半 導体基板 2をエッチングし、 メサ溝 9を形成する。 これにより、 保護膜 3及ぴカ ソード電極 4を形成するために従来技術のように複数回のエッチング工程を繰り 返す必要がなくなる。  As described above, according to the present embodiment, after forming aluminum film 11 constituting force source electrode 4, semiconductor substrate 2 is etched using aluminum film 11 as a mask, and A groove 9 is formed. This eliminates the need to repeat a plurality of etching steps as in the prior art, in order to form the protective film 3 and the cathode electrode 4.
また、 本実施の形態では、 アルミニウム膜 1 1を形成した後、 保護膜 3を形成 しているので、 従来技術のように保護膜 3が力ソード電極形成予定領域の縁に残 存する、 といった問題が生じなくなる。 アルミニウム膜 1 1を先に形成できるの で、 上述したように、 アルミニウム膜 1 1の縁とメサ溝 9の縁とをエッチングに よって揃えやすい。 このため、 本実施の形態では、 従来技術と比べて力ソード電 極 4を形成するためのエッチングを精度良く行える。  Further, in the present embodiment, since the protective film 3 is formed after the aluminum film 11 is formed, there is a problem that the protective film 3 remains on the edge of the region where the force source electrode is to be formed as in the related art. Will not occur. Since the aluminum film 11 can be formed first, the edge of the aluminum film 11 and the edge of the mesa groove 9 are easily aligned by etching as described above. For this reason, in the present embodiment, etching for forming the force sword electrode 4 can be performed more accurately than in the conventional technique.
従って、 本実施の形態では、 従来より生産性が向上したメサ型ダイオードを形 成できる。  Therefore, in the present embodiment, it is possible to form a mesa diode having improved productivity as compared with the related art.
さらに、 本実施の形態では、 力ソード電極 4を構成するアルミニウム膜 1 1が 劣化する温度よりも低い温度の熱によってメサ溝 9を被覆する保護膜 3を形成し ている。 このため、 本実施の形態では、 熱によってアルミニウム膜 1 1に実質的 なダメージが生じにくい。  Further, in the present embodiment, protective film 3 covering mesa groove 9 is formed by heat at a temperature lower than the temperature at which aluminum film 11 constituting force source electrode 4 deteriorates. For this reason, in the present embodiment, the heat hardly causes substantial damage to the aluminum film 11.
なお、 本発明は、 上記の実施の形態に限られず、 種々の変形、 応用が可能であ る。 例えば、 上記実施の形態では、 力ソード電極 4を構成する金属膜が熱によつ て劣化する温度を、 融点を例にして説明した。 し力 し、 金属膜が熱によって劣化 する温度は、 融点に限定されず、 金属膜の性質 (例えば抵抗率) を実質的に変化 させる温度であれば何でもよい。  Note that the present invention is not limited to the above-described embodiment, and various modifications and applications are possible. For example, in the above embodiment, the temperature at which the metal film forming the force source electrode 4 is degraded by heat has been described by taking the melting point as an example. However, the temperature at which the metal film is degraded by heat is not limited to the melting point, but may be any temperature that substantially changes the properties (eg, resistivity) of the metal film.
上記実施の形態では、 保護膜 3にポリイミ ド系樹脂を用いた場合を例として説 明した。 しかし、 これに限定されず、 保護膜 3を構成する材料は、 力ソード電極 4を構成する材料の膜質が変化する温度より低い温度で保護膜 3を形成可能なも のであれば何でもよい。 すなわち、 保護膜 3の材料は、 力ソード電極 4を構成す る材料に実質的なダメージを生じることがない温度で熱処理可能なものであれば 何でもよい。 この場合、 力ソード電極 4を構成する材料によって、 保護膜 3を構 成する材料を適宜変更するとよい。 In the above-described embodiment, the case where the polyimide resin is used for the protective film 3 has been described as an example. However, the material is not limited to this, and any material may be used as the material of the protective film 3 as long as the material of the force source electrode 4 can be formed at a temperature lower than the temperature at which the film quality of the material changes. That is, if the material of the protective film 3 can be heat-treated at a temperature that does not cause substantial damage to the material constituting the force source electrode 4, Anything is fine. In this case, the material forming the protective film 3 may be appropriately changed depending on the material forming the force source electrode 4.
また、 上記実施の形態では、 第 1半導体領域 6の他方の主面にテープ部材 1 4 (及びアルミニウム膜 1 2 ) を形成した場合を例として説明したが、 テープ部材 1 4 (及ぴアルミニウム膜 1 2 ) を形成しなくてもよい。 この場合には、 メサ型 ダイォード 1の製造工程を上記実施の形態のものと比較して簡単にすることがで き、 さらに生産性が向上したメサ型ダイォードを提供することが可能となる。 さらには、 上記実施の形態では、 デイスペンサ型の塗布器を用いて、 ポリイミ ド系樹脂をメサ溝 9に塗布した場合を例にして説明したが、 これに限定されず、 各種の手法を用いてポリイミ ド系樹脂をメサ溝 9に塗布しても差し支えない。 上記実施の形態の半導体素子は、 メサ型ダイオードに限定されず、 メサ型トラ ンジスタ等の他の任意のメサ型半導体素子であってもよい。 この場合、 メサ型ト ランジスタは、 例えば図 3に示す構成を有するとよい。 図示するメサ型トランジ スタ l aは、 p型半導体領域 2 1と n型半導体領域 2 2とを除いて、 図 1に示す 構成と同一の構成を有する。  In the above embodiment, the case where the tape member 14 (and the aluminum film 12) is formed on the other main surface of the first semiconductor region 6 has been described as an example, but the tape member 14 (and the aluminum film 1 2) need not be formed. In this case, the manufacturing process of the mesa-type diode 1 can be simplified as compared with the above-described embodiment, and a mesa-type diode with further improved productivity can be provided. Further, in the above-described embodiment, the case where the polyimide resin is applied to the mesa groove 9 using the dispenser type applicator has been described as an example, but the present invention is not limited to this, and various methods may be used. A polyimide resin may be applied to the mesa groove 9 without any problem. The semiconductor element of the above embodiment is not limited to the mesa diode, but may be any other mesa semiconductor element such as a mesa transistor. In this case, the mesa transistor may have the configuration shown in FIG. 3, for example. The illustrated mesa transistor la has the same configuration as that shown in FIG. 1 except for the p-type semiconductor region 21 and the n-type semiconductor region 22.
上記実施の形態では、 寘空蒸着によってカソード電極 4を構成するアルミエゥ ム膜 1 1を半導体基板 2の一方の主面に形成した。 しかし、 これに限定されず、 例えばスパッタリングによってアルミニウム膜 1 1を半導体基板 2の一方の主面 に形成してもよい。  In the above embodiment, the aluminum film 11 constituting the cathode electrode 4 is formed on one main surface of the semiconductor substrate 2 by vacuum evaporation. However, the present invention is not limited to this. For example, the aluminum film 11 may be formed on one main surface of the semiconductor substrate 2 by sputtering.
以上説明したように、 本発明によれば、 半導体素子の生産性を向上させること ができる半導体素子及びその製造方法を提供することが可能となる。  As described above, according to the present invention, it is possible to provide a semiconductor device capable of improving the productivity of a semiconductor device and a method for manufacturing the same.
• なお、 本発明は、 2 0 0 2年 3月 8日に出願された日本国特許出願 2 0 0 2 - 6 3 1 7 3号に基づき、 本明細書中にその明細書、 特許請求の範囲、 図面全体を 取り込むものとする。 産業上の利用の可能性  • The present invention is based on Japanese Patent Application No. 2002-6311 173 filed on March 8, 2002, and its description and claims The range and the whole drawing shall be taken. Industrial applicability
本発明は、 メサ型の半導体素子に利用可能である。  INDUSTRIAL APPLICABILITY The present invention can be used for a mesa type semiconductor device.

Claims

請求の範囲 The scope of the claims
1. 半導体基板'(2) と、 前記半導体基板 (2) の一方の主面の所定の領域に 形成された電極 (4) と、 前記半導体基板 (2) の一方の主面の外周に沿って該1. A semiconductor substrate (2), an electrode (4) formed in a predetermined region on one main surface of the semiconductor substrate (2), and an outer periphery of the one main surface of the semiconductor substrate (2). The
5半導体基板 (2) に形成されたメサ溝 (9) と、 前記メサ溝 (9) の内面を被覆 する保護膜 (3) とを備えるメサ形状の半導体素子 (1) の製造方法において、 前記半導体基板 (2) の一方の主面の所定の領域に、 前記電極を構成する金属 膜 (1 1) を形成し、 (5) A method for manufacturing a mesa-shaped semiconductor element (1) comprising: a mesa groove (9) formed in a semiconductor substrate (2); and a protective film (3) covering an inner surface of the mesa groove (9). Forming a metal film (11) constituting the electrode in a predetermined region on one main surface of the semiconductor substrate (2);
前記金属膜 (11) をマスクとして、 前記半導体基板 (2) の一方の主面の外 10周に沿って前記メサ溝 (9) を形成し、  Using the metal film (11) as a mask, forming the mesa groove (9) along the outer periphery of one main surface of the semiconductor substrate (2),
前記金属膜 (1 1) が劣化する温度よりも低い温度の熱によって硬化する材料 を用いて、 前記メサ溝 (9) の内面を被覆するように前記保護膜 (3) を形成し 前記保護膜 (3) によって被覆された前記メサ溝 (9) に沿って前記半導体基 I5板 (2) をダイシングする、 The protective film (3) is formed so as to cover the inner surface of the mesa groove (9) by using a material that is cured by heat at a temperature lower than the temperature at which the metal film (11) deteriorates. Dicing the semiconductor substrate I 5 plate (2) along the mesa groove (9) covered by (3);
. ことを含んでいることを特徴とするメサ形状の半導体素子の製造方法。  A method for manufacturing a mesa-shaped semiconductor device, comprising:
2. アルミユウムを用いて前記電極 (4) を形成し、 アルミニウムの融点より も 100°C〜400°C低い温度の熱によって硬化する材料を用いて前記保護膜 ( 3) を形成する、 ことを特徴とする請求項 1に記載の半導体素子の製造方法。 2. forming the electrode (4) using aluminum, and forming the protective film (3) using a material that is cured by heat at a temperature of 100 ° C. to 400 ° C. lower than the melting point of aluminum; 2. The method for manufacturing a semiconductor device according to claim 1, wherein:
20 3. ポリイミ ド系樹脂から前記保護膜 (3) を形成する、 ことを特徴とする請 求項 2に記載の半導体素子の製造方法。 20 3. The method for manufacturing a semiconductor device according to claim 2, wherein the protective film (3) is formed from a polyimide resin.
4. 半導体基板 (2) と、 前記半導体基板 (2) の一方の主面の所定の領域に 形成された第 1の電極 (4) と、 前記半導体基板 (2) の他方の主面に形成され た第 2の電極 (5) と、 前記半導体基板 (2) の一方の主面の外周に沿って該半 5導体基板 (2) に形成されたメサ溝 (9) と、 前記メサ溝 (9) の内面を被覆す る保護膜 (3) と、 を備えるメサ型の半導体素子 (1) において、  4. A semiconductor substrate (2), a first electrode (4) formed in a predetermined region on one main surface of the semiconductor substrate (2), and a first electrode (4) formed on the other main surface of the semiconductor substrate (2) The second electrode (5), a mesa groove (9) formed in the semi-five conductor substrate (2) along the outer periphery of one main surface of the semiconductor substrate (2), and the mesa groove ( 9) In a mesa-type semiconductor device (1) comprising a protective film (3) covering the inner surface of
前記第 1の電極 (4) は、 金属膜 (1 1) から構成され、  The first electrode (4) is composed of a metal film (1 1),
前記保護膜 (3) は、 前記金属膜 (1 1) が劣化する温度よりも低い温度の熱 によつて硬化する材料から構成される、 ことを特徴とする半導体素子。 The protective film (3) is made of a material that is cured by heat at a temperature lower than the temperature at which the metal film (11) deteriorates. A semiconductor element characterized by the above-mentioned.
5. 前記メ.サ溝 (9) は、 前記第 1の電極 (4) を構成する金属膜 (1 1) を マスクとして用いて、 前記半導体基板 (2) の一方の主面をエッチングすること によって形成されたものである、 ことを特徴とする請求項 4に記載の半導体素子 o  5. The mesa groove (9) is formed by etching one main surface of the semiconductor substrate (2) using the metal film (1 1) constituting the first electrode (4) as a mask. The semiconductor device according to claim 4, wherein the semiconductor device is formed by:
6. 前記半導体基板 (2) は、 第 1導電型の第 1半導体領域 (6) と、 前記第 1の半導体領域 (6) との界面が p n接合を形成する第 2導電型の第 2半導体領 域 (7) と、 該第 2の半導体領域 (7) に接するとともに該第 2半導体領域 (7 ) よりも高濃度の第 2導電型の第 3半導体領域 (8) とを備える、 ことを特徴と する請求項 4に記載の半導体素子。  6. The semiconductor substrate (2) includes a second semiconductor of a second conductivity type in which an interface between the first semiconductor region (6) of the first conductivity type and the first semiconductor region (6) forms a pn junction. A third semiconductor region (8) in contact with the second semiconductor region (7) and having a higher concentration than the second semiconductor region (7). 5. The semiconductor device according to claim 4, wherein the semiconductor device is characterized in that:
7. 前記保護膜 (3) は、 前記第 1の電極 (4) を構成する金属膜の融点より も 100°C〜400°C低い温度の熱によって硬化する材料から構成されている、 ことを特徴とする請求項 4に記載の半導体素子。  7. The protective film (3) is made of a material that is cured by heat at a temperature 100 ° C to 400 ° C lower than the melting point of the metal film forming the first electrode (4). 5. The semiconductor device according to claim 4, wherein:
8. 前記第 1の電極 (4) は、 アルミニウムから構成され、  8. The first electrode (4) is made of aluminum,
前記保護膜 (3) は、 200° (〜 500°Cの熱によって硬化する材料から構成 されている、 ことを特徴とする請求項 7に記載の半導体素子。  The semiconductor device according to claim 7, wherein the protective film (3) is made of a material that is cured by heat at 200 ° (up to 500 ° C).
9. 前記保護膜 (3) は、 ポリイミ ド系樹脂から構成されている、 ことを特徴 とする請求項 8に記載の半導体素子。  9. The semiconductor device according to claim 8, wherein the protective film (3) is made of a polyimide resin.
PCT/JP2003/002787 2002-03-08 2003-03-10 Semiconductor device and its manufacturing method WO2003077306A1 (en)

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