WO2003073514A1 - Structure multicouche a semi-conducteur a base de nitrure d'elements du groupe iii-v et son procede de production - Google Patents

Structure multicouche a semi-conducteur a base de nitrure d'elements du groupe iii-v et son procede de production Download PDF

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Publication number
WO2003073514A1
WO2003073514A1 PCT/JP2003/001935 JP0301935W WO03073514A1 WO 2003073514 A1 WO2003073514 A1 WO 2003073514A1 JP 0301935 W JP0301935 W JP 0301935W WO 03073514 A1 WO03073514 A1 WO 03073514A1
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substrate
nitride semiconductor
buffer layer
layer
laminated structure
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PCT/JP2003/001935
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English (en)
Japanese (ja)
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Seikoh Yoshida
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The Furukawa Electric Co., Ltd.
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Priority claimed from JP2002317878A external-priority patent/JP4593067B2/ja
Priority claimed from JP2003029899A external-priority patent/JP4329984B2/ja
Application filed by The Furukawa Electric Co., Ltd. filed Critical The Furukawa Electric Co., Ltd.
Publication of WO2003073514A1 publication Critical patent/WO2003073514A1/fr

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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C30B29/406—Gallium nitride
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the present invention relates to a stacked structure composed of 111_V group nitride semiconductors such as GaN-based semiconductors and a method of manufacturing the same. More specifically, the quality of the crystal is good, and even if the grown film thickness of the nitride semiconductor is increased, cracks and the like do not occur there, and the surface is flat and mirror-like.
  • the present invention relates to a laminated structure that is less likely to leak to the substrate side during operation of a semiconductor device manufactured using this laminated structure, and is useful as a starting material when manufacturing various semiconductor devices, and a method of manufacturing the same. Background art
  • field-effect transistors using GaN-based semiconductors, which are a type of group IV nitride semiconductor, have attracted attention as FETs that have excellent heat resistance and operate at high breakdown voltages.
  • FETs field-effect transistors
  • a predetermined semiconductor material is sequentially laminated on a semiconductor single crystal substrate by an epitaxy crystal growth method prior to processing into a target device.
  • a starting material having a predetermined laminated structure is produced.
  • a single crystal of GaN has a melting point of more than 200 Ot: and a vapor pressure at that melting point of more than 10 OGPa, so, for example, by applying a zone melting method or the like as in the case of GaAs, It is extremely difficult to directly produce single crystals. Therefore, in order to obtain a single crystal of GaN, a different kind of substrate material from GaN must be used, and crystal growth must be performed thereon. However, there is no material whose lattice constant matches that of G a N. Therefore, in order to alleviate the lattice mismatch with the substrate material, a method of forming a buffer layer in advance on the surface of the substrate to be used and growing GaN crystal on the buffer layer is generally used. It is being done.
  • the substrate for example, sapphire (A 1 2 0 3) substrate, S i C substrate, S i substrate, GaAs substrate, although such G a P substrate is used, among these, the sapphire substrate Most commonly used.
  • the lattice mismatch between this sapphire substrate and GaN is as large as 20% or more.
  • the thickness of a layer of a semiconductor material grown on a substrate needs to be at least 10 Onm or more.
  • the difference between the lattice constant of the substrate material and the lattice constant of the semiconductor material grown on the substrate is larger than 0.5%, the thickness of the growing semiconductor material layer exceeds 100 thighs due to the critical thickness.
  • the problem is that the crystal has many defects.
  • the following two-step growth method is used to grow thick GaN crystals on a sapphire substrate.
  • MOCVD metal organic chemical vapor deposition
  • TMA trimethylaluminum
  • NH 3 ammonia
  • hydrogen is used as a carrier gas, and at a long temperature of 800 ° C.
  • an A1N layer having a thickness of about 50 nm is temporarily formed as a buffer layer.
  • the growth temperature is raised to 1100, and GaN is grown thickly on the above-mentioned buffer layer using trimethylgallium (TMG) and ammonia (NH 3 ).
  • TMG trimethylgallium
  • NH 3 ammonia
  • MOCVD is applied, TMG and NH 3 are used, and hydrogen is used as a carrier gas.
  • a film is formed as a buffer layer.
  • the growth temperature is raised to 1000, and a thick GaN crystal is grown.
  • GMBE method gas source molecular beam epitaxy method
  • a thin buffer layer made of GaN is formed on a sapphire substrate or a Si substrate at a growth temperature of 500 to 550 ° C by using metal Ga and nitrogen that has been turned into plasma.
  • a thick GaN crystal is grown on the buffer layer by increasing the temperature.
  • the buffer layer becomes uniform if the thickness of the buffer layer is about 10 to 20 nm.
  • the film is not formed in a film shape, but is formed in an island pattern.
  • the Si substrate is exposed between the island crystals. Therefore, it is virtually impossible to grow GaN with good crystallinity and high quality on such a substrate.
  • the island pattern disappears, and a film-like buffer layer is formed as a whole.
  • the surface of the buffer layer at that time is not flat, even if a thick GaN layer is formed thereon, the surface of the GaN layer is affected by the island-like pattern of the lower buffer layer and becomes fine. There are irregularities and they are not flat mirror surface.
  • the thickness of the GaN layer is set to 1 m or more, cracks may occur in the thick GaN layer.
  • the GaN crystal in the above-mentioned thick GaN layer cannot be said to be of high quality.
  • threading dislocations defects that extend substantially perpendicular to the film thickness direction are generated in the buffer layer due to lattice mismatch with the substrate, and these threading dislocations remain as they are. This is because it propagates to the GaN crystal formed thereon.
  • this method requires a lithographic operation to form an opening in the mask, and the GaN layer grown on the mask has few dislocations, but is still directly above the opening in the mask. A number of dislocations are generated in the GaN layer that has grown.
  • the size of the opening of the mask is reduced, the dislocation density in the GaN layer can also be reduced.
  • the size of the opening cannot be smaller than a predetermined area. Therefore, there is a problem that the area that can be effectively used as a device is limited in the manufactured laminated structure.
  • the laminated structure manufactured in this manner is then processed by a predetermined processing technique.
  • a gate electrode, a source electrode, a drain electrode, etc. are arranged on the GaN layer, and they are assembled into, for example, an FET, etc.
  • the substrate is, for example, a Si substrate, it is placed on the substrate side.
  • Leakage current may flow on the order of mA.
  • a Si substrate having a resistivity higher than that of a true Si semiconductor cannot be manufactured, so that a Si substrate with sufficiently high resistance cannot be obtained. This is because the blocked current flows through the Si substrate.
  • An object of the present invention is to solve the above-described problem in the conventional stacked structure in which the buffer layer is made of A1N or GaN, and that a crack is generated in the thick crystal growth layer formed on the buffer layer.
  • An object of the present invention is to provide a novel stacked structure of a group III-V nitride semiconductor which is designed so that current is hardly generated, and a method of manufacturing the same.
  • Another object of the present invention is to suppress the occurrence of dislocations in a thick crystal growth layer even when the lattice mismatch with the substrate to be used is large, and the crystal is of high quality.
  • An object of the present invention is to provide a stacked structure of a group nitride semiconductor and a method of manufacturing the same. Disclosure of the invention
  • the buffer layer and the crystal growth layer are both made of an mv group nitride semiconductor.
  • the crystal growth layer has a film thickness of 10 O nm or more, the crystal growth layer is free from cracks and has a mirror-finished surface.
  • a substrate formed over the entire surface of the substrate, and a lower layer portion formed of AlxGa! - ⁇ (X is A number that satisfies 0 x x 1) (y is a number satisfying 0.5 ⁇ y ⁇ l, x and y), and a buffer layer including at least one unit buffer layer having a two-layer structure, and A stacked structure of 111 group-V nitride semiconductor (hereinafter referred to as a stacked structure B) having a crystal growth layer of a group-V nitride semiconductor, and
  • a stacked structure C an MV group nitride semiconductor
  • a method for manufacturing a laminated structure of an m-V nitride semiconductor comprising the following steps:
  • a first m-v nitride semiconductor is formed on at least a part of the surface of the substrate by an epitaxial crystal growth method having a growth temperature of 600 to 90 O: to form a buffer layer. Performing the steps; and
  • manufacturing method ⁇ Manufacturing method of laminated structure of V nitride semiconductor
  • the entire surface of the substrate is covered by the epitaxial crystal growth method,
  • Al x G a ⁇ X N (x is 0 ⁇ a lower layer consisting of A l yG a! — y N (y is a number satisfying 0.5 ⁇ y ⁇ l, x ⁇ y) and a lower layer consisting of are sequentially formed to form at least one unit buffer layer having a two-layer structure, and a crystal growth layer made of a second 111-V nitride semiconductor is formed on the upper layer of the buffer layer.
  • a method for manufacturing a laminated structure of 111-V nitride semiconductor (hereinafter referred to as manufacturing method B), and
  • An insulating thin film in which holes reaching the surface of the substrate are distributed is formed so as to cover the entire surface of the substrate, and the holes are formed by an epitaxy crystal growth method at a growth temperature of 600 to 900 ° C.
  • a buffer layer made of a first MV group nitride semiconductor is formed therein, and then a crystal is grown from the buffer layer by a selective lateral growth method to cover the entire surface of the insulating thin film.
  • FIG. 1 is a sectional view showing an example A of a laminated structure of the present invention.
  • FIG. 2 is a cross-sectional view showing an example B of the laminated structure of the present invention.
  • FIG. 3 is a cross-sectional view showing an example C of the laminated structure of the present invention.
  • FIG. 4 is a cross-sectional view showing a state where an insulating thin film is formed on a substrate.
  • Figure 5 is a sectional view showing a state in which formation of the S I_ ⁇ 2 thin film on a substrate.
  • FIG. 6 is a cross-sectional view showing a state where a metal is directly attached to an insulating thin film.
  • FIG. 7 is a cross-sectional view showing a state in which holes are formed in the SiO 2 thin film by heating the substrate of FIG.
  • FIG. 8 is a cross-sectional view showing a state where the holes of the SiO 2 thin film are partially filled with the first III-V nitride semiconductor.
  • BEST MODE FOR CARRYING OUT THE INVENTION in the multilayer structure of the present invention, in any of the multilayer structures A, B, and C, the thickness of the crystal growth layer formed on the uppermost layer is set to 100 nm or more in consideration of the use as a starting material of the semiconductor device. Is done.
  • the multilayer structure of the present invention no cracks are generated even though the crystal growth layer is as thick as 10 Onm or more, and the surface of the crystal growth layer has a flat and mirror-like state. It is characterized by the following.
  • the multilayer structure C there is almost no dislocation defect in the thick crystal growth layer, and the crystal has a feature that it is a high-quality and virtually single crystal. I have.
  • the substrate used for manufacturing the laminated structure of the present invention may be a sapphire substrate as in the related art, but may be a diamond-structured substrate such as a Si substrate, a GaAs substrate, or a GaP substrate. It may be of a sphalerite type such as a substrate. Specifically, S i substrate, GaAs substrate, GaP substrate, S i C substrate, a sapphire substrate, Zn O board, A 1N substrate, Z rB 2 substrate, NaGa_ ⁇ 3 substrate, L i Ga_ ⁇ 3 substrate, Sc A and the like can be used LMg0 4 substrate. Among these, the Si substrate is preferred in that it is easily available and inexpensive. Either of these substrates can be used to form a crack-free thick GaN-based crystal growth layer. First, the laminated structure A and the manufacturing method A will be described.
  • Fig. 1 shows an example of the laminated structure A.
  • a buffer layer 2 made of a first IE-V nitride semiconductor is formed so as to cover one entire surface of a substrate 1, and a second III-V nitride is formed on this buffer layer.
  • a crystal growth layer made of a semiconductor is formed.
  • the first III-V nitride semiconductor constituting the buffer layer 2 is Al (0 ⁇ ⁇ 1) is used.
  • the second III-V nitride semiconductor is not particularly limited, and is appropriately selected in relation to a target optical element or electronic device.
  • a target optical element or electronic device For example, GaN, InN, InGaN, InA l GaN, Al GaN, GaNAs, GaNP, In One or more selected from the group of GaNAsP and InA1GaNasP can be used.
  • the laminated structure A is manufactured by the manufacturing method A. Specifically, an epitaxial crystal growth method such as the MOCVD method or the GSMBE method is applied on the substrate 1 to form a buffer layer (Al GaN layer) 2 and a crystal growth layer 3 having a thickness of 10 Onm or more. Are sequentially formed into a film.
  • an epitaxial crystal growth method such as the MOCVD method or the GSMBE method is applied on the substrate 1 to form a buffer layer (Al GaN layer) 2 and a crystal growth layer 3 having a thickness of 10 Onm or more. are sequentially formed into a film.
  • the growth temperature during the formation of the buffer layer 2 is set to 600 to 90. Preferably, it is set at 650 to 900 ° C.
  • the growth temperature is high, the crystal quality of the formed A 1 GaN layer 2 is also improved.
  • the growth temperature employed when forming the buffer layer 2 is appropriately set within the above temperature range in relation to the composition of A 1 GaN. For example, when forming a buffer layer of A ⁇ Ga! ⁇ N (0 ⁇ x ⁇ 0.5, more preferably 0 ⁇ x ⁇ 0.2) having a low A1 composition, the growth temperature is set to 650-850. Is preferred. This is because uniformity of the buffer layer 2 can be realized.
  • the maximum growth temperature is set at 900 ° C.
  • an A 1 source or a Ga source is introduced in advance prior to the introduction of the N source (NH 3 ), and the metal A 1 or the like is deposited on the surface of the substrate 1.
  • the metal Ga may be deposited to a thickness of several atomic layers (1 to 7 layers), and then an N source may be introduced to form an A1GaN layer on the substrate.
  • an N source (generally NH 3 ) is introduced to perform nitriding on the surface of the substrate, and then a buffer layer is formed on the nitridation surface.
  • NH 3 N source
  • nitriding with NH 3 while exposing the surface to NH 3 at a temperature of 800 at a temperature of about 5 minutes is preferable since the buffer layer formed thereafter becomes very uniform. is there.
  • the buffer layer 2 may be doped with a p-type impurity. By doing so, the buffer layer 2 has a high resistance.For example, when the FET is assembled using the laminated structure A and the buffer layer 2 is operated, the buffer layer functions as a high resistance layer. This is because the occurrence of is suppressed.
  • Such P-type impurities include, for example, one or more of Mg, Zn, C and the like, and the doping concentration is determined by the relationship with the desired resistance value. Generally, it should be set to about 1 ⁇ 10 17 to 1 ⁇ 10 21 cm ⁇ 3 . Next, the laminated structure B will be described.
  • the laminated structure B has the same configuration as the laminated structure A, except that the buffer layer has a structure in which one or more unit buffer layers described later are laminated.
  • FIG. 2 shows an example in which the buffer layer is formed of one unity buffer layer 2 ′.
  • the unit buffer layer 2 ' has a two-layer structure including a lower layer portion 2a' and an upper layer portion 2b ', each of which is composed of A 1 GaN, which is the first group IV nitride semiconductor.
  • a 1 GaN which is the first group IV nitride semiconductor.
  • the A 1 N ratio of the upper layer 2 b ′ is lower than that of the lower layer 2 a ′.
  • the crystal composition is A1N-rich.
  • the composition of the lower layer 2 a ′ is Al x G a, as in the case of the multilayer structure A.
  • the y value When represented by, the y value satisfies the relationship of 0.5 ⁇ y ⁇ 1.0 and satisfies the relationship of x ⁇ y.
  • the upper layer side is A 1 N-rich, so that the overall resistance is high.
  • the surface is smooth.
  • the unit buffer layer 2 ′ can be formed by setting the thickness of the upper layer 2 b ′ to about 10 to 20 mn. By functioning as a high resistance layer, it is possible to suppress generation of a leak current to the substrate 1 side.
  • the laminated structure B is manufactured by the manufacturing method B.
  • a unit buffer layer 2 is formed by sequentially forming a lower layer portion 2a 'and an upper layer portion 2b' having a predetermined thickness so as to cover the entire surface of the substrate 1.
  • the growth temperature is set to 600 to 90 regardless of whether the lower layer or the upper layer is formed for the same reason as in the case of the manufacturing method A.
  • the film forming operation of the lower layer portion and the upper layer portion may be performed alternately a required number of times.
  • a second mv group nitride semiconductor is formed on the formed buffer layer to form a crystal growth layer having a thickness of 100 nm or more.
  • the upper layer portion 2 b ′ and the lower layer portion 2 a ′ may be doped with a p-type impurity to increase the resistance when the unit buffer layer 2 is formed. Further, by performing the above-mentioned nitriding treatment on the surface of the substrate 1, the unity sofa layer 2 'can be made uniform and its surface can be smoothed.
  • the buffer layer in the multilayer structure B may be configured with only one unit buffer layer, but may be configured by stacking a plurality of (for example, 3 to 5) unit buffer layers.
  • the laminated structure c will be described.
  • FIG. 3 shows an example of the laminated structure C of the present invention.
  • the insulating thin film 4 is formed on the substrate 1.
  • the insulating thin film 4 has fine holes 5 extending from the surface 4 a of the insulating thin film 4 to the surface 1 a of the substrate 1.
  • the diameter of the vacancy 5 is about 5 to 1 O nm in atomic order.
  • the holes 5 are filled with a first m_v group nitride semiconductor 6 epitaxially grown on the surface 1 a of the substrate exposed in the holes 5.
  • the first IE-V nitride semiconductor 6 may fill the hole 5 and may be completely filled, but the first m-v nitride semiconductor may be filled in the hole 5. Partially filled is preferred. The following description will be made on the premise of the partial filling described above.
  • the first m-V group nitride semiconductor 6 fills the holes 5 from the surface 1a of the substrate, but does not completely fill the holes 5 but partially fills the holes.
  • the upper part of the hole 5 is unfilled.
  • the first III-V nitride semiconductor 6 partially filled in such a state functions as a buffer layer when the intended thick film 3 is formed.
  • the buffer layer 6 is partially formed on the surface of the substrate 1 and is distributed over the entire surface of the substrate. Has become.
  • the remaining unfilled portion 5 a of the vacancy 5 and the surface 4 a of the insulating thin film 4, which are present on the upper part of the buffer layer 6, are formed by the second V V It is buried in a thick crystal growth layer 3 made of a group III nitride semiconductor.
  • the crystal growth layer 3 is formed on the buffer layer 6 by using the insulating thin film 4 as a mask, as described later, on a selective lateral growth (one of epitaxy crystal growth methods).
  • ELO Crystal grown by the Epitaxial Lateral Overgrowth (ELO) method.
  • the pores 5 are fine pores having a diameter of the order of atoms. Therefore, in the crystal growth layer 3, almost no dislocation defects are generated on the insulating thin film 4, and the dislocation defects generated immediately above the buffer layer 6 in the holes 5 are extremely fine. As a whole, the proportion of dislocation defects is small in the layer 3, and the crystal is a high-quality single crystal.
  • the laminated structure C is manufactured by the manufacturing method C.
  • the semiconductor material is G a
  • an insulating thin film 4 is formed on a substrate 1 as shown in FIG.
  • the insulating thin film 4 may be any material if it has an insulating property.
  • S I_ ⁇ 2 thin film, S i N thin, T i N thin film, T a O x thin film, A 1 2 0 3 thin film , a 1 N thin film, M O_ ⁇ _X, WO x, Ru can be mentioned a thin film of metal Sani ⁇ such as T i O x.
  • a Si substrate is used as the substrate 1
  • a Si ⁇ ⁇ ⁇ 2 thin film is preferable.
  • the insulating thin film 4 is formed, for example, by the MOC VD method. It is preferable to control the film thickness to about 2 to about 100. In such a case, by appropriately selecting film forming conditions such as a film forming time, a film forming gas flow rate, and a film forming temperature, the formed insulating thin film is randomly distributed in the plane, and the diameter thereof is reduced.
  • the holes 5 in the atomic order are formed spontaneously. Note that, depending on the film forming conditions, the holes 5 may not be formed in the insulating thin film 4. Considering such a situation, it is preferable to intentionally form the holes 5 by performing the following processing on the formed insulating thin film 4.
  • a metal atom 7 such as a metal Ga or a metal In is directly attached to the surface of the SiO 2 thin film 4. Then, the entire substrate is heated to a temperature of about 600 to 100 Ot. As a result, 3 1_Rei 2 thin film 4 and the metal 0 & (or metal I n) to occur is oxidation-reduction reaction between the 7, S i 0 2 of the thin film is more volatile high S i 0 2 Convert. Then, the high volatility of S i 0 2 is released from the insulating film Then, as shown in FIG. 7, the trace is left as a vacancy 5 having a size of the atomic order of metal Ga (or metal In).
  • the adhesion amounts of the metal Ga and the metal In are each set to a thickness of 10 atomic layers or less. If the thickness is larger than 10 atomic layers, metal Ga and metal In become drops (liquid), which is inconvenient.
  • the MOCVD method is applied to the substrate shown in FIG. 7, and the first mV group nitride semiconductor is selectively grown using the Si 2 thin film 4 as a mask.
  • the first III-V nitride semiconductor is selectively nucleated from the surface 1a of the substrate in the vacancies 5 and deposited sequentially, so that as shown in FIG. A buffer layer 6 made of the first mV group nitride semiconductor is formed on the first substrate.
  • the voids 5 are not completely filled with the first ⁇ _ ⁇ group nitride semiconductor, but a space (not yet) is formed above the voids 5.
  • the buffer layer 6 is formed with a thickness such that 5a remains. It is preferable to form the buffer layer 6 so that a space portion 5a of about 550% with respect to the depth of the whole hole remains.
  • the reason is that selective lateral growth of the second mv group nitride semiconductor can be performed to form the crystal growth layer 3.
  • the first mv group nitride semiconductor used is appropriately selected in relation to the second mv group nitride semiconductor used for forming the crystal growth layer 3.
  • the group V nitride semiconductor is GaN
  • a s — a 1 ⁇ G ai _ X n n PmA si- n - m a l x I n y "ai -. can be used x -y n n P m a s 0 xy, mn ⁇ l) and solely this
  • the buffer layer 6 becomes one layer.
  • a plurality of GaN-based materials may be stacked to form the buffer layer 6 into a multilayer structure.
  • a multilayer structure includes, for example, a unit buffer layer of a multilayer structure B. It can be mentioned buffer layer, on the outer, Al GaNZGaN, A 1 ING aN / I n G aN, A 1 x I n y G a preparative x - V NZA 1 x I n v G a 2 _ X _ "n D As i- n, A 1 x I n y G a _ x _ y n n A s 1 -!
  • n / A 1 x I n y G aj _ x _ y n n p m s i- n - m (0 ⁇ x, y, m, n ⁇ l) etc. may be sequentially laminated to form a buffer layer.
  • the growth temperature at the time of forming the buffer layer 6 is set at 600 to 900 ° C., preferably 650 to 900 ° C. for the same reason as in the case of the laminated structures A and B.
  • the buffer layer 6 is formed of A 1 GaN, as described above for the stacked structures A and B, the metal A 1 and the metal Ga are applied to the substrate surface 1 a prior to the introduction of the N source. It is preferable to keep it adhered or to perform a nitriding treatment on the surface of the substrate. This is because the buffer layer 6 is made uniform, whereby the surface of the thick crystal growth layer 3 formed thereon becomes flat and exhibits a mirror-like state.
  • a p-type impurity may be doped during the formation of the buffer layer 6 to take measures to suppress the generation of a leak current.
  • the composition of A 1 is 0 ⁇ x
  • the second IE-V nitride semiconductor is crystal-grown on the substrate shown in FIG. 8 by the selective lateral growth method to produce the laminated structure C shown in FIG. I do.
  • this selective lateral growth method first, the second]]! — Crystal growth of the group V nitride semiconductor proceeds on the buffer layer 6, and the upper space portion 5a in the vacancy becomes the second space. It is buried with HI-V nitride semiconductor. After the completion of the burying in the holes, the selective lateral growth proceeds on the surface 4a of the insulating thin film 4, and the second! [[— Crystal growth layer made of a group V nitride semiconductor is formed. 3 is formed.
  • the pores 5 are ultrafine pores having a diameter on the order of atoms, it can be said that the ratio of the whole diameter area of the pores 5 to the crystal growth surface is extremely small.
  • Example 1 the dislocation density of threading dislocations in the formed crystal growth layer 3 is extremely low, and the crystallinity of the crystal growth layer 3 is of high quality as a whole.
  • Example 1 the dislocation density of threading dislocations in the formed crystal growth layer 3 is extremely low, and the crystallinity of the crystal growth layer 3 is of high quality as a whole.
  • a laminated structure A was manufactured as follows.
  • the temperature of the Si substrate was raised to 1030 ° C., and TMG 58 nmol / min and NH 3 12 L min were introduced for 15 minutes to form a GaN layer having a thickness of 500 nm.
  • Example 2 the substrate was taken out of the apparatus, and the surface of the GaN layer was visually observed.
  • the mirror surface had a metallic luster. No cracks were observed at all, and it was confirmed and confirmed that high quality crystals were formed.
  • ⁇ -A1 having a thickness of 50 nm was obtained by simultaneously introducing cyclopentanenyl magnesium at a flow rate of 5 nmolZmin in addition to TMG, TMA, and NH 3 . . 3 Ga Q. 7 N cyclopropyl Petain Genis Le mug after forming the buffer layer
  • the supply of Nesium was cut off, the temperature of the Si substrate was raised to 1030 ° C, and TMG 58 ⁇ mol / min, NH 3 12 L / min, and n-type dopant Si H 4 2n mol Zmin were introduced for 15 minutes.
  • An n-type GaN layer having a thickness of 50 Onm and a carrier concentration of 2 ⁇ 1.0 17 cm ⁇ 3 was formed. No cracks were observed in the GaN layer, and the surface was a mirror-like metallic surface.
  • a GaN-based MESFET was fabricated by assembling the gate electrode, source electrode, and drain electrode with this layered structure.
  • the gate electrode was formed by depositing PtZAu, and the source electrode and the drain electrode were formed by depositing A1 / Ti / Au.
  • the gate length was set to 2 // m and the gate width was set to 2 Ocm.
  • This MES FET was a withstand voltage of 600 V, an operating current of 1 OA, and a leakage current of 1 A or less.
  • the MESFET also continued to operate at 40 O.
  • Example 3
  • a laminated structure B was manufactured as follows.
  • the temperature of the Si substrate was raised to 1050, TMG5 On mol / min, NH 3 12 LZmin were introduced for 15 minutes, and the n-type dopant S i H 2 n mol / min was increased to 15%. Then, an n-type GaN layer having a thickness of 50 nm was formed on the unit buffer layer at a carrier concentration of 2 ⁇ 10 7 cm ⁇ 3 .
  • the substrate was taken out of the apparatus, and the surface of the GaN layer was visually observed. Mirror surface with metallic luster. No crack was observed in the GaN layer.
  • the laminated structure A was manufactured under the same conditions as in Example 1 except that a sapphire substrate was used instead of the Si substrate.
  • Example 5 As in the case of Example 1, this laminated structure had a mirror-finished surface, no cracks, and high quality crystals.
  • the laminated structure C was manufactured as follows.
  • TMG 58n mol Xmin
  • TMA as A 1 source
  • ⁇ source 121 / lin
  • the substrate temperature was raised to 1300 ° C., the supply of TMA was stopped, and GaN was grown for 15 minutes to form a thick film having a thickness of 50 Onm.
  • the substrate was taken out of the apparatus and the GaN thick film was visually observed.
  • the surface was extremely flat and had a metallic luster mirror surface.
  • the present invention even if the thickness is 10 Onm or more, no cracks are generated, the surface is flat and mirror-like, and the crystal is of high quality.
  • a GaN-based crystal growth layer of a film can be formed. This is an effect obtained by setting the growth temperature of the buffer layer formed on the substrate to a high temperature of 600 to 900. Further, according to the present invention, it is possible to suppress the occurrence of a leak current by making the buffer layer have a high resistance.
  • the laminated structure of the present invention it is possible to provide a material such as a GaN-based FET that operates at a high withstand voltage and a low on-resistance, and its industrial value is extremely large.

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Abstract

Cette invention concerne une structure multicouche comprenant une couche de croissance des cristaux de semi-conducteur GaN de bonne qualité dans laquelle une couche de croissance des cristaux d'un semi-conducteur de nitrure d'éléments du groupe III-V tel qu'un GaN est formée sur un substrat, une couche tampon de AlxGa1-xN (0<x<1) étant interposée entre la couche de croissance des cristaux et le substrat. Cette invention concerne également un procédé de production d'une telle structure selon lequel une couche tampon de AlxGa1-xN (0<x<1) est formée sur un substrat à une température de croissance comprise entre 600 et 900 °C et une couche de croissances des cristaux d'un semi-conducteur de nitrure d'éléments du groupe III-V est formée sur la couche tampon.
PCT/JP2003/001935 2002-02-28 2003-02-21 Structure multicouche a semi-conducteur a base de nitrure d'elements du groupe iii-v et son procede de production WO2003073514A1 (fr)

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JP2002-54527 2002-02-28
JP2002054527 2002-02-28
JP2002317878A JP4593067B2 (ja) 2002-10-31 2002-10-31 半導体材料の積層構造の製造方法
JP2002-317878 2002-10-31
JP2003-29899 2003-02-06
JP2003029899A JP4329984B2 (ja) 2002-02-28 2003-02-06 Ｉｉｉ−ｖ族窒化物半導体の層構造体、その製造方法

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012127738A1 (fr) * 2011-03-22 2012-09-27 住友電気工業株式会社 SUBSTRAT DE GaN COMPOSÉ ET PROCÉDÉ DE PRODUCTION ASSOCIÉ, ET DISPOSITIF SEMI-CONDUCTEUR DE NITRURE DU GROUPE III ET PROCÉDÉ DE PRODUCTION ASSOCIÉ

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JPH04321280A (ja) * 1991-04-19 1992-11-11 Nichia Chem Ind Ltd 発光ダイオード
WO1995017019A1 (fr) * 1993-12-13 1995-06-22 Cree Research, Inc. Structure tampon entre du carbure du silicium et du nitrure de gallium et dispositifs semi-conducteurs ainsi obtenus
US20010015437A1 (en) * 2000-01-25 2001-08-23 Hirotatsu Ishii GaN field-effect transistor, inverter device, and production processes therefor

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JPH04321280A (ja) * 1991-04-19 1992-11-11 Nichia Chem Ind Ltd 発光ダイオード
WO1995017019A1 (fr) * 1993-12-13 1995-06-22 Cree Research, Inc. Structure tampon entre du carbure du silicium et du nitrure de gallium et dispositifs semi-conducteurs ainsi obtenus
US20010015437A1 (en) * 2000-01-25 2001-08-23 Hirotatsu Ishii GaN field-effect transistor, inverter device, and production processes therefor

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Haoxiang Zhang et al., "Epitaxial growth of wurtzite GaN on Si(111) by a vacuum reactive evaporation", Journal of Applied Physics, 15 March 2000, Vol. 87, No. 6, pages 2830 - 2834 *
M. Seon et al., "Selective growth of high quality GaN on Si(111) substrates", Applied Physics Letters, 03 April 2000, Vol. 76, No. 14, pages 1842 - 1844 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012127738A1 (fr) * 2011-03-22 2012-09-27 住友電気工業株式会社 SUBSTRAT DE GaN COMPOSÉ ET PROCÉDÉ DE PRODUCTION ASSOCIÉ, ET DISPOSITIF SEMI-CONDUCTEUR DE NITRURE DU GROUPE III ET PROCÉDÉ DE PRODUCTION ASSOCIÉ
JP2012199398A (ja) * 2011-03-22 2012-10-18 Sumitomo Electric Ind Ltd 複合ＧａＮ基板およびその製造方法、ならびにＩＩＩ族窒化物半導体デバイスおよびその製造方法

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