WO2003071689A3 - Kombinierter ver- und entschachteler sowie turbo-decodierer mit kombiniertem ver- und entschachteler - Google Patents
Kombinierter ver- und entschachteler sowie turbo-decodierer mit kombiniertem ver- und entschachteler Download PDFInfo
- Publication number
- WO2003071689A3 WO2003071689A3 PCT/DE2003/000145 DE0300145W WO03071689A3 WO 2003071689 A3 WO2003071689 A3 WO 2003071689A3 DE 0300145 W DE0300145 W DE 0300145W WO 03071689 A3 WO03071689 A3 WO 03071689A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- deinterleaver
- combined
- interleaver
- address generator
- combined interleaver
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2782—Interleaver implementations, which reduce the amount of required interleaving memory
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
- H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
- H03M13/2714—Turbo interleaver for 3rd generation partnership project [3GPP] universal mobile telecommunications systems [UMTS], e.g. as defined in technical specification TS 25.212
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/276—Interleaving address generation
- H03M13/2764—Circuits therefore
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2771—Internal interleaver for turbo codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
Landscapes
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Error Detection And Correction (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
Abstract
Eine kombinierte Ver- und Entschachtelungsschaltung (IDL1) weist einen ersten Datenspeicher (RAM) zum temporären Speichern der zu ver- bzw. entschachtelnden Daten auf. Ein erster Adressgenerator erzeugt eine Sequenz fortlaufender Adressen und ein zweiter Adressgenerator (AG) erzeugt eine die Verschachtelungsvorschrift (a(i)) repräsentierende Sequenz von Adressen. Ein Logikmittel (XOR, MUX) bewirkt, dass der Datenspeicher (RAM) im Verschachtelungsmodus bei einem Lesevorgang und im Entschachtelungsmodus bei einem Schreibvorgang von dem zweiten Adressgenerator (AG) adressiert wird.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/920,902 US20050034046A1 (en) | 2002-02-18 | 2004-08-18 | Combined interleaver and deinterleaver, and turbo decoder comprising a combined interleaver and deinterleaver |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10206727.9 | 2002-02-18 | ||
DE10206727A DE10206727A1 (de) | 2002-02-18 | 2002-02-18 | Kombinierter Ver-und Entschachteler sowie Turbo-Decodierer mit kombiniertem Ver-und Entschachteler |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/920,902 Continuation US20050034046A1 (en) | 2002-02-18 | 2004-08-18 | Combined interleaver and deinterleaver, and turbo decoder comprising a combined interleaver and deinterleaver |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2003071689A2 WO2003071689A2 (de) | 2003-08-28 |
WO2003071689A3 true WO2003071689A3 (de) | 2003-12-31 |
Family
ID=27635101
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2003/000145 WO2003071689A2 (de) | 2002-02-18 | 2003-01-20 | Kombinierter ver- und entschachteler sowie turbo-decodierer mit kombiniertem ver- und entschachteler |
Country Status (4)
Country | Link |
---|---|
US (1) | US20050034046A1 (de) |
CN (1) | CN1633750A (de) |
DE (1) | DE10206727A1 (de) |
WO (1) | WO2003071689A2 (de) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050097046A1 (en) | 2003-10-30 | 2005-05-05 | Singfield Joy S. | Wireless electronic check deposit scanning and cashing machine with web-based online account cash management computer application system |
CA2869452C (en) | 2004-10-12 | 2016-01-19 | Tq Delta, Llc | Resource sharing in a telecommunications environment |
US7502982B2 (en) * | 2005-05-18 | 2009-03-10 | Seagate Technology Llc | Iterative detector with ECC in channel domain |
US7360147B2 (en) * | 2005-05-18 | 2008-04-15 | Seagate Technology Llc | Second stage SOVA detector |
US7395461B2 (en) * | 2005-05-18 | 2008-07-01 | Seagate Technology Llc | Low complexity pseudo-random interleaver |
EP1966918A2 (de) * | 2005-11-30 | 2008-09-10 | Tuvia Apelewicz | Neuartige verteilte basisstationsarchitektur |
US8335956B2 (en) | 2006-04-12 | 2012-12-18 | Tq Delta, Llc | Packet retransmission and memory sharing |
WO2008032261A2 (en) | 2006-09-12 | 2008-03-20 | Nxp B.V. | Deinterleaver for a multi-stage interleaving scheme with processing of bit pairs |
US7873200B1 (en) | 2006-10-31 | 2011-01-18 | United Services Automobile Association (Usaa) | Systems and methods for remote deposit of checks |
US8708227B1 (en) | 2006-10-31 | 2014-04-29 | United Services Automobile Association (Usaa) | Systems and methods for remote deposit of checks |
US9058512B1 (en) | 2007-09-28 | 2015-06-16 | United Services Automobile Association (Usaa) | Systems and methods for digital signature detection |
US9159101B1 (en) * | 2007-10-23 | 2015-10-13 | United Services Automobile Association (Usaa) | Image processing |
US10380562B1 (en) | 2008-02-07 | 2019-08-13 | United Services Automobile Association (Usaa) | Systems and methods for mobile deposit of negotiable instruments |
US10504185B1 (en) | 2008-09-08 | 2019-12-10 | United Services Automobile Association (Usaa) | Systems and methods for live video financial deposit |
US8452689B1 (en) | 2009-02-18 | 2013-05-28 | United Services Automobile Association (Usaa) | Systems and methods of check detection |
US10956728B1 (en) | 2009-03-04 | 2021-03-23 | United Services Automobile Association (Usaa) | Systems and methods of check processing with background removal |
US8432961B2 (en) * | 2009-06-11 | 2013-04-30 | Lg Electronics Inc. | Transmitting/receiving system and method of processing broadcast signal in transmitting/receiving system |
US9779392B1 (en) | 2009-08-19 | 2017-10-03 | United Services Automobile Association (Usaa) | Apparatuses, methods and systems for a publishing and subscribing platform of depositing negotiable instruments |
US8977571B1 (en) | 2009-08-21 | 2015-03-10 | United Services Automobile Association (Usaa) | Systems and methods for image monitoring of check during mobile deposit |
US9129340B1 (en) | 2010-06-08 | 2015-09-08 | United Services Automobile Association (Usaa) | Apparatuses, methods and systems for remote deposit capture with enhanced image detection |
US20130142057A1 (en) * | 2011-12-01 | 2013-06-06 | Broadcom Corporation | Control Channel Acquisition |
US10380565B1 (en) | 2012-01-05 | 2019-08-13 | United Services Automobile Association (Usaa) | System and method for storefront bank deposits |
US9286514B1 (en) | 2013-10-17 | 2016-03-15 | United Services Automobile Association (Usaa) | Character count determination for a digital image |
CN105812089B (zh) * | 2014-12-31 | 2018-12-18 | 晨星半导体股份有限公司 | 适用于第二代地面数字视频广播系统的解交错程序的数据处理电路及方法 |
US10506281B1 (en) | 2015-12-22 | 2019-12-10 | United Services Automobile Association (Usaa) | System and method for capturing audio or video data |
US11030752B1 (en) | 2018-04-27 | 2021-06-08 | United Services Automobile Association (Usaa) | System, computing device, and method for document detection |
US11900755B1 (en) | 2020-11-30 | 2024-02-13 | United Services Automobile Association (Usaa) | System, computing device, and method for document detection and deposit processing |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010014962A1 (en) * | 1999-02-26 | 2001-08-16 | Kazuhisa Obuchi | Turbo decoding apparatus and interleave-deinterleave apparatus |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5912898A (en) * | 1997-02-27 | 1999-06-15 | Integrated Device Technology, Inc. | Convolutional interleaver/de-interleaver |
US6304985B1 (en) * | 1998-09-22 | 2001-10-16 | Qualcomm Incorporated | Coding system having state machine based interleaver |
US6353900B1 (en) * | 1998-09-22 | 2002-03-05 | Qualcomm Incorporated | Coding system having state machine based interleaver |
JP3445525B2 (ja) * | 1999-04-02 | 2003-09-08 | 松下電器産業株式会社 | 演算処理装置及び方法 |
KR100762612B1 (ko) * | 2001-12-07 | 2007-10-01 | 삼성전자주식회사 | 터보 복호화 장치에서 인터리버와 디인터리버간 메모리공유 장치 및 방법 |
-
2002
- 2002-02-18 DE DE10206727A patent/DE10206727A1/de not_active Withdrawn
-
2003
- 2003-01-20 CN CNA038040638A patent/CN1633750A/zh active Pending
- 2003-01-20 WO PCT/DE2003/000145 patent/WO2003071689A2/de not_active Application Discontinuation
-
2004
- 2004-08-18 US US10/920,902 patent/US20050034046A1/en not_active Abandoned
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010014962A1 (en) * | 1999-02-26 | 2001-08-16 | Kazuhisa Obuchi | Turbo decoding apparatus and interleave-deinterleave apparatus |
Non-Patent Citations (4)
Title |
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HONG S ET AL: "DESIGN AND IMPLEMENTATION OF A LOW COMPLEXITY VLSI TURBO-CODE DECODER ARCHITECTURE FOR LOW ENERGY MOBILE WIRELESS COMMUNICATIONS", JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL. IMAGE, AND VIDEO TECHNOLOGY, KLUWER ACADEMIC PUBLISHERS, DORDRECHT, NL, vol. 24, no. 1, February 2000 (2000-02-01), pages 43 - 56, XP000920089, ISSN: 0922-5773 * |
IN SAN JEON ET AL: "An efficient turbo decoder architecture for IMT2000", VLSI AND CAD, 1999. ICVC '99. 6TH INTERNATIONAL CONFERENCE VLSI AND CAD IN SEOUL, SOUTH KOREA 26-27 OCT. 1999, PISCATAWAY, NJ, USA,IEEE, US, 26 October 1999 (1999-10-26), pages 301 - 304, XP010370101, ISBN: 0-7803-5727-2 * |
WORM A ET AL: "VLSI architectures for high-speed MAP decoders", PROCEEDINGS OF 14TH INTERNATIONAL CONFERENCE ON VLSI DESIGN IN BENGALORE (INDIA), IEEE, 3 January 2001 (2001-01-03) - 7 January 2001 (2001-01-07), pages 446 - 453, XP010531492 * |
WU P H-Y ET AL: "IMPLEMENTATION OF A LOW COMPLEXITY, LOW POWER, INTEGER-BASED TURBO DECODER", GLOBECOM'01. 2001 IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE. SAN ANTONIO, TX, NOV. 25 - 29, 2001, IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE, NEW YORK, NY: IEEE, US, vol. 2 OF 6, 25 November 2001 (2001-11-25), pages 946 - 951, XP001099245, ISBN: 0-7803-7206-9 * |
Also Published As
Publication number | Publication date |
---|---|
WO2003071689A2 (de) | 2003-08-28 |
CN1633750A (zh) | 2005-06-29 |
US20050034046A1 (en) | 2005-02-10 |
DE10206727A1 (de) | 2003-08-28 |
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