WO2003048953A3 - Verfahren zum bestimmen eines abstands von prozessoreinheiten zu mindestens einer referenzposition in einer prozessor-anordnung und prozessor-anordnung - Google Patents
Verfahren zum bestimmen eines abstands von prozessoreinheiten zu mindestens einer referenzposition in einer prozessor-anordnung und prozessor-anordnung Download PDFInfo
- Publication number
- WO2003048953A3 WO2003048953A3 PCT/DE2002/004373 DE0204373W WO03048953A3 WO 2003048953 A3 WO2003048953 A3 WO 2003048953A3 DE 0204373 W DE0204373 W DE 0204373W WO 03048953 A3 WO03048953 A3 WO 03048953A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- processor
- separation
- reference position
- processor unit
- arrangement
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Controls And Circuits For Display Device (AREA)
- Measurement Of Velocity Or Position Using Acoustic Or Ultrasonic Waves (AREA)
- Multi Processors (AREA)
Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/496,696 US20050078115A1 (en) | 2001-11-30 | 2002-11-28 | Method for determination of a separation from processor units to at least one reference position in a processor arrangement and processor arrangement |
EP02798255A EP1449110A2 (de) | 2001-11-30 | 2002-11-28 | Verfahren zum bestimmen eines abstands von prozessoreinheiten zu mindestens einer referenzposition in einer prozessor-anordnung und prozessor-anordnung |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE2001158784 DE10158784B4 (de) | 2001-11-30 | 2001-11-30 | Verfahren zum Bestimmen eines Abstands von Prozessoreinheiten zu mindestens einer Referenzposition in einer Prozessor-Anordnung und Prozessor-Anordnung |
DE10158781.3 | 2001-11-30 | ||
DE2001158781 DE10158781A1 (de) | 2001-11-30 | 2001-11-30 | Pixel-Anordnung |
DE10158784.8 | 2001-11-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2003048953A2 WO2003048953A2 (de) | 2003-06-12 |
WO2003048953A3 true WO2003048953A3 (de) | 2003-11-06 |
Family
ID=26010689
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2002/004373 WO2003048953A2 (de) | 2001-11-30 | 2002-11-28 | Verfahren zum bestimmen eines abstands von prozessoreinheiten zu mindestens einer referenzposition in einer prozessor-anordnung und prozessor-anordnung |
Country Status (3)
Country | Link |
---|---|
US (1) | US20050078115A1 (de) |
EP (1) | EP1449110A2 (de) |
WO (1) | WO2003048953A2 (de) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7340644B2 (en) * | 2002-12-02 | 2008-03-04 | Marvell World Trade Ltd. | Self-reparable semiconductor and method thereof |
US7185225B2 (en) * | 2002-12-02 | 2007-02-27 | Marvell World Trade Ltd. | Self-reparable semiconductor and method thereof |
US20060001669A1 (en) * | 2002-12-02 | 2006-01-05 | Sehat Sutardja | Self-reparable semiconductor and method thereof |
DE10335819A1 (de) * | 2003-08-05 | 2005-03-17 | Infineon Technologies Ag | Prozessor-Anordnung, Textilgewebestruktur, Flächenverkleidungsstruktur und Verfahren zum Übertragen von elektronischen Nachrichten zwischen Prozessoren einer Prozessor-Anordnung |
AU2006201825B2 (en) * | 2005-05-02 | 2012-01-19 | Roads And Maritime Services | Variable Message Sign |
DE102005052005B4 (de) * | 2005-10-31 | 2007-10-18 | Infineon Technologies Ag | Prozessor-Anordnung |
US20080043003A1 (en) * | 2006-08-17 | 2008-02-21 | Vogsland Robin O | Smart display pixel |
US8718079B1 (en) | 2010-06-07 | 2014-05-06 | Marvell International Ltd. | Physical layer devices for network switches |
US9153171B2 (en) * | 2012-12-17 | 2015-10-06 | LuxVue Technology Corporation | Smart pixel lighting and display microcontroller |
DE102017106812B4 (de) | 2016-05-09 | 2018-01-11 | Elmos Semiconductor Aktiengesellschaft | Vorrichtung und zugehöriges Verfahren zur selbständigen Adresskonfiguration konfektionierbarer, flexibler LED-Sensor-Bänder |
DE102017106813B4 (de) | 2016-05-09 | 2018-01-18 | Elmos Semiconductor Aktiengesellschaft | Vorrichtung und zugehöriges Verfahren zur selbständigen Adresskonfiguration konfektionierbarer, flexibler Sensor-Bänder |
DE102017106811B4 (de) | 2016-05-09 | 2018-01-11 | Elmos Semiconductor Aktiengesellschaft | Vorrichtung und zugehöriges Verfahren zur selbständigen Adresskonfiguration konfektionierbarer, flexibler LED-Bänder |
DE102017109247B4 (de) | 2017-04-28 | 2024-05-08 | Elmos Semiconductor Se | Verfahren zur Bestimmung der physikalischen Position einer Leuchtmittelgruppe innerhalb eines eindimensionalen Leuchtbands mit mehreren Leuchtmittelgruppen |
DE102018102998A1 (de) * | 2018-02-09 | 2019-08-14 | Infineon Technologies Ag | Vorrichtung, Verfahren und Computerprogramm zum Vergleichen der Ausgabe von Sensorzellen |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63240667A (ja) * | 1987-03-28 | 1988-10-06 | Nippon Telegr & Teleph Corp <Ntt> | 並列デ−タ処理装置 |
WO2001090915A2 (en) * | 2000-05-22 | 2001-11-29 | Gazelle Technology Corporation | Processor array and parallel data processing methods |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5262771A (en) * | 1988-03-03 | 1993-11-16 | U.S. Philips Corporation | Method for addressing processor units |
US5600354A (en) * | 1992-04-02 | 1997-02-04 | Hewlett-Packard Company | Wrap-around flex with address and data bus |
US5917464A (en) * | 1994-10-18 | 1999-06-29 | Xerox Corporation | Combination of 2-D detector array with display for image processing |
US5644327A (en) * | 1995-06-07 | 1997-07-01 | David Sarnoff Research Center, Inc. | Tessellated electroluminescent display having a multilayer ceramic substrate |
DE19710855A1 (de) * | 1997-03-15 | 1998-10-01 | Dambach Werke Gmbh | Leuchtdiodenmatrix-Anzeigevorrichtung |
US5941714A (en) * | 1997-09-23 | 1999-08-24 | Massachusetts Institute Of Technology | Digital communication, programmable functioning and data transfer using modular, hinged processor elements |
US6240478B1 (en) * | 1998-10-30 | 2001-05-29 | Eaton Corporation | Apparatus and method for addressing electronic modules |
-
2002
- 2002-11-28 EP EP02798255A patent/EP1449110A2/de not_active Withdrawn
- 2002-11-28 US US10/496,696 patent/US20050078115A1/en not_active Abandoned
- 2002-11-28 WO PCT/DE2002/004373 patent/WO2003048953A2/de not_active Application Discontinuation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63240667A (ja) * | 1987-03-28 | 1988-10-06 | Nippon Telegr & Teleph Corp <Ntt> | 並列デ−タ処理装置 |
WO2001090915A2 (en) * | 2000-05-22 | 2001-11-29 | Gazelle Technology Corporation | Processor array and parallel data processing methods |
Non-Patent Citations (2)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 013, no. 047 (P - 822) 3 February 1989 (1989-02-03) * |
YOUN H Y ET AL: "Near optimal embedding of binary tree architecture in VLSI", DISTRIBUTED COMPUTING SYSTEMS, 1988., 8TH INTERNATIONAL CONFERENCE ON SAN JOSE, CA, USA 13-17 JUNE 1988, WASHINGTON, DC, USA,IEEE COMPUT. SOC. PR, US, 13 June 1988 (1988-06-13), pages 86 - 93, XP010013075, ISBN: 0-8186-0865-X * |
Also Published As
Publication number | Publication date |
---|---|
WO2003048953A2 (de) | 2003-06-12 |
US20050078115A1 (en) | 2005-04-14 |
EP1449110A2 (de) | 2004-08-25 |
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