WO2003026006A3 - Anordnung eines halbleiterchips in einem gehäuse, chipkarte und chipmodul - Google Patents

Anordnung eines halbleiterchips in einem gehäuse, chipkarte und chipmodul Download PDF

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Publication number
WO2003026006A3
WO2003026006A3 PCT/DE2002/003147 DE0203147W WO03026006A3 WO 2003026006 A3 WO2003026006 A3 WO 2003026006A3 DE 0203147 W DE0203147 W DE 0203147W WO 03026006 A3 WO03026006 A3 WO 03026006A3
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WO
WIPO (PCT)
Prior art keywords
semiconductor
housing
chip
arrangement
chip card
Prior art date
Application number
PCT/DE2002/003147
Other languages
English (en)
French (fr)
Other versions
WO2003026006A2 (de
Inventor
Kai Geyer
Harald Gundlach
Bernhard Schulte-Doeinghaus
Original Assignee
Infineon Technologies Ag
Kai Geyer
Harald Gundlach
Bernhard Schulte-Doeinghaus
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Kai Geyer, Harald Gundlach, Bernhard Schulte-Doeinghaus filed Critical Infineon Technologies Ag
Publication of WO2003026006A2 publication Critical patent/WO2003026006A2/de
Publication of WO2003026006A3 publication Critical patent/WO2003026006A3/de

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01013—Aluminum [Al]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
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    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

Das Gehäuse besitzt eine rings umgebende Abschirmung nach Art eines Faraday'schen Käfigs; oder es sind geeignete Dämpfungselemente in den Zuleitungen vorgesehen; es können auch gleichzeitig diese beiden Mittel eingesetzt sein. Auf diese Weise kann insbesondere ein Chipkarten-Modul-Gehäuse mit einer Abschirmung versehen sein. Ein Halbleiterchip (1) ist auf einem Chipträger (2) angebracht und mit einer Vergussmasse (3) umspritzt, auf deren Aussenseite eine elektrisch leitfähige Beschichtung (4) aufgebracht und mit einer Metallschicht (7) auf der Innenseite des Chipträgers verbunden ist.
PCT/DE2002/003147 2001-08-30 2002-08-28 Anordnung eines halbleiterchips in einem gehäuse, chipkarte und chipmodul WO2003026006A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10142542A DE10142542A1 (de) 2001-08-30 2001-08-30 Anordnung eines Halbleiterchips in einem Gehäuse, Chipkarte und Chipmodul
DE10142542.2 2001-08-30

Publications (2)

Publication Number Publication Date
WO2003026006A2 WO2003026006A2 (de) 2003-03-27
WO2003026006A3 true WO2003026006A3 (de) 2003-08-07

Family

ID=7697146

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2002/003147 WO2003026006A2 (de) 2001-08-30 2002-08-28 Anordnung eines halbleiterchips in einem gehäuse, chipkarte und chipmodul

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DE (1) DE10142542A1 (de)
WO (1) WO2003026006A2 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10329329B4 (de) * 2003-06-30 2005-08-18 Siemens Ag Hochfrequenz-Gehäuse und Verfahren zu seiner Herstellung

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03214691A (ja) * 1990-01-18 1991-09-19 Fujitsu Ltd フレキシブルプリント板の集積回路実装構造
US5311059A (en) * 1992-01-24 1994-05-10 Motorola, Inc. Backplane grounding for flip-chip integrated circuit
US5557142A (en) * 1991-02-04 1996-09-17 Motorola, Inc. Shielded semiconductor device package
US5639989A (en) * 1994-04-19 1997-06-17 Motorola Inc. Shielded electronic component assembly and method for making the same
WO1997025847A1 (en) * 1996-01-08 1997-07-17 Xicon Ab Shielding of electronic components embedded in plastics directly on circuit board
US5717359A (en) * 1995-04-14 1998-02-10 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit having elongated fixed potential lines to reduce noise on the lines
EP1085572A2 (de) * 1999-09-16 2001-03-21 Texas Instruments Incorporated Mit ener Halbleiterverpackung integrierterTiefpassfilter
EP1098367A2 (de) * 1999-11-05 2001-05-09 Lucent Technologies Inc. Elektronische Verpackung mit integriertem Filter

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59172253A (ja) * 1983-03-18 1984-09-28 Mitsubishi Electric Corp 半導体装置
DE19548046C2 (de) * 1995-12-21 1998-01-15 Siemens Matsushita Components Verfahren zur Herstellung von für eine Flip-Chip-Montage geeigneten Kontakten von elektrischen Bauelementen
DE19806818C1 (de) * 1998-02-18 1999-11-04 Siemens Matsushita Components Verfahren zur Herstellung eines elektronischen Bauelements, insbesondere eines mit akustischen Oberflächenwllen arbeitenden OFW-Bauelements
FR2799883B1 (fr) * 1999-10-15 2003-05-30 Thomson Csf Procede d'encapsulation de composants electroniques

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03214691A (ja) * 1990-01-18 1991-09-19 Fujitsu Ltd フレキシブルプリント板の集積回路実装構造
US5557142A (en) * 1991-02-04 1996-09-17 Motorola, Inc. Shielded semiconductor device package
US5311059A (en) * 1992-01-24 1994-05-10 Motorola, Inc. Backplane grounding for flip-chip integrated circuit
US5639989A (en) * 1994-04-19 1997-06-17 Motorola Inc. Shielded electronic component assembly and method for making the same
US5717359A (en) * 1995-04-14 1998-02-10 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit having elongated fixed potential lines to reduce noise on the lines
WO1997025847A1 (en) * 1996-01-08 1997-07-17 Xicon Ab Shielding of electronic components embedded in plastics directly on circuit board
EP1085572A2 (de) * 1999-09-16 2001-03-21 Texas Instruments Incorporated Mit ener Halbleiterverpackung integrierterTiefpassfilter
EP1098367A2 (de) * 1999-11-05 2001-05-09 Lucent Technologies Inc. Elektronische Verpackung mit integriertem Filter

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 015, no. 490 (E - 1144) 11 December 1991 (1991-12-11) *

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DE10142542A1 (de) 2003-03-27
WO2003026006A2 (de) 2003-03-27

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