WO2003017362A8 - Circuit integre avec cellule memoire dram - Google Patents

Circuit integre avec cellule memoire dram

Info

Publication number
WO2003017362A8
WO2003017362A8 PCT/FR2002/002887 FR0202887W WO03017362A8 WO 2003017362 A8 WO2003017362 A8 WO 2003017362A8 FR 0202887 W FR0202887 W FR 0202887W WO 03017362 A8 WO03017362 A8 WO 03017362A8
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
substrate
integrated circuit
capacitor
memory cell
Prior art date
Application number
PCT/FR2002/002887
Other languages
English (en)
Other versions
WO2003017362A1 (fr
Inventor
Pascale Mazoyer
Christian Caillat
Original Assignee
St Microelectronics Sa
Pascale Mazoyer
Christian Caillat
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Sa, Pascale Mazoyer, Christian Caillat filed Critical St Microelectronics Sa
Priority to JP2003522167A priority Critical patent/JP2005500695A/ja
Priority to US10/486,752 priority patent/US20040262638A1/en
Priority to EP02794818A priority patent/EP1425795A1/fr
Publication of WO2003017362A1 publication Critical patent/WO2003017362A1/fr
Publication of WO2003017362A8 publication Critical patent/WO2003017362A8/fr

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Circuit intégré comprenant un substrat (1), au moins un condensateur (9) disposé au-dessus du substrat (1) et pourvu d'une première électrode (5), d'une deuxième électrode (8), et d'un diélectrique (7) disposé entre les deux électrodes, au moins un via de connexion entre le substrat (1) et un niveau conducteur situé au-dessus du condensateur (9), et un matériau diélectrique recouvrant le substrat (1) et entourant le condensateur (9) et le via (6). Le via comprend une première portion (18) disposée entre le substrat et le niveau inférieur de la première électrode, une deuxième portion (6) disposée entre le niveau inférieur de la première électrode et le niveau supérieur de la première électrode, et une troisième portion (12) en contact avec la première portion et affleurant ledit niveau conducteur, la deuxième portion étant réalisée avec le même matériau que la première électrode du condensateur.
PCT/FR2002/002887 2001-08-16 2002-08-14 Circuit integre avec cellule memoire dram WO2003017362A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2003522167A JP2005500695A (ja) 2001-08-16 2002-08-14 Ｄｒａｍメモリ・セルを備える集積回路
US10/486,752 US20040262638A1 (en) 2001-08-16 2002-08-14 Integrated circuit with dram memory cell
EP02794818A EP1425795A1 (fr) 2001-08-16 2002-08-14 Circuit integre, notamment cellule memoire dram avec contact a faible facteur de forme et procede de fabrication

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR01/10867 2001-08-16
FR0110867A FR2828763B1 (fr) 2001-08-16 2001-08-16 Circuit integre, notamment cellule memoire dram avec contact a faible facteur de forme et procede de fabrication

Publications (2)

Publication Number Publication Date
WO2003017362A1 WO2003017362A1 (fr) 2003-02-27
WO2003017362A8 true WO2003017362A8 (fr) 2003-04-03

Family

ID=8866568

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2002/002887 WO2003017362A1 (fr) 2001-08-16 2002-08-14 Circuit integre avec cellule memoire dram

Country Status (5)

Country Link
US (1) US20040262638A1 (fr)
EP (1) EP1425795A1 (fr)
JP (1) JP2005500695A (fr)
FR (1) FR2828763B1 (fr)
WO (1) WO2003017362A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008087498A1 (fr) * 2007-01-17 2008-07-24 Stmicroelectronics Crolles 2 Sas Condensateur empilé de mémoire vive dynamique et son procédé de fabrication utilisant un polissage chimico-mécanique
KR101159900B1 (ko) * 2009-04-22 2012-06-25 에스케이하이닉스 주식회사 반도체 소자 및 그 제조방법
US8803122B2 (en) * 2012-07-31 2014-08-12 Globalfoundries Singapore Pte. Ltd. Method for forming a PCRAM with low reset current
KR102601650B1 (ko) * 2016-07-26 2023-11-13 삼성디스플레이 주식회사 표시 장치
TWI642333B (zh) 2017-10-25 2018-11-21 欣興電子股份有限公司 電路板及其製造方法
TWI642334B (zh) 2017-10-25 2018-11-21 欣興電子股份有限公司 電路板及其製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0223657A (ja) * 1988-07-12 1990-01-25 Sharp Corp 半導体メモリ素子
JPH0260162A (ja) * 1988-08-25 1990-02-28 Sony Corp 半導体メモリ
JP3623834B2 (ja) * 1995-01-31 2005-02-23 富士通株式会社 半導体記憶装置及びその製造方法
US6214727B1 (en) * 1997-02-11 2001-04-10 Micron Technology, Inc. Conductive electrical contacts, capacitors, DRAMs, and integrated circuitry, and methods of forming conductive electrical contacts, capacitors, DRAMs, and integrated circuitry
US6737696B1 (en) * 1998-06-03 2004-05-18 Micron Technology, Inc. DRAM capacitor formulation using a double-sided electrode
US5895239A (en) * 1998-09-14 1999-04-20 Vanguard International Semiconductor Corporation Method for fabricating dynamic random access memory (DRAM) by simultaneous formation of tungsten bit lines and tungsten landing plug contacts

Also Published As

Publication number Publication date
WO2003017362A1 (fr) 2003-02-27
FR2828763A1 (fr) 2003-02-21
FR2828763B1 (fr) 2004-01-16
JP2005500695A (ja) 2005-01-06
EP1425795A1 (fr) 2004-06-09
US20040262638A1 (en) 2004-12-30

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