Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
  • H03K17/10—Modifications for increasing the maximum permissible switched voltage
  • H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
  • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
  • H03K3/53—Generators characterised by the type of circuit or by the means used for producing pulses by the use of an energy-accumulating element discharged through the load by a switching device controlled by an external signal and not incorporating positive feedback
  • H03K3/57—Generators characterised by the type of circuit or by the means used for producing pulses by the use of an energy-accumulating element discharged through the load by a switching device controlled by an external signal and not incorporating positive feedback the switching device being a semiconductor device

Definitions

• This invention relates to high voltage switching apparatus, and in particular, but not exclusively to a switching apparatus for providing pulses to a pulse switched ⁇ • » load.
• ?Q is because the load is not a purely resistive load but is of a non-linear nature and includes a capacitive component .
• a known way of correcting for this voltage overshoot is to include a further capacitance in parallel with the load as shown in Figure 3.
• the load is shown as
• the invention distributes the load capacitance over the switches of the switch stack. More specifically, there is provided a high voltage switching arrangement for applying a pulse across a load, comprising a capacitor for providing electrical' energy to the load and > a switch stack for connecting the capacitor to the load, the switch stack comprising ' a plurality of switches arranged in wells, and a plurality of load capacitances in parallel across the switches.
• each switch has a capacitance nCd in : ⁇ parallel across the switch, where Cd is the required additional capacitance across the load and n is the number of switches.
• Figure 1 (referred to previously) is a graph of 20 voltage/time ! showing an ideal rise in load voltage when a switch is cl ⁇ sed;
• Figure 2 (referred to previously) is a similar graph to Figure 1 showing actual voltage rise including overshoot;
• Figure 3 (referred to previously) is a circuit diagram ?: ⁇ > if a known solution to the problem;
• Figure 4 is a schematic longitudinal view of a high voltage switching mechanism
• Figure 5 is a schematic cross-section of the line V-V jn Figure 4; 30 Figure 6 j « a circuit diagram of an equivalent representation of the known circuit of Figure 3; and
• Figure 7 shows how the capacitance of Figure 6 may be distributed in accordance with an embodiment of the invention.
• -'' ⁇ 3 Figures 4 and 5 show the switching mechanism disclosed in our earlier applications GB9928074.5 and GB9928049.7.
• the mechanism provides high voltage pulses to a high voltage load, such as a magnetron, by switching a capacitance.
• the switching is triggered by trigger pulses derived from a high voltage supply and the capacitance is also charged by that supply.
• the switching arrangement shown in Figures 4 and 5 comprises a switch stack arranged within a chamber surrounded by a plurality of capacitances.
• the switch stack comprises a number of FET modules 1, 2, 3, 4, ...n, each of which includes one or more FET switches. There may be, for
• each module may include three FET switches arranged in parallel.
• the modules are mounted in close proximity to one another and are stacked along the axis 'in Figure 1.
• each module includes a secondary transformer winding r> 6 with a common primary winding' ' 7 extending along the length of the axis to act as the primary for each module.
• the primary is used to provide power to the FET switches. Power to the switching arrangement is applied from a source 8 to a trigger driver 9 at the high voltage end of the stack
• the trigger driver is formed as a module ,: of similar dimensions to the FET modules and forms the end module of the stack.
• the load 10 for example a magnetron, is connected to an output 11' of the switching mechanism to receive pulses from the switching mechanism.
• the output 11 also provides an output 12 to a heater transformer for heating the magnetron cathode.
• the power for the transformer is provided from 'a power source 12.
• the switching mechanism is arranged within a housing
• the housing is formed of a''non-conductive material such y . as a plastics material and comprises outer and inn c walls
• annular chamber 15 16 defining an annular chamber therebetween, and an interior chamber 23 bounded by the inner walls and in which the switching stack is arranged.
• the annular chamber and the interior chamber 23 communicate via apertures 24, 25 in the
• the housing and the annular and interior chambers are rectangular in cross section .
• Four capacitors 17 , 18 , 19, 20 are arranged in the annular chamber, one on each side, and extend along the length of the chamber shielding the switching mechanism.
• the capacitors are connected at the high voltage end to the first switch module and to the load 10 at the low voltage end, which may be at ground.
• the capacitors each comprise a pl urality of parallel plates forming . capacitor elements which are interconnected so that a nominally linear voltage gradient appears f rom the power supply end to the zero volt i n end .
• the capacitors may each be 0 .15 ⁇ f .
• the unit is oil fi lled for heat dissipation and insulation .
• Oil can pass between the annular and inner chambers through passageways 24 , 25.
• An expansion tank 26 is connected to the chambers which includes a diaphragm, and i h which moves with the changes in oil volume, for example due to temperature changes .
• the switching stack also compri ses a control module 40 whi ch is mounted on the stack between the trigger driver module and the first FET- module 1 and which is of similar
• the control module controls tri ggering of the FET switches and floats at the high vol tage of -55kV but has its own It power supply to operate the control ci rcuitry .
• Figure 6 shows an equivalent circuit to the known
• switch modules 30 In a typical switch stack, there may be 75 switch modules .
• a capacitor may be placed across each of the switch modules instead of a single capacitor across the load .
• each capacitor must be nCd, where n is the number of switch modules , or looking at it another way, the - nu ber of seri es connected capacitors.
• ⁇ Cd is such that the applied capacitance greatly exceeds and swamps any stray capacitances generated at the switch.
• FIG. 7 shows this arrangement.
• each of the switches Si, S2 - Sn are shown with a capacitance nCd in parallel and a further capacitance C r> in phantom as the effect is minimal compared to the effect cjif nCs.
• the arrangement described has a number of advantages .
• a simple capacitance used in parallel with a magnetron is physically very big and expensive, typically in the order of about £50.
• nCd is arranged in parallel across each" switch, or switch module.
• each switch module comprises a number M of switches arranged in parallel
• the capacitance nCd may be distributed as nCd/M across each of the parallel switches. In practical realisations," this makes for a more flexible layout.
• the number of switches and the number of switch modules may vary

Landscapes

• Generation Of Surge Voltage And Current (AREA)
• Electronic Switches (AREA)
• Microwave Tubes (AREA)
• Power Conversion In General (AREA)

Priority Applications (4)

Applications Claiming Priority (2)

Publications (2)

Family

ID=9916706

Family Applications (1)

Country Status (6)

Cited By (1)

Families Citing this family (25)

Family Cites Families (14)

• 2001
  • 2001-06-15 GB GB0114675A patent/GB2378065B/en not_active Expired - Lifetime
• 2002
  • 2002-06-14 AU AU2002345159A patent/AU2002345159A1/en not_active Abandoned
  • 2002-06-14 EP EP02743366.3A patent/EP1396082B1/en not_active Expired - Lifetime
  • 2002-06-14 WO PCT/GB2002/002732 patent/WO2002103904A2/en not_active Ceased
  • 2002-06-14 US US10/480,527 patent/US7256637B2/en not_active Expired - Lifetime
  • 2002-06-14 JP JP2003506100A patent/JP4326940B2/ja not_active Expired - Fee Related

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