WO2002103799A3 - Verfahren zum herstellen eines speicherbauelements - Google Patents

Verfahren zum herstellen eines speicherbauelements Download PDF

Info

Publication number
WO2002103799A3
WO2002103799A3 PCT/EP2002/006512 EP0206512W WO02103799A3 WO 2002103799 A3 WO2002103799 A3 WO 2002103799A3 EP 0206512 W EP0206512 W EP 0206512W WO 02103799 A3 WO02103799 A3 WO 02103799A3
Authority
WO
WIPO (PCT)
Prior art keywords
control electrode
electrode strips
producing
memory component
memory
Prior art date
Application number
PCT/EP2002/006512
Other languages
English (en)
French (fr)
Other versions
WO2002103799A2 (de
Inventor
Dirk Toebben
Original Assignee
Infineon Technologies Ag
Dirk Toebben
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Dirk Toebben filed Critical Infineon Technologies Ag
Priority to KR1020037016505A priority Critical patent/KR100571773B1/ko
Priority to US10/480,999 priority patent/US7012003B2/en
Publication of WO2002103799A2 publication Critical patent/WO2002103799A2/de
Publication of WO2002103799A3 publication Critical patent/WO2002103799A3/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)

Abstract

Die vorliegende Erfindung schafft ein Verfahren zum Herstellen eines Speicherbauelements, das einen Speicherzellenbereich (104) mit Speicherzellen und ersten Steuerelektrodenbahnen (162) zum Ansteuern der einzelnen Speicherzellen und einen Peripheriebereich (106) mit Peripherieelementen und zweiten Steuerelektrodenbahnen (164) zum Ansteuern der Peripherieelemente aufweist. Das Verfahren ermöglicht eine nahezu beliebige Einstellung der Ausdehnung der zweiten Steuerelektrodenbahnen (164) in dem Peripheriebereich (106) auf minimale Linienbreiten ohne die Ausdehnung der ersten Steuerelektrodenbahnen (162) in dem Speicherzellenbereich (104) zu beeinflussen oder zu ändern.
PCT/EP2002/006512 2001-06-18 2002-06-13 Verfahren zum herstellen eines speicherbauelements WO2002103799A2 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020037016505A KR100571773B1 (ko) 2001-06-18 2002-06-13 메모리 소자 제조방법
US10/480,999 US7012003B2 (en) 2001-06-18 2002-06-13 Memory for producing a memory component

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10128933.2 2001-06-18
DE10128933A DE10128933A1 (de) 2001-06-18 2001-06-18 Verfahren zum Herstellen eines Speicherbauelements

Publications (2)

Publication Number Publication Date
WO2002103799A2 WO2002103799A2 (de) 2002-12-27
WO2002103799A3 true WO2002103799A3 (de) 2003-05-01

Family

ID=7688312

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2002/006512 WO2002103799A2 (de) 2001-06-18 2002-06-13 Verfahren zum herstellen eines speicherbauelements

Country Status (5)

Country Link
US (1) US7012003B2 (de)
KR (1) KR100571773B1 (de)
DE (1) DE10128933A1 (de)
TW (1) TW571399B (de)
WO (1) WO2002103799A2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI304633B (en) * 2003-08-25 2008-12-21 Promos Technologies Inc Semiconductor device and fabricating method thereof
KR100954107B1 (ko) * 2006-12-27 2010-04-23 주식회사 하이닉스반도체 반도체 소자의 제조방법
US8440569B2 (en) * 2007-12-07 2013-05-14 Cadence Design Systems, Inc. Method of eliminating a lithography operation
US8399347B2 (en) * 2010-08-23 2013-03-19 Micron Technology, Inc. Integrated circuits and methods of forming conductive lines and conductive pads therefor
CN113745228B (zh) * 2020-05-29 2024-03-29 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5289422A (en) * 1990-11-01 1994-02-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having dummy wiring pattern therein and manufacturing method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5661053A (en) * 1994-05-25 1997-08-26 Sandisk Corporation Method of making dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5289422A (en) * 1990-11-01 1994-02-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having dummy wiring pattern therein and manufacturing method thereof

Also Published As

Publication number Publication date
DE10128933A1 (de) 2003-01-02
TW571399B (en) 2004-01-11
WO2002103799A2 (de) 2002-12-27
US20050020009A1 (en) 2005-01-27
KR20040012941A (ko) 2004-02-11
KR100571773B1 (ko) 2006-04-17
US7012003B2 (en) 2006-03-14

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