WO2002097874A1 - Procede de gravure seche verticale et profonde de dielectriques - Google Patents

Procede de gravure seche verticale et profonde de dielectriques Download PDF

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Publication number
WO2002097874A1
WO2002097874A1 PCT/CA2002/000784 CA0200784W WO02097874A1 WO 2002097874 A1 WO2002097874 A1 WO 2002097874A1 CA 0200784 W CA0200784 W CA 0200784W WO 02097874 A1 WO02097874 A1 WO 02097874A1
Authority
WO
WIPO (PCT)
Prior art keywords
etching
sample
plasma source
deep
dielectric
Prior art date
Application number
PCT/CA2002/000784
Other languages
English (en)
Inventor
Boris Lamontagne
Lynden Erickson
Dan-Xia Xu
Andre Delage
Siegfried Janz
Pavel Cheben
Sylvain Charbonneau
Original Assignee
Lnl Technologies Canada Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lnl Technologies Canada Inc. filed Critical Lnl Technologies Canada Inc.
Publication of WO2002097874A1 publication Critical patent/WO2002097874A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Definitions

  • the invention relates to a method of etching of dielectrics, especially transparent dielectrics, such as S1O 2 , for example, for use in the manufacture of planar waveguides and gratings.
  • dielectrics especially transparent dielectrics, such as S1O 2
  • the manufacture of photonic devices, such as echelle gratings requires the fabrication of structures having vertical sidewalls.
  • the structures are typically made by deep (5 to 10 ⁇ m) etching of an SiO 2 layer.
  • smooth and vertical etching is critical. Non-verticality of only 2°, e.g. 88° instead of 90°, can introduce additional optical losses of 3 dB in some cases.
  • a method of etching a dielectric sample to produce vertical sidewalls comprising: performing a high rate plasma etch on said sample in the presence of a low energy ion bombardment using a main etchant gas giving a high amount of etching radicals; and controlling the sidewall profiles by varying the temperature of the sample.
  • the dielectric is typically Si02, especially silicon rich silicon glass (SRSG)
  • the etchant gas is preferably C F 8 since this gives a high etch rate by creating a high amount of etching radicals, although other suitable gases creating a high amount of etching radicals could be employed.
  • the plasma is preferably provided by a high density plasma source having an RF energy in the region of 200 watts or more.
  • An inductively coupled plasma (ICP) source enables the use of low energy ion bombardment. This gives high etching selectivity with a hard mask, typically a metal mask, such as aluminum.
  • the energy of the ions should be sufficiently low that they do not significantly pass through the hard mask. Also, because the energy of the ions is low, they do not have the same impact on the temperature of the sample as high energy ions.
  • Figure 1 is an SEM image of a Si0 2 ridge etched using the inventive process
  • Figure 2 shows the effect of DC bias on selectivity and etch rate
  • Figure 3 is a table showing the results obtained for various samples under different conditions.
  • SiO 2 sample in this example, silicon rich silicon glass (SRSG) was placed in a vacuum chamber.
  • An aluminum hard mask was formed on the Si0 2 sample in a manner known per se.
  • Other materials such as SiChrome or even photoresist can be employed.
  • the preferred material is aluminum since this has been found to give the best selectivity.
  • the sample was subjected to a high rate deep plasma etch using C F 8 as the etchant in Argon.
  • the C 4 F 8 generates a large amount of etching radicals, which contribute to the high etch rate.
  • An inductively coupled plasma (ICP) source was used to generate the plasma. This permitted a low energy ion bombardment to be employed to perform the vertical etching.
  • Figure 1 shows an example of a SiO 2 sample that has been etched in accordance with described process. It will be noted how straight and smooth the sidewalls appear at 4,500 magnification.
  • the precise parameters depend on the actual experimental conditions and can be determined by routine experiment.
  • the inventors have found that as the ICP power increases from 1500 watts to 2000 watts, the etch rate increases by about 30%. However, the selectivity drops by more than 50%. As the pressure increases from 5 mtorr 10 mtorr, the etch rate decreases by 40% and the selectivity increases by 70%.
  • the selectivity is defined as the ratio of the etch rate into the SiO2/ etch rate into the mask.
  • the etch rate slightly increases.
  • the etching results are not significantly modified.
  • Preferred conditions are an ICP power of 1500 watts, an RF power of 235 watts, a DC bias of 200 volts, a pressure of 8 mTorr, a C F 8 flow rate of 25 seem, an argon flow rate of 25 seem, and a temperature of about 70°C.
  • the temperature can be varied to control the verticality of the sidewalls.
  • the inventors are able to achieve good selectivity because the low energy ions do not significantly penetrate the mask, especially if a hard mask is employed.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

L'invention concerne un procédé permettant de graver un diélectrique, tel que SiO2, pour produire des parois verticales. Ce procédé est effectué à une vitesse de gravure élevée, à l'aide d'un bombardement ionique de faible énergie et mettant en oeuvre C4F8 en tant que gaz de gravure principal. Les profils des parois de SiO2 sont maîtrisés par variation de la température de l'échantillon.
PCT/CA2002/000784 2001-05-28 2002-05-28 Procede de gravure seche verticale et profonde de dielectriques WO2002097874A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CA2,349,032 2001-05-28
CA 2349032 CA2349032A1 (fr) 2001-05-28 2001-05-28 Methode de gravure a sec de sio2 verticale et en profondeur

Publications (1)

Publication Number Publication Date
WO2002097874A1 true WO2002097874A1 (fr) 2002-12-05

Family

ID=4169126

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CA2002/000784 WO2002097874A1 (fr) 2001-05-28 2002-05-28 Procede de gravure seche verticale et profonde de dielectriques

Country Status (2)

Country Link
CA (1) CA2349032A1 (fr)
WO (1) WO2002097874A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150034592A1 (en) * 2013-07-30 2015-02-05 Corporation For National Research Initiatives Method for etching deep, high-aspect ratio features into glass, fused silica, and quartz materials

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5468342A (en) * 1994-04-28 1995-11-21 Cypress Semiconductor Corp. Method of etching an oxide layer
US5711851A (en) * 1996-07-12 1998-01-27 Micron Technology, Inc. Process for improving the performance of a temperature-sensitive etch process
US5814563A (en) * 1996-04-29 1998-09-29 Applied Materials, Inc. Method for etching dielectric using fluorohydrocarbon gas, NH3 -generating gas, and carbon-oxygen gas

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5468342A (en) * 1994-04-28 1995-11-21 Cypress Semiconductor Corp. Method of etching an oxide layer
US5814563A (en) * 1996-04-29 1998-09-29 Applied Materials, Inc. Method for etching dielectric using fluorohydrocarbon gas, NH3 -generating gas, and carbon-oxygen gas
US5711851A (en) * 1996-07-12 1998-01-27 Micron Technology, Inc. Process for improving the performance of a temperature-sensitive etch process

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150034592A1 (en) * 2013-07-30 2015-02-05 Corporation For National Research Initiatives Method for etching deep, high-aspect ratio features into glass, fused silica, and quartz materials
US9576773B2 (en) * 2013-07-30 2017-02-21 Corporation For National Research Initiatives Method for etching deep, high-aspect ratio features into glass, fused silica, and quartz materials

Also Published As

Publication number Publication date
CA2349032A1 (fr) 2002-11-28

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