WO2002073693A1 - Dispositif à semi-conducteurs - Google Patents
Dispositif à semi-conducteurs Download PDFInfo
- Publication number
- WO2002073693A1 WO2002073693A1 PCT/JP2002/002039 JP0202039W WO02073693A1 WO 2002073693 A1 WO2002073693 A1 WO 2002073693A1 JP 0202039 W JP0202039 W JP 0202039W WO 02073693 A1 WO02073693 A1 WO 02073693A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor device
- chamber
- working
- working medium
- chip
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 85
- 239000000758 substrate Substances 0.000 claims description 25
- 238000005461 lubrication Methods 0.000 abstract 2
- 238000007599 discharging Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 abstract 1
- 230000001050 lubricating effect Effects 0.000 abstract 1
- 239000000203 mixture Substances 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 7
- 230000001965 increasing effect Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229920003002 synthetic resin Polymers 0.000 description 2
- 239000000057 synthetic resin Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
- H01L2225/06586—Housing with external bump or bump-like connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Definitions
- the present invention relates to a semiconductor device provided with a package that enables high-density mounting.
- small-sized electronic devices that are called portable electronic devices and are portable have been widely used.
- the equipment itself is small, and the space for mounting electronic components inside the equipment is limited.
- This type of electronic equipment is required to have high functionality while being downsized.
- a large number of semiconductor chips, functional elements such as passive elements, etc. are required, and these functional parts are mounted on a mother board with a limited mounting space in the equipment body. It is necessary to mount to the density.
- CSP chip size package
- BGA ball grid array
- the semiconductor device 100 shown in FIG. 1 is in the form of a chip size package (CSP), and has a semiconductor chip 101 because the package size is as close as possible to the semiconductor chip 101.
- the dimension in the height direction is suppressed by flip-chip connection between the substrate and the intermediate substrate (ink-poser) 102.
- the flip-chip connection of the semiconductor device 100 shown in FIG. This is a mounting method in which the electrode 104 on the second side and the bump 103 are aligned and connected by so-called face-down bonding.
- semiconductor chips 101 and The space between the housing and the poser 102 is sealed with a synthetic resin 105.
- the semiconductor device 100 is packaged on the motherboard 107 via the bumps 106 at a high density by adopting a package form as shown in FIG.
- a semiconductor device is integrated by connecting a semiconductor chip and an in-poser by flip-chip connection, and these are mounted as one functional component on the motherboard separately from chip components such as passive elements. are doing.
- Some semiconductor devices have a semiconductor chip and a passive element integrated on an intermediate substrate, but the size itself is not the same size as the package size of a CSP or the like. In particular, the increase in the size in the height direction makes it difficult to fit the above-mentioned small electronic devices in the restricted mounting space.
- Another object of the present invention is to provide a semiconductor device capable of further downsizing and higher density without increasing the cost.
- a chip component is provided on a surface of an intermediate substrate mounted on a pace substrate via bumps, the surface facing the base substrate.
- a semiconductor device by effectively utilizing a space formed between an intermediate substrate and a base substrate by a bump, chip components can be prevented from increasing in the height direction while suppressing an increase in height. Can be mounted on the surface facing the base substrate of Further miniaturization and higher density of the device are realized.
- FIG. 1 is a cross-sectional view showing a conventional semiconductor device.
- FIG. 2 is a cross-sectional view showing a semiconductor device according to the present invention.
- FIG. 3 is a plan view of the semiconductor device shown in FIG. 2 as viewed from the side facing the motherboard.
- FIG. 4 is a sectional view showing another example of the semiconductor device according to the present invention.
- FIG. 5 is a plan view of the semiconductor device shown in FIG. 4 as viewed from the side facing the motherboard.
- the semiconductor device 1 has a package form that enables high-density mounting on a mother board 20.
- the semiconductor device 1 includes an interposer 2 as an intermediate substrate.
- the INZUI POSER 2 itself functions as one functional component.
- the in-plane poser 2 is made of a dielectric material, and the organic substrates 3a, 3b, and 3c are bonded together via a prepreg (not shown).
- a surface 2a facing the mother board 20 which is the main surface on the outer layer side of a, both main surfaces of the organic substrate 3b, and a mother board 20 which is a main surface on the outer layer side of the organic substrate 3c It has a four-layer built-up structure in which a metal wiring layer is formed on a surface 2b opposite to the surface 2a to be formed.
- the metal wiring layer is, for example, a resonator 4 or a capacitor 5,
- the functional elements such as the spacer 6 and the wiring pattern 7 and the ground pattern 8 connecting them are formed as a thin film. Each functional element is electrically connected to a wiring pattern 7 ⁇ ground pattern 8 connecting them and via holes 9 and through holes 10 formed through the organic substrates 3 a, 3 b, and 3 c. ing.
- the semiconductor chip 11 is mounted on the inner poser 2 by flip-chip connection on a surface 2 b opposite to the surface facing the mother board 20.
- flip-chip connection is a method in which a bump electrode called a bump is formed on a chip-side electrode, and the board-side electrode and the bump are turned upside down to be connected by so-called face-down bonding. Is the way.
- the bumps 12 are formed on the semiconductor chip 11, are aligned with the electrodes 13 of the interposer 2, and are heated and melted to perform face-down bonding. According to this flip-chip connection, for example, a wiring space for wires is not required as compared with wire bonding, and the dimension in the height direction can be significantly reduced.
- a chip component 14 such as a passive element is mounted on the interposer 2 on the surface 2 b opposite to the surface facing the motherboard 20.
- the semiconductor chip 15 is mounted on the inner poser 2 by flip-chip connection on a surface 2 a facing the motherboard 20.
- the semiconductor chip 15 is used by thinning it to a thickness of, for example, about 50 to 100 / m by polishing or the like, and a bump 16 is formed on the semiconductor chip 15. Face-down bonding is performed by aligning with the electrode 17 of the interposer 2 and melting by heating. As a result, the height dimension can be significantly reduced.
- the space between the semiconductor chip 15 and the interposer 2 is sealed with a resin 18.
- a plurality of solder bumps 1 are located on the surface 2 a facing the mother board 20 so as to surround the semiconductor chip 15 described above. 9 are arranged.
- the bump 19 is for mounting the semiconductor device 1 on the mother port 20 and is formed so that the thickness of the bump 19 is larger than the thickness of the semiconductor chip 15 described above. .
- the thickness of the bump 19 is about 200 to 250.
- the semiconductor device 1 becomes a mother board 20 When mounted on the surface, it is possible to prevent the semiconductor chip 15 provided on the surface 2 a of the in-poser 2 facing the mother board 20 from contacting the mother board 20. .
- the thickness of the bump 19 larger than the thickness of the semiconductor chip 19, it is possible to arrange the semiconductor chip 15 between the inner poser 2 and the mother board 20. A sufficient space 21 can be formed.
- the semiconductor device 1 configured as described above is mounted as one functional component on the motherboard 20 via the bump 19.
- the overall thickness of the semiconductor device 1 mounted on the mother board 20 is about 1.2 mm.
- the semiconductor chip 15 is provided on the surface 2a of the in-poser 2 which is mounted via the bumps 19 and faces the mother board 20 ( see FIG. 1 ).
- the semiconductor chip 15 can be mounted on the surface 2 a of the ink poser 2 facing the motherboard 20.
- the semiconductor device 1 according to the present invention having the above-described configuration can be further reduced in size and density without increasing the cost, and can be accommodated in a restricted mounting space of a small electronic device. Becomes possible.
- a passive element such as a chip component is provided on both sides 2 a and 2 b of the interposer 2, separately from a passive element including a metal wiring layer formed on an inner layer or an outer layer of the interposer 2. Since the metal wiring layer can be provided, the load on the metal wiring layer formed in the ink poser 2 can be greatly reduced.
- FIG. 4 is a cross-sectional view of the semiconductor device 30.
- FIG. 5 is a plan view of the semiconductor device 30 as viewed from a surface facing the mother board 20.
- semiconductor chips 22 and 23 are mounted by flip-chip connection on a surface 2a of motherboard 20 facing the motherboard 20 of the ink poser 2.
- the semiconductor chips 22 and 23 are, for example, 50% by polishing or the like.
- the bumps 24 and 25 are formed on these semiconductor chips 22 and 23, and these are aligned with the electrodes 26 and 27 of the interposer 2.
- the face down bonding is performed by heating and melting. As a result, the height dimension can be significantly reduced.
- the space between the semiconductor chips 22:23 and the ink poser 2 is sealed with synthetic resins 28,29.
- a plurality of solder bumps 19 are arranged on the interposer 2 so as to surround the semiconductor chips 22 and 23 on the surface 2 a facing the motherboard 20. It is established.
- the bump 19 is for mounting the semiconductor device 30 on the motherboard 20, and the thickness of the bump 19 is larger than the thickness of the semiconductor chips 22 and 23 described above. Is formed.
- the thickness of the bump 19 is about 200 to 250 m.
- the semiconductor device 30 configured as described above is mounted as one functional component on the motherboard 20 via the bumps 19.
- the overall thickness of the semiconductor device 3 ⁇ mounted on the mother board 20 is about 1.2 mm.
- the semiconductor chips 22 and 23 are provided on the surface 2 a of the in-poser 2 that is mounted via the bumps 19 and faces the mother board 20. ing. In this case, by effectively utilizing the space 21 formed between the inner poser 2 and the mother board 20 by the pump 19, the increase in the dimension of the semiconductor device 30 in the height direction can be reduced. While suppressing, the semiconductor chips 22 and 23 can be mounted on the surface 2a facing the mother board 20 of the input port 2.
- the semiconductor device 30 as in the case of the semiconductor device 1 described above, further miniaturization and higher density can be achieved without increasing the cost, and the mounting space where the small electronic device is restricted is limited. It is possible to fit in.
- the semiconductor device 30 is formed in an inner layer or an outer layer of the interposer 2.
- the passive elements made of metal wiring layers it is possible to provide passive elements made of chip components on both sides 2a and 2b of the interposer 2.
- the load on the metal wiring layer can be greatly reduced.
- the organic substrate 3 a, 3 b, 3 b It is not limited to the combination, and may be, for example, a silicon substrate.
- chip parts such as passive elements should be mounted on the surface 2 a of the inner poser 2 facing the mother board 20. Is also possible.
- the semiconductor device according to the present invention has an increased cost because chip components are provided on a surface of an intermediate substrate, which is mounted on a single substrate via bumps, on a surface facing the base substrate. It is possible to further reduce the size and increase the density without inducing. Therefore, it is possible to fit in the limited mounting space of a small electronic device.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Combinations Of Printed Boards (AREA)
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02702745A EP1309004A1 (en) | 2001-03-09 | 2002-03-05 | Semiconductor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001067456A JP2002270762A (ja) | 2001-03-09 | 2001-03-09 | 半導体装置 |
JP2001-67456 | 2001-03-09 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2002073693A1 true WO2002073693A1 (fr) | 2002-09-19 |
Family
ID=18925804
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2002/002039 WO2002073693A1 (fr) | 2001-03-09 | 2002-03-05 | Dispositif à semi-conducteurs |
Country Status (4)
Country | Link |
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US (1) | US20030164538A1 (ja) |
EP (1) | EP1309004A1 (ja) |
JP (1) | JP2002270762A (ja) |
WO (1) | WO2002073693A1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006114928A1 (ja) * | 2005-04-18 | 2006-11-02 | Murata Manufacturing Co., Ltd. | 高周波モジュール |
KR100632587B1 (ko) * | 2005-07-01 | 2006-10-09 | 삼성전기주식회사 | 주기판 및 보조기판으로 모듈부품이 분리 내장된패키지내장시스템 |
RU2663688C1 (ru) | 2014-09-26 | 2018-08-08 | Интел Корпорейшн | Корпусированная интегральная схема, содержащая соединенный проволочными перемычками многокристальный пакет |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11154728A (ja) * | 1997-09-16 | 1999-06-08 | Matsushita Electric Ind Co Ltd | 半導体装置およびその実装体 |
GB2337852A (en) * | 1998-05-26 | 1999-12-01 | Nec Corp | Multichip module |
JP2000340736A (ja) * | 1999-05-26 | 2000-12-08 | Sony Corp | 半導体装置及びその実装構造、並びにこれらの製造方法 |
JP2001223297A (ja) * | 1999-11-30 | 2001-08-17 | Fujitsu Ltd | 半導体装置及び半導体装置の製造方法及び半導体装置の積層方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5200362A (en) * | 1989-09-06 | 1993-04-06 | Motorola, Inc. | Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film |
US5438224A (en) * | 1992-04-23 | 1995-08-01 | Motorola, Inc. | Integrated circuit package having a face-to-face IC chip arrangement |
US5616958A (en) * | 1995-01-25 | 1997-04-01 | International Business Machines Corporation | Electronic package |
GB9502178D0 (en) * | 1995-02-03 | 1995-03-22 | Plessey Semiconductors Ltd | MCM-D Assemblies |
US6667560B2 (en) * | 1996-05-29 | 2003-12-23 | Texas Instruments Incorporated | Board on chip ball grid array |
US6137164A (en) * | 1998-03-16 | 2000-10-24 | Texas Instruments Incorporated | Thin stacked integrated circuit device |
US5854507A (en) * | 1998-07-21 | 1998-12-29 | Hewlett-Packard Company | Multiple chip assembly |
US6437990B1 (en) * | 2000-03-20 | 2002-08-20 | Agere Systems Guardian Corp. | Multi-chip ball grid array IC packages |
JP2001339043A (ja) * | 2000-05-30 | 2001-12-07 | Mitsubishi Electric Corp | 半導体装置及びそれを用いた半導体モジュール |
US6525413B1 (en) * | 2000-07-12 | 2003-02-25 | Micron Technology, Inc. | Die to die connection method and assemblies and packages including dice so connected |
-
2001
- 2001-03-09 JP JP2001067456A patent/JP2002270762A/ja not_active Withdrawn
-
2002
- 2002-03-05 EP EP02702745A patent/EP1309004A1/en not_active Withdrawn
- 2002-03-05 WO PCT/JP2002/002039 patent/WO2002073693A1/ja not_active Application Discontinuation
- 2002-03-05 US US10/275,792 patent/US20030164538A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11154728A (ja) * | 1997-09-16 | 1999-06-08 | Matsushita Electric Ind Co Ltd | 半導体装置およびその実装体 |
GB2337852A (en) * | 1998-05-26 | 1999-12-01 | Nec Corp | Multichip module |
JP2000340736A (ja) * | 1999-05-26 | 2000-12-08 | Sony Corp | 半導体装置及びその実装構造、並びにこれらの製造方法 |
JP2001223297A (ja) * | 1999-11-30 | 2001-08-17 | Fujitsu Ltd | 半導体装置及び半導体装置の製造方法及び半導体装置の積層方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2002270762A (ja) | 2002-09-20 |
US20030164538A1 (en) | 2003-09-04 |
EP1309004A1 (en) | 2003-05-07 |
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