WO2002061841A3 - Partially silicide diode and method of manufacture - Google Patents

Partially silicide diode and method of manufacture Download PDF

Info

Publication number
WO2002061841A3
WO2002061841A3 PCT/US2001/047113 US0147113W WO02061841A3 WO 2002061841 A3 WO2002061841 A3 WO 2002061841A3 US 0147113 W US0147113 W US 0147113W WO 02061841 A3 WO02061841 A3 WO 02061841A3
Authority
WO
WIPO (PCT)
Prior art keywords
anode
cathode
manufacture
diode
partially
Prior art date
Application number
PCT/US2001/047113
Other languages
French (fr)
Other versions
WO2002061841A2 (en
Inventor
Stephen G Beebe
Dong-Hyuk Ju
William G En
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to AU2002225999A priority Critical patent/AU2002225999A1/en
Publication of WO2002061841A2 publication Critical patent/WO2002061841A2/en
Publication of WO2002061841A3 publication Critical patent/WO2002061841A3/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A silicon-on-insulator (SOI) diode (10) has an active region (18) having an anode (20) disposed adjacent a cathode (22); a first silicide layer (24) formed on the anode (20) distal a junction between the anode (20) and the cathode (22) and a second silicide layer (24) formed on the cathode (22) distal the the junction between the anode (20) and the cathode (22); and an oxide layer (26) isolating the first and second silicide layers (24). Also disclosed is a method of fabricating the SOI diode (10).
PCT/US2001/047113 2001-01-31 2001-12-03 Partially silicide diode and method of manufacture WO2002061841A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002225999A AU2002225999A1 (en) 2001-01-31 2001-12-03 Partially silicide diode and method of manufacture

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US77473201A 2001-01-31 2001-01-31
US09/774,732 2001-01-31

Publications (2)

Publication Number Publication Date
WO2002061841A2 WO2002061841A2 (en) 2002-08-08
WO2002061841A3 true WO2002061841A3 (en) 2003-01-23

Family

ID=25102103

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/047113 WO2002061841A2 (en) 2001-01-31 2001-12-03 Partially silicide diode and method of manufacture

Country Status (2)

Country Link
AU (1) AU2002225999A1 (en)
WO (1) WO2002061841A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10314505B4 (en) 2003-03-31 2009-05-07 Advanced Micro Devices, Inc., Sunnyvale Improved diode structure for Soi circuits
US7227233B2 (en) 2005-09-12 2007-06-05 International Business Machines Corporation Silicon-on-insulator (SOI) Read Only Memory (ROM) array and method of making a SOI ROM
US9368648B2 (en) 2009-04-02 2016-06-14 Qualcomm Incorporated Active diode having no gate and no shallow trench isolation

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0387944A1 (en) * 1989-03-13 1990-09-19 Koninklijke Philips Electronics N.V. Semiconductor device provided with a protection circuit
US5629544A (en) * 1995-04-25 1997-05-13 International Business Machines Corporation Semiconductor diode with silicide films and trench isolation
EP0923132A1 (en) * 1997-10-09 1999-06-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0387944A1 (en) * 1989-03-13 1990-09-19 Koninklijke Philips Electronics N.V. Semiconductor device provided with a protection circuit
US5629544A (en) * 1995-04-25 1997-05-13 International Business Machines Corporation Semiconductor diode with silicide films and trench isolation
EP0923132A1 (en) * 1997-10-09 1999-06-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor device

Also Published As

Publication number Publication date
WO2002061841A2 (en) 2002-08-08
AU2002225999A1 (en) 2002-08-12

Similar Documents

Publication Publication Date Title
EP1211727A3 (en) Semiconductor device having shallow trench isolation structure and manufacturing method thereof
EP1213757A3 (en) Integrated circuits having and adjacent p-type doped regions having shallow trench isolation structures without liner layers therein therebetween and methods of forming same
WO2003044833A3 (en) Method for limiting divot formation in post shallow trench isolation processes
EP1235279A3 (en) Semiconductor device using nitride compound and method for fabricating the same
WO2006135505A3 (en) Capacitorless dram over localized soi
AU2002359741A1 (en) Oxide layer on a gaas-based semiconductor structure and method of forming the same
EP0715350A3 (en) Method of forming a shallow trench, for isolating adjacent deep trenches, using a silicidation step
SG106655A1 (en) Thermistor and method of manufacture
EP0926725A3 (en) Defect induced buried oxide (dibox) for throughput SOI
EP1263062A3 (en) Organic semiconductor device and process of manufacturing the same
EP1037284A3 (en) Heterojunction bipolar transistor and method for fabricating the same
EP1209738A3 (en) Method for fabricating an air gap shallow trench isolation (STI) structure
AU4524701A (en) Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on weak posts, and gallium nitride semiconductor structures fabricated thereby
WO2005050716A3 (en) High-temperature devices on insulator substrates
AU2001280492A1 (en) Schottky diode having increased active surface area and method of fabrication
EP1388902A3 (en) Fabricating method of Gunn diode
TW327700B (en) The method for using rough oxide mask to form isolating field oxide
EP1043819A3 (en) Structure and method for asymmetric waveguide nitride laser diode
WO2002003474A3 (en) N-type nitride semiconductor laminate and semiconductor device using same
EP1246258A4 (en) Semiconductor device, method of manufacture thereof, and information processing device
WO2001099198A3 (en) Power mosfet and method of making the same
EP1777739A3 (en) Semiconductor device and fabrication method therefor
WO2002061801A3 (en) Dual gate process using self-assembled molecular layer
TW351849B (en) Method for fabricating shadow trench insulation structure
AU2001218182A1 (en) Methods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride posts, and gallium nitride semiconductor structures fabricated thereby

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PH PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PH PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP