WO2002061841A2 - Partially silicide diode and method of manufacture - Google Patents

Partially silicide diode and method of manufacture Download PDF

Info

Publication number
WO2002061841A2
WO2002061841A2 PCT/US2001/047113 US0147113W WO02061841A2 WO 2002061841 A2 WO2002061841 A2 WO 2002061841A2 US 0147113 W US0147113 W US 0147113W WO 02061841 A2 WO02061841 A2 WO 02061841A2
Authority
WO
WIPO (PCT)
Prior art keywords
diode
anode
cathode
soi
silicide
Prior art date
Application number
PCT/US2001/047113
Other languages
French (fr)
Other versions
WO2002061841A3 (en
Inventor
Stephen G. Beebe
Dong-Hyuk Ju
William G. En
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Priority to AU2002225999A priority Critical patent/AU2002225999A1/en
Publication of WO2002061841A2 publication Critical patent/WO2002061841A2/en
Publication of WO2002061841A3 publication Critical patent/WO2002061841A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements

Definitions

  • the present invention generally relates to the manufacture of semiconductor devices, and, more specifically, relates the manufacture of a silicon-on-insulator (SOI) diode having a salicide blocked region, the diode being particularly well suited for use as an electrostatic discharge (ESD) protection device.
  • SOI silicon-on-insulator
  • ESD electrostatic discharge
  • SOI diodes are typically manufactured by using a polysilicon layer, or poly layer, to define an unsilicided region.
  • a polysilicon layer or poly layer
  • the foregoing poly-defined diode exhibits a relatively high resistance (e.g., 500 ohm- ⁇ m to 2,000 ohm- ⁇ m) which adversely affects diode performance, especially when used as an electrostatic discharge (ESD) protection device.
  • the high resistance is a result of low doping in the active region, especially in the areas directly below the gate oxide and poly layers as these layers tend to impede dopant penetration into the active region.
  • a gate oxide layer, disposed on the active region is susceptible to voltage overstress and may become damaged during diode operation.
  • the invention is a silicon-on-insulator (SOI) diode.
  • SOI diode has an active region having an anode disposed adjacent a cathode; a first suicide layer formed on the anode distal a junction between the anode and the cathode and a second suicide layer formed on the cathode distal the junction between the anode and the cathode; and an insulating layer isolating the first and second suicide layers.
  • the invention is a silicon-on-insulator (SOI) diode.
  • SOI diode has an active region having an anode and a cathode; a first suicide layer formed on the anode distal a junction between the anode and the cathode and a second suicide layer formed on the cathode distal the junction between the anode and the cathode; and a resistor-protect mask formed on a central region of the active layer and defining the placement of the suicide layer.
  • the invention is a method of fabricating a silicon-on- insulator (SOI) diode.
  • the method includes the steps of (a) defining an active region on an SOI wafer; (b) implanting a first portion of the active region with dopant to form an anode and implanting a second portion of the active region with dopant to form a cathode; (c) depositing a resistor-protect mask on a central region of the active region, the resistor-protect mask defining silicide regions; and (d) forming a suicide layer in the suicide regions defined by the resistor-protect mask.
  • SOI silicon-on- insulator
  • FIG. 1 is a cross-section of a salicide blocked diode arranged as an electrostatic discharge (ESD) protection device
  • FIG. 2 is a flow diagram of a method of manufacturing the salicide blocked diode
  • FIG. 3a is a cross-section of the salicide blocked diode in a first intermediate stage of manufacture
  • FIG. 3b is a cross-section of the salicide blocked diode in a second intermediate stage of manufacture
  • FIG. 3c is a cross-section of the salicide blocked diode in a third intermediate stage of manufacture
  • FIG. 3d is a cross-section of the salicide blocked diode in a fourth intermediate stage of manufacture
  • FIG. 3e is a cross-section of the salicide blocked diode in a fifth intermediate stage of manufacture; and FIG. 3f is a cross-section of the salicide blocked diode in a last stage of manufacture.
  • a salicide blocked diode 10 is illustrated.
  • the diode 10 is formed on a silicon-on- insulator (SOI) integrated circuit having a silicon substrate 12, a buried oxide (BOX) layer 14 formed on the substrate 12 and a silicon layer (also referred to as an active layer) disposed on the buried oxide layer 14.
  • SOI silicon-on- insulator
  • BOX buried oxide
  • active layer silicon layer
  • shallow trench isolation (STI) regions 16 define the placement of silicon active regions, one of the active regions being used for the diode 10 and is referred to as active region 18.
  • the active region 18 has a P+ region, or anode 20, and an N+ region, or cathode 22.
  • a suicide layer 24 (also known in the art as a salicide structure) is formed on the anode region 20 distal to the P+ region and N+ region interface, or P-N junction.
  • Another suicide layer 24 is deposited on the cathode region 22 distal to the P-N junction. As is known in the art, the suicide layers 24 establish conduction to the anode region 20 and the cathode region 22.
  • One or more insulating layers, such as oxide layer 26, are formed to isolate the active areas of the diode 10. Contacts 28 and metal layers 30 are formed in the oxide 26 to respectively establish electrical connection to the anode 20 and the cathode 22 through the suicide layers 24.
  • the diode 10 can be used for a variety of purposes, including use as an electrostatic discharge (ESD) protection device.
  • the cathode 22 can be coupled via the silicide layer 24 and respective contact 28 and metal layer 30 to an I/O pad, or other node, to be protected.
  • the anode 20 is connected to ground, or Vss, via the anode's respective silicide layer 24, contact 28 and metal layer 30.
  • the anode 20 is coupled to the I/O pad and the cathode 22 is coupled to a supply voltage, or Vdd
  • the P+ region and N+ region are heavily doped (e.g., about 10 18 atoms/cm 2 to about 10 22 atoms/cm 2 ) to give the diode 10 a relatively low resistance (e.g., about 100 ohm- ⁇ m to about 300 ohm- ⁇ m) which forward biases at a relatively low bias voltage (e.g., about 0.3 volts to about 0.6 volt) and breaks down at a relatively low reverse break down voltage (e.g., about 3 volts to about 4 volts), thereby exhibiting traits important for good ESD protection.
  • a relatively low bias voltage e.g., about 0.3 volts to about 0.6 volt
  • a relatively low reverse break down voltage e.g., about 3 volts to about 4 volts
  • a method 40 is illustrated in flowchart format for manufacturing the diode 10 illustrated in FIG. 1.
  • the method 40 starts in step 42 in which an SOI wafer is manufactured.
  • the SOI wafer, or SOI material has the silicon substrate 12 having the buried oxide layer 14 disposed thereon.
  • a silicon layer 44 (or active layer) is disposed on the buried oxide layer 14 in conventional format.
  • the SOI arrangement illustrated in FIG. 3a is manufactured using conventional techniques.
  • the active region 18 is defined in the silicon layer 44 by fabricating shallow trench isolation (STI) regions 16 using conventional techniques.
  • STI shallow trench isolation
  • the P+ region, or anode 20, is formed in the active region in step 48 and as further illustrated by FIG. 3c. More specifically, the P+ region is defined by depositing a P+ mask 50 over areas where exposure to P+ implantation should be minimized, such as the future N+ region of the active region 18 and adjacent STI 16. Next, the device is doped using standard PMOS source/drain implants, such as on the order of about 10 18 atoms/cm 2 to about 10 20 atoms/cm 2 , thereby forming the anode 20. Subsequently, the P+ mask is stripped from the device in step 52. The P+ implantation step may be used to simultaneously dope other areas of the wafer in the fabrication of other devices.
  • the N+ region, or cathode 22 is formed in the active region 18 in step 54 and as further illustrated by FIG. 3d. More specifically, the N+ region is defined by depositing an N+ mask 56 over the P+ region, or anode 20, and adjacent STI 16. Next, the device is doped using standard NMOS source/drain implants, such as on the order of about 10 18 atoms/cm 2 to about 10 20 atoms/cm 2 , thereby forming the cathode 22. The N+ implantation step may be used to simultaneously dope other areas of the wafer in the fabrication of other devices.
  • openings in the N+ and P+ masks should overlap with each other by at least the tolerance, or error margin in placement, of the mask to ensure that there is no undoped region in the area of a P-
  • the N+ and P+ regions are implanted using standard NMOS and PMOS source/drain implants, respectively. Other implants, such as extension and halo implants, may or may not be blocked as is desired for the anticipated function of the diode 10 being manufactured.
  • the N+ mask is stripped from the device in step 60.
  • the active region 18 can be doped with N+ implants prior to being doped with
  • the regions for silicidation are defined by depositing a resistor-protect (RSPT) mask 62 in step 64 and as illustrated in FIG. 3e. It is noted that salicidation is taken herein to have the same meaning as silicidation.
  • the RSPT mask 62 is placed in all regions where silicide is not desired. More specifically, the RSPT mask 62 is placed over the P-N junction 58 and extends over the P+ region and the N+ region to block the deposition of silicide over the desired active portions of the N+/P+ function.
  • the area masked by the RSPT mask 62 is selected to result in a desired resistance of the diode 10 since, as the size of the silicide layers 24 increases, the resistance of the diode decreases. It should be appreciated that the RSPT mask 62 is used to block the silicide layers 24 from the central junction region of the active region 18, but the silicide layers 24 is allowed to form on the distal areas of the anode 20 and cathode 22, respectfully, to provide conduction to other devices as described in greater detail above. RSPT mask 62 is also deposited over the STI regions 16 to prevent silicide formation on the STI regions 16.
  • the RSPT mask 62 typically an oxide, is conventionally used to define resistors formed on the wafer and is therefore typically a part of existing steps in most overall wafer fabrication processes. Accordingly, the RSPT mask 62 used for the salicide blocking function is deposited using the conventional techniques used when defining resistor elements.
  • the silicide layers 24 are formed in step 66 using conventional techniques. More specifically, silicide is formed depositing metal in at least the unmasked areas and reacting the metal with the exposed silicon areas of the anode 20 and cathode 22. Preferably, a TiSi 2
  • RSPT mask 62 is stripped in step 68 using conventional techniques.
  • the oxide material 26, the contacts 28 and the metal layers 30 are formed using conventional techniques in order to protect the diode 10, isolate the two silicide layers 24 and couple the diode
  • step 70 The formation of the oxide material 26, the metal layers 30 and the contacts 28 are completed in step 70 and shown in an exemplary formation in FIG. 3f.

Abstract

A silicon-on-insulator (SOI) diode (10) has an active region (18) having an anode (20) disposed adjacent a cathode (22); a first silicide layer (24) formed on the anode (20) distal a junction between the anode (20) and the cathode (22) and a second silicide layer (24) formed on the cathode (22) distal the the junction between the anode (20) and the cathode (22); and an oxide layer (26) isolating the first and second silicide layers (24). Also disclosed is a method of fabricating the SOI diode (10).

Description

SALICIDE BLOCKED DIODE AND METHOD OF MANUFACTURE
TECHNICAL FIELD
The present invention generally relates to the manufacture of semiconductor devices, and, more specifically, relates the manufacture of a silicon-on-insulator (SOI) diode having a salicide blocked region, the diode being particularly well suited for use as an electrostatic discharge (ESD) protection device.
BACKGROUND ART
Traditional silicon-on-insulator (SOI) diodes are typically manufactured by using a polysilicon layer, or poly layer, to define an unsilicided region. There are, however, several shortcomings associated with such a conventional diode. The foregoing poly-defined diode exhibits a relatively high resistance (e.g., 500 ohm-μm to 2,000 ohm-μm) which adversely affects diode performance, especially when used as an electrostatic discharge (ESD) protection device. The high resistance is a result of low doping in the active region, especially in the areas directly below the gate oxide and poly layers as these layers tend to impede dopant penetration into the active region. In addition, a gate oxide layer, disposed on the active region, is susceptible to voltage overstress and may become damaged during diode operation.
DISCLOSURE OF THE INVENTION
According to one aspect of the invention, the invention is a silicon-on-insulator (SOI) diode. The SOI diode has an active region having an anode disposed adjacent a cathode; a first suicide layer formed on the anode distal a junction between the anode and the cathode and a second suicide layer formed on the cathode distal the junction between the anode and the cathode; and an insulating layer isolating the first and second suicide layers.
According to another aspect of the invention, the invention is a silicon-on-insulator (SOI) diode. The SOI diode has an active region having an anode and a cathode; a first suicide layer formed on the anode distal a junction between the anode and the cathode and a second suicide layer formed on the cathode distal the junction between the anode and the cathode; and a resistor-protect mask formed on a central region of the active layer and defining the placement of the suicide layer.
According to yet another aspect of the invention, the invention is a method of fabricating a silicon-on- insulator (SOI) diode. The method includes the steps of (a) defining an active region on an SOI wafer; (b) implanting a first portion of the active region with dopant to form an anode and implanting a second portion of the active region with dopant to form a cathode; (c) depositing a resistor-protect mask on a central region of the active region, the resistor-protect mask defining silicide regions; and (d) forming a suicide layer in the suicide regions defined by the resistor-protect mask. BRIEF DESCRIPTION OF DRAWINGS
These and further features of the present invention will be apparent with reference to the following description and drawings, wherein:
FIG. 1 is a cross-section of a salicide blocked diode arranged as an electrostatic discharge (ESD) protection device; FIG. 2 is a flow diagram of a method of manufacturing the salicide blocked diode; FIG. 3a is a cross-section of the salicide blocked diode in a first intermediate stage of manufacture; FIG. 3b is a cross-section of the salicide blocked diode in a second intermediate stage of manufacture; FIG. 3c is a cross-section of the salicide blocked diode in a third intermediate stage of manufacture; FIG. 3d is a cross-section of the salicide blocked diode in a fourth intermediate stage of manufacture;
FIG. 3e is a cross-section of the salicide blocked diode in a fifth intermediate stage of manufacture; and FIG. 3f is a cross-section of the salicide blocked diode in a last stage of manufacture.
MODES FOR CARRYING OUT THE INVENTION In the detailed description which follows, identical components have been given the same reference numerals, regardless of whether they are shown in different embodiments of the present invention. To illustrate the present invention in a clear and concise manner, the drawings may not necessarily be to scale and certain features may be shown in somewhat schematic form.
Referring to FIG. 1, a salicide blocked diode 10 is illustrated. The diode 10 is formed on a silicon-on- insulator (SOI) integrated circuit having a silicon substrate 12, a buried oxide (BOX) layer 14 formed on the substrate 12 and a silicon layer (also referred to as an active layer) disposed on the buried oxide layer 14. Within the silicon layer, shallow trench isolation (STI) regions 16 define the placement of silicon active regions, one of the active regions being used for the diode 10 and is referred to as active region 18. The active region 18 has a P+ region, or anode 20, and an N+ region, or cathode 22. A suicide layer 24 (also known in the art as a salicide structure) is formed on the anode region 20 distal to the P+ region and N+ region interface, or P-N junction.
Another suicide layer 24 is deposited on the cathode region 22 distal to the P-N junction. As is known in the art, the suicide layers 24 establish conduction to the anode region 20 and the cathode region 22. One or more insulating layers, such as oxide layer 26, are formed to isolate the active areas of the diode 10. Contacts 28 and metal layers 30 are formed in the oxide 26 to respectively establish electrical connection to the anode 20 and the cathode 22 through the suicide layers 24.
The diode 10 can be used for a variety of purposes, including use as an electrostatic discharge (ESD) protection device. For example, the cathode 22 can be coupled via the silicide layer 24 and respective contact 28 and metal layer 30 to an I/O pad, or other node, to be protected. In this aπ-angement the anode 20 is connected to ground, or Vss, via the anode's respective silicide layer 24, contact 28 and metal layer 30. In another arrangement the anode 20 is coupled to the I/O pad and the cathode 22 is coupled to a supply voltage, or Vdd
(not shown).
Bom the P+ region and N+ region are heavily doped (e.g., about 1018 atoms/cm2 to about 1022 atoms/cm2) to give the diode 10 a relatively low resistance (e.g., about 100 ohm-μm to about 300 ohm-μm) which forward biases at a relatively low bias voltage (e.g., about 0.3 volts to about 0.6 volt) and breaks down at a relatively low reverse break down voltage (e.g., about 3 volts to about 4 volts), thereby exhibiting traits important for good ESD protection.
Referring now to FIG. 2, a method 40 is illustrated in flowchart format for manufacturing the diode 10 illustrated in FIG. 1. The method 40 starts in step 42 in which an SOI wafer is manufactured. With additional reference to FIG. 3a, the SOI wafer, or SOI material, has the silicon substrate 12 having the buried oxide layer 14 disposed thereon. A silicon layer 44 (or active layer) is disposed on the buried oxide layer 14 in conventional format. The SOI arrangement illustrated in FIG. 3a is manufactured using conventional techniques.
Next, in step 46, and as illustrated in FIG. 3b, the active region 18 is defined in the silicon layer 44 by fabricating shallow trench isolation (STI) regions 16 using conventional techniques.
The P+ region, or anode 20, is formed in the active region in step 48 and as further illustrated by FIG. 3c. More specifically, the P+ region is defined by depositing a P+ mask 50 over areas where exposure to P+ implantation should be minimized, such as the future N+ region of the active region 18 and adjacent STI 16. Next, the device is doped using standard PMOS source/drain implants, such as on the order of about 1018 atoms/cm2 to about 1020 atoms/cm2, thereby forming the anode 20. Subsequently, the P+ mask is stripped from the device in step 52. The P+ implantation step may be used to simultaneously dope other areas of the wafer in the fabrication of other devices.
In similar fashion, the N+ region, or cathode 22, is formed in the active region 18 in step 54 and as further illustrated by FIG. 3d. More specifically, the N+ region is defined by depositing an N+ mask 56 over the P+ region, or anode 20, and adjacent STI 16. Next, the device is doped using standard NMOS source/drain implants, such as on the order of about 1018 atoms/cm2 to about 1020 atoms/cm2, thereby forming the cathode 22. The N+ implantation step may be used to simultaneously dope other areas of the wafer in the fabrication of other devices.
It is noted that, openings in the N+ and P+ masks should overlap with each other by at least the tolerance, or error margin in placement, of the mask to ensure that there is no undoped region in the area of a P-
N junction 58 formed at the interface of the P+ region and the N+ region. As mentioned, the N+ and P+ regions are implanted using standard NMOS and PMOS source/drain implants, respectively. Other implants, such as extension and halo implants, may or may not be blocked as is desired for the anticipated function of the diode 10 being manufactured. Subsequent to the N+ doping, the N+ mask is stripped from the device in step 60. As one skilled in the art will appreciate, the active region 18 can be doped with N+ implants prior to being doped with
P+ implants thereby reversing pairs of steps 48/52 and 54/60.
After the active region 18 has been doped, the regions for silicidation are defined by depositing a resistor-protect (RSPT) mask 62 in step 64 and as illustrated in FIG. 3e. It is noted that salicidation is taken herein to have the same meaning as silicidation. The RSPT mask 62 is placed in all regions where silicide is not desired. More specifically, the RSPT mask 62 is placed over the P-N junction 58 and extends over the P+ region and the N+ region to block the deposition of silicide over the desired active portions of the N+/P+ function. The area masked by the RSPT mask 62 is selected to result in a desired resistance of the diode 10 since, as the size of the silicide layers 24 increases, the resistance of the diode decreases. It should be appreciated that the RSPT mask 62 is used to block the silicide layers 24 from the central junction region of the active region 18, but the silicide layers 24 is allowed to form on the distal areas of the anode 20 and cathode 22, respectfully, to provide conduction to other devices as described in greater detail above. RSPT mask 62 is also deposited over the STI regions 16 to prevent silicide formation on the STI regions 16. The RSPT mask 62, typically an oxide, is conventionally used to define resistors formed on the wafer and is therefore typically a part of existing steps in most overall wafer fabrication processes. Accordingly, the RSPT mask 62 used for the salicide blocking function is deposited using the conventional techniques used when defining resistor elements.
Once the RSPT mask 62 is formed to define the silicide regions, the silicide layers 24 are formed in step 66 using conventional techniques. More specifically, silicide is formed depositing metal in at least the unmasked areas and reacting the metal with the exposed silicon areas of the anode 20 and cathode 22. Preferably, a TiSi2
(titanium) salicide process is employed, although CoSi2 (cobalt), PtSi2 (platinum) and MoSi2 (molybdenum) salicide processes may also be used. Next, the RSPT mask 62 is stripped in step 68 using conventional techniques.
Subsequently, the oxide material 26, the contacts 28 and the metal layers 30 are formed using conventional techniques in order to protect the diode 10, isolate the two silicide layers 24 and couple the diode
10 to other devices or nodes as is desired. The formation of the oxide material 26, the metal layers 30 and the contacts 28 are completed in step 70 and shown in an exemplary formation in FIG. 3f.
Although particular embodiments of the invention have been described in detail, it is understood that the invention is not limited correspondingly in scope, but includes all changes, modifications and equivalents coming within the spirit and terms of the claims appended hereto.

Claims

CLAIMSWhat is claimed is:
1. A silicon-on-insulator (SOI) diode (10), comprising: an active region (18) having an anode (20) disposed adjacent a cathode (22); a first silicide layer (24) formed on the anode (20) distal a junction between the anode (20) and the cathode (22) and a second silicide layer (24) formed on the cathode (22) distal the junction between the anode (20) and the cathode (22); and an insulating layer (26) isolating the first and second silicide layers (24).
2. The SOI diode (10) according to claim 1, wherein placement of the first and second silicide layers (24) is defined by a resistor-protect mask (62).
3. The SOI diode (10) according to claim 1, wherein the anode (20) and the cathode (22) are respectively implanted with P+ and N+ dopant before deposition of a mask (62) to define placement of the first and second silicide layers (24).
4. The SOI diode (10) according to claim 1, wherein the anode (20) and the cathode (22) are respectfully coupled to external nodes such that the SOI diode (10) is configured as an electrostatic discharge protection device.
5. The SOI diode (10) according to claim 1, wherein the SOI diode (10) has a resistance of about 100 ohm-μm to about 300 ohm-μm.
6. A method of fabricating a silicon-on-insulator (SOI) diode (10), comprising the steps of: (a) defining an active region (18) on an SOI wafer;
(b) implanting a first portion of the active region (18) with dopant to form an anode (20) and implanting a second portion of the active region (18) with dopant to form a cathode (22);
(c) depositing a resistor-protect mask (62) on a central region of the active region (18), the resistor-protect mask (62) defining silicide regions; and (d) forming a silicide layer (24) in the silicide regions defined by the resistor-protect mask (62).
7. The method according to claim 6, wherein step (b) is carried out before step (c).
8. The method according to claim 6, further comprising the step of respectively coupling the anode (20) and the cathode (22) to external nodes such that the SOI diode (10) is configured as an electrostatic discharge protection device.
9. The method according to claim 6, further comprising the step of stripping the resistor-protect mask (62) following silicide formation.
10. The method according to claim 6, wherein the central area having the resistor protect mask (62) is selected to result in the SOI diode (10) having a resistance of about 100 ohm-μm to about 300 ohm-μm.
PCT/US2001/047113 2001-01-31 2001-12-03 Partially silicide diode and method of manufacture WO2002061841A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002225999A AU2002225999A1 (en) 2001-01-31 2001-12-03 Partially silicide diode and method of manufacture

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US77473201A 2001-01-31 2001-01-31
US09/774,732 2001-01-31

Publications (2)

Publication Number Publication Date
WO2002061841A2 true WO2002061841A2 (en) 2002-08-08
WO2002061841A3 WO2002061841A3 (en) 2003-01-23

Family

ID=25102103

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/047113 WO2002061841A2 (en) 2001-01-31 2001-12-03 Partially silicide diode and method of manufacture

Country Status (2)

Country Link
AU (1) AU2002225999A1 (en)
WO (1) WO2002061841A2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10314505A1 (en) * 2003-03-31 2004-11-04 Advanced Micro Devices, Inc., Sunnyvale Improved diode structure for Soi circuits
US7358120B2 (en) 2005-09-12 2008-04-15 International Business Machines Corporation Silicon-on-insulator (SOI) read only memory (ROM) array and method of making a SOI ROM
WO2010115137A1 (en) * 2009-04-02 2010-10-07 Qualcomm Incorporated Lateral diode and method of manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0387944A1 (en) * 1989-03-13 1990-09-19 Koninklijke Philips Electronics N.V. Semiconductor device provided with a protection circuit
US5629544A (en) * 1995-04-25 1997-05-13 International Business Machines Corporation Semiconductor diode with silicide films and trench isolation
EP0923132A1 (en) * 1997-10-09 1999-06-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0387944A1 (en) * 1989-03-13 1990-09-19 Koninklijke Philips Electronics N.V. Semiconductor device provided with a protection circuit
US5629544A (en) * 1995-04-25 1997-05-13 International Business Machines Corporation Semiconductor diode with silicide films and trench isolation
EP0923132A1 (en) * 1997-10-09 1999-06-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor device

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10314505A1 (en) * 2003-03-31 2004-11-04 Advanced Micro Devices, Inc., Sunnyvale Improved diode structure for Soi circuits
US6905924B2 (en) 2003-03-31 2005-06-14 Advanced Micro Devices, Inc. Diode structure for SOI circuits
DE10314505B4 (en) * 2003-03-31 2009-05-07 Advanced Micro Devices, Inc., Sunnyvale Improved diode structure for Soi circuits
US7358120B2 (en) 2005-09-12 2008-04-15 International Business Machines Corporation Silicon-on-insulator (SOI) read only memory (ROM) array and method of making a SOI ROM
WO2010115137A1 (en) * 2009-04-02 2010-10-07 Qualcomm Incorporated Lateral diode and method of manufacturing the same
CN102379031A (en) * 2009-04-02 2012-03-14 高通股份有限公司 Lateral diode and method of manufacturing the same
JP2012523124A (en) * 2009-04-02 2012-09-27 クアルコム，インコーポレイテッド Horizontal diode and manufacturing method thereof
KR101279420B1 (en) * 2009-04-02 2013-06-27 퀄컴 인코포레이티드 Lateral diode and method of manufacturing the same
JP2015029102A (en) * 2009-04-02 2015-02-12 クアルコム，インコーポレイテッド Lateral diodes and method of manufacturing the same
US9368648B2 (en) 2009-04-02 2016-06-14 Qualcomm Incorporated Active diode having no gate and no shallow trench isolation

Also Published As

Publication number Publication date
AU2002225999A1 (en) 2002-08-12
WO2002061841A3 (en) 2003-01-23

Similar Documents

Publication Publication Date Title
TWI358811B (en) Semiconductor devices and methods for forming an e
US6987303B2 (en) Silicon-controlled rectifier structures on silicon-on insulator with shallow trench isolation
US6004838A (en) ESD protection using selective siliciding techniques
US5342798A (en) Method for selective salicidation of source/drain regions of a transistor
EP1708274B1 (en) Lateral bipolar transistor with additional ESD implant
EP0982776A2 (en) ESD protection thyristor with trigger diode
US7285830B2 (en) Lateral bipolar junction transistor in CMOS flow
US7981753B1 (en) Method and device for electrostatic discharge protection
US20020030231A1 (en) Semiconductor device having electrostatic protection circuit and method of fabricating the same
US6433395B2 (en) Electrostatic discharge protection for salicided devices
KR100723076B1 (en) Semiconductor device with transparent link area for silicide applications and fabrication thereof
US6261932B1 (en) Method of fabricating Schottky diode and related structure
US6528380B2 (en) Electro static discharge protection n-well ballast resistor device
US6589823B1 (en) Silicon-on-insulator (SOI)electrostatic discharge (ESD) protection device with backside contact plug
KR0178551B1 (en) Method of manufacturing semiconductor integrated circuit
US6121092A (en) Silicide blocking process to form non-silicided regions on MOS devices
US5386134A (en) Asymmetric electro-static discharge transistors for increased electro-static discharge hardness
US6372590B1 (en) Method for making transistor having reduced series resistance
US6462381B1 (en) Silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device with backside contact opening
JPH1022461A (en) Static discharge protective transistor and manufacture thereof
US6225166B1 (en) Method of manufacturing electrostatic discharge protective circuit
WO2002061841A2 (en) Partially silicide diode and method of manufacture
US6670245B2 (en) Method for fabricating an ESD device
US6489210B1 (en) Method for forming dual gate in DRAM embedded with a logic circuit
US6259140B1 (en) Silicide blocking process to form non-silicided regions on MOS devices

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PH PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PH PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase in:

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP