WO2002008964A2 - Circuit integre - Google Patents

Circuit integre Download PDF

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Publication number
WO2002008964A2
WO2002008964A2 PCT/EP2001/008534 EP0108534W WO0208964A2 WO 2002008964 A2 WO2002008964 A2 WO 2002008964A2 EP 0108534 W EP0108534 W EP 0108534W WO 0208964 A2 WO0208964 A2 WO 0208964A2
Authority
WO
WIPO (PCT)
Prior art keywords
cells
cell
integrated circuit
circuit according
connections
Prior art date
Application number
PCT/EP2001/008534
Other languages
German (de)
English (en)
Other versions
WO2002008964A3 (fr
Inventor
Martin Vorbach
Armin NÜCKEL
Volker Baumgarte
Gerd Ehlers
Original Assignee
Pact Informationstechnolgie Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10036627A external-priority patent/DE10036627A1/de
Priority claimed from PCT/EP2001/006703 external-priority patent/WO2002013000A2/fr
Priority to EP01969493A priority Critical patent/EP1377919A2/fr
Priority to AU2001289737A priority patent/AU2001289737A1/en
Application filed by Pact Informationstechnolgie Gmbh filed Critical Pact Informationstechnolgie Gmbh
Publication of WO2002008964A2 publication Critical patent/WO2002008964A2/fr
Priority to US10/471,061 priority patent/US7581076B2/en
Priority to AU2002254921A priority patent/AU2002254921A1/en
Priority to JP2002570052A priority patent/JP4011488B2/ja
Priority to EP02727358A priority patent/EP1540507B1/fr
Priority to PCT/EP2002/002398 priority patent/WO2002071248A2/fr
Priority to EP02712937A priority patent/EP1454258A2/fr
Priority to US10/469,910 priority patent/US20070299993A1/en
Priority to AU2002257615A priority patent/AU2002257615A1/en
Priority to JP2002570103A priority patent/JP2004535613A/ja
Priority to PCT/EP2002/002403 priority patent/WO2002071249A2/fr
Priority to JP2002570104A priority patent/JP2004536373A/ja
Priority to EP02724198.3A priority patent/EP1386220B1/fr
Priority to PCT/EP2002/002402 priority patent/WO2002071196A2/fr
Priority claimed from DE10129237A external-priority patent/DE10129237A1/de
Publication of WO2002008964A3 publication Critical patent/WO2002008964A3/fr
Priority to JP2008249116A priority patent/JP2009043276A/ja
Priority to JP2008249115A priority patent/JP2009043275A/ja
Priority to JP2008249099A priority patent/JP2009032281A/ja
Priority to JP2008249112A priority patent/JP2009020909A/ja
Priority to JP2008249106A priority patent/JP2009054170A/ja
Priority to US12/496,012 priority patent/US20090300262A1/en
Priority to US12/944,068 priority patent/US9037807B2/en
Priority to US13/043,102 priority patent/US20110173389A1/en
Priority to US13/653,639 priority patent/US9075605B2/en
Priority to US14/219,945 priority patent/US9552047B2/en
Priority to US14/231,358 priority patent/US9436631B2/en
Priority to US14/318,211 priority patent/US9250908B2/en
Priority to US14/500,618 priority patent/US9141390B2/en
Priority to US15/225,638 priority patent/US10152320B2/en
Priority to US15/408,358 priority patent/US10331194B2/en
Priority to US16/190,931 priority patent/US20190102173A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Definitions

  • the present invention relates to an integrated circuit according to the preamble of the independent claim.
  • the present invention therefore deals generally with the production of digital and / or analog semiconductor components and / or optical components.
  • the data processing device comprises a cell matrix made up of a multiplicity of orthogonally arranged, homogeneously structured cells, the function and networking of which are freely programmable. It is not specified how in practice an integrated module can advantageously be produced with this cell matrix. Besides, will not specified as shown
  • Data processing device can be manufactured in a simple manner adapted to certain applications.
  • CMOS VLSI Design by N.H. Weste and K. Eshraghian, Addison-Wesley, 2nd edition 1993, chapter 8, section 8.4.2.1 is a block layout, i.e. a floor plan of a generic, i.e. known PLA adaptable to certain applications. An illustration is shown in which a row of cells for different logical functions are arranged side by side. Also shown in Fig. 8.80 of the document is a physical implementation for a PLA, in which two different logic function blocks are provided with different connections. Here, too, it is not specified how an integrated module can be produced particularly advantageously in practice.
  • the object of the invention is to provide something new for commercial use.
  • an integrated circuit with a plurality of cells which are adjacent to one another, at least two types of cells having connections being provided, the cells being of a size which is sufficient for integrating a multiplicity of logic elements, at least one logic element being programmable on at least some of the cells and the connections are provided at at least substantially identical positions of the cell, in order to allow an arbitrary, ie not strictly regular, repetition of the cell types in the adjacent arrangement of the cells.
  • a first essential idea of the invention is therefore that an integrated, highly complex circuit, on which a multiplicity of different logic functions is implemented, can be easily produced by defining cell blocks thereon which have programmable logic elements inside the cell area and on the outside have matching ports. It was recognized that it is only possible to provide different cell types to any number of areas for the implementation of certain functions in a predetermined manner, in that way there are conductor tracks without actual function in the form of connecting lines, that is to say the number of objects to be taken into account when designing the chip is increased To be placed on the integrated circuit without having to redesign the entire circuit from scratch.
  • At least one memory, floating point arithmetic unit, integer arithmetic unit, adder, multiplier, Encryption, connection, input and / or output means can be implemented.
  • the encryption or cryptography work can be, for example, a circuit structure which, in a fixed or programmable manner, exchanges the bits of a data word with one another in order to carry out encryption or decryption.
  • a connecting means it can be provided that supplied signals are led out on an opposite cell side without any change; For this purpose, for example, only continuous conductor tracks are provided in the cell interior.
  • memory means can be a RAM, ROM, PROM, EEPROM memory and / or combinations of the aforementioned types of memory.
  • the input and / or output means can be used for communication with a modem connection, a network connection, a storage means and / or with a peripheral device connection such as a mouse, a printer, a display, etc.
  • Unused inputs are signals that are intended as inputs according to the universally defined wiring system, but are not used within a specific cell. These are either no longer taken into account and are therefore not wired or set to a fixed, defined value.
  • Unused outputs are signals that are intended as outputs according to the universally defined wiring system, but are not used within a specific cell. These are either connected to an input of the same cell corresponding to the wiring system or terminated in a suitable manner according to the prior art.
  • lines which are routed through a cell regardless of whether they are used or not used by the cell, definitely have an amplifier (buffer) to improve the signal quality and / or transit time and / or registers for temporal decoupling and / or other logic can be provided according to the respective circuit.
  • buffer amplifier
  • the cells for the integration will preferably be dimensioned by a number of logic elements, in particular gates, which is appropriate according to the prior art. This ensures that the additional space required for the provision of connecting lines for the cells does not have a substantially disadvantageous effect and, at the same time, that very different cell functions can be implemented.
  • the cells can preferably be dimensioned such that at least one edge length of the cells is at least 500 times, preferably at least 100 times the gate length that characterizes the manufacturing process.
  • a cell edge can therefore have at least a length of 125 ⁇ m. It is preferred if both edges of the cell do not fall below a certain minimum size.
  • at least two edge lengths of the cells can be at least 200 times, preferably at least 500 times, the gate length that characterizes the manufacturing process.
  • the cells of different types have at least substantially identical sizes, that is to say they have at most insignificant size deviations. This has the advantage that the cells can be easily strung together. Minor size differences can be compensated for, for example, by subsequently enlarging the cells in such a way that all cells correspond to the largest ones used, the peripheral connections of the cells being extended by the enlargement.
  • the result is a uniform cell format with a largely uniform bus format, or connection format and position of the peripheral connections, so that any one Geometrically, the cell can be replaced by any other one without, for example, generating a geometric error and / or layout error and / or open lines and / or short-circuited lines. If possible, any defined combination of any cells should lead to a functional circuit of any defined function.
  • strips between the cells that have a small, preferably minimal, extent. These strips can be used to adapt lines and buses between the cells, as well as their specific adaptation, which results in a higher flexibility of the circuit.
  • the advantages of the described method are completely retained in that usually pre-defined and pre-wired strips are used, which, however, can be easily modified by position in the individual special case.
  • these strips can initially be undefined and in particular empty, so that they can be routed efficiently by a router according to the prior art after the cells and strips have been positioned in such a way that there is a meaningful error-free and defined connection between the cells.
  • the proposed structure and arrangement of cells in particular enables local routing of the strips without interaction between several strips. This considerably reduces the routing and testing effort, as well as the time required for this.
  • connections will preferably comprise at least one of the connections supply voltage and / or ground, and / or at least one cell input and / or output line, it being possible in particular for the cell input and / or output line to form part of an input and / or output bus and / or includes a clock line.
  • the inlets and / or outlets provided for the respective bits will be arranged at sufficiently corresponding locations along the cell wall. This enables two or more independent busses to be brought to and / or pass through the cell without signal transfer problems becoming relevant.
  • the cell connections are guided completely to the edge, so that connections of adjacent cells abut one another on the mask and merge into one another in the integrated circuit.
  • the cell connections can be on the top and / or bottom of the cell be arranged. This allows at least two layers of cells to be provided one above the other.
  • the arithmetic units such as multipliers, adders, etc. can be arranged in a first position and the control machines connected therewith, ie state machines, in the second position.
  • the cells of the integrated circuit can each be processed individually using the design tools.
  • the "place" and “route” layout functions can be carried out for each cell, only one cell per type having to be processed, even if this cell is present several times on the integrated circuit.
  • the results of the individual work steps are saved for each cell.
  • the previously stored data of the individual cells are included in the respective routines as specifications, so that reprocessing of the cells can be omitted. Especially since duplicate identical cells have only been processed once before, the effort is significantly reduced.
  • Fig. 1 shows an integrated circuit of the present
  • FIG. 2 shows a section of the integrated circuit with a single cell; 3 different cells of the integrated circuit according to the invention with respective logic elements; Fig. 4 arrangement of cells with strips for connection; 5 shows possible functions of a strip; Fig. 6 Possible connection structures within one
  • an integrated circuit 1, generally designated 1 comprises a number of different types of cells 2a-2e with respective logic elements 3a-3e.
  • the individual cells are delimited from one another, as illustrated by boundary lines 4.
  • Connections 5a-5d are provided on the cells, which connect cells 2a-2e across the border lines to the respective neighboring cells or to the outside.
  • the cells 2a are memory cells 2a which are designed for the optional storage of data, ie for reading and / or writing operations.
  • Cell 2b is an I / O cell 2b, ie an input Output unit cell 2b.
  • the I / O cell 2b is designed to provide input and / or output to one or more peripheral devices such as a mouse, a trackball, a touchpad, a printer, a modem, a camera, a display device and / or a graphics card
  • the cells 2c are floating point unit cells 2c, ie floating point unit cells 2c, which are designed to carry out floating point arithmetic operations on data which represent floating point numbers.
  • the cells 2d are arithmetic unit cells 2d which are designed to perform logical operations and arithmetic operations on data which represent logical operands or integers.
  • the cells 2e are multiplying cells 2e which multiply link data representing numbers.
  • Each of the cells 2a to 2e is composed of a plurality of gates (not shown) in a manner known per se. These gates form the logic elements 3a-3e of the cells. At least some of the gates are programmable in each cell during runtime in order to be able to perform a required task with the cell.
  • the boundary lines 4 between the cells do not have to be implemented by a real structure. Rather, they can be defined by a space which is arranged between the closely spaced gates and other components of the cells 2a to 2e and which is only crossed by the lines of the connections 5 and which, in the case of a good design, has at most little expansion.
  • the possibly only imaginary boundary lines 4 can be arranged so that the individual cells 2a to 2e have at least substantially identical sizes.
  • the boundary lines 4 form a rectangle 6 circumscribing the respective cell 2, which has sides 4a-4d, cf. Fig. 2.
  • connections 5a-5d are provided on each of the sides 4a to 4d, which connect the cells 2a-2e to the respective neighboring cells or lead to the outside from the integrated circuit and / or on the outer sides of the outer cells of the integrated circuit 1 are completed in a suitable manner.
  • Connection 5a represents a bus connection 5a consisting of input lines 7a and output lines 7b.
  • Connection 5c represents a bus connection 5c consisting of input lines 8b and output lines 8a.
  • Switches are provided in the interior of cell 2d to selectively supply data from the input lines 7a of bus connection 5a to transmit the output lines 8a of the bus connection 5c and / or to transmit other data with the same data format to the output lines 8a.
  • An internal bus 9 is thus provided.
  • the input lines 7a and the output lines 8a are led directly to the cell edge defined by the boundary line 4a or 4c.
  • the input lines 7a are so exactly opposite the respective output lines 8a that at
  • output lines 8a of the first cell are in electrically conductive connection with input lines 7a of the second cell.
  • output lines 7b are also provided at connection 5a, which correspond to input lines 8b of connection 5c, as previously explained for the input / output line pair 7a, 8a.
  • the input and output lines provided on page 4b also correspond of connection 5b with output and input lines of connection 5d of side 4d.
  • an arithmetic unit 10 for linking data arriving on the input lines of the connections 5 as well as an associated automatic control unit 11 and a series of internal connections 12a to 12c between them and for connecting them to the bus 9 in a manner known per se intended.
  • the cells 2a to 2e of the different cell types have identical sizes as illustrated by the identical size of the boundary lines 4 circumscribing the cell.
  • the connecting lines 5 of all cells 2a to 2e are each brought up to the cell boundary 4, where they are located in the same positions.
  • the internal connections between the connections 5 to a cell 2 with each other and to the logical elements provided in the cell can vary from cell to cell.
  • Fig. 4 shows an arrangement of cells (0401) which are connected to one another by strips (0402).
  • the strips can be used for the following functions, for example:
  • Figure 5 shows some wiring examples for strips (0503).
  • 0501 and 0502 represent two cells that can be the same or different.
  • Several outputs from 0501 are forwarded as a bus directly to 0502 (0504).
  • an output is wired to multiple inputs.
  • the output and / or inputs can also be configured individually or together as bidirectional lines.
  • 0506 shows a simple wiring, in which the line is not directly wired, but leads from one position at 0501 to another position at 0502.
  • 0508 shows an output terminated via an H-level resistor.
  • 0509 shows an open bidirectional line.
  • An input defined with H level is shown with 0510.
  • 0507 shows two rotated signals that are also routed to other positions.
  • 0512 shows an input defined with L level.
  • 0513 shows a bidirectional line defined by an L-level resistor.
  • 0511 shows an open entrance. It should be stated that other types of wiring and combinations than those shown as examples are also possible
  • drivers, registers, decoders and other active elements can also be accommodated in the strips, for example.
  • the use of test structures and connections and identifiers (e.g. barcodes) in the strips is conceivable for the testing of modules.
  • FIG. 6 shows a possible wiring of universal lines in a cell 0601.
  • a first exemplary line is led directly through the cell (0602) and has a possible connection to the cell (0603).
  • Another line (0604) is led through the cell by an active element (0605) and also has a possible branch (0606).
  • the active element can have any configuration, for example as
  • Figure 7 shows the innovation in the design flow of the described method. Any flow first processes the individual cells, whereby multiple identical cells only have to be processed once (0701). The results are saved (0702). In the subsequent processing of the entire integrated circuit, the global processing is carried out, the individual cells not having to be reprocessed, but the data required in each case being read from the database (0702).
  • FIG. 8 shows a cell grid (0801) for designing a basic structure. Individual cells can correspond exactly to the grid (0802), possibly by using strips to compensate for the dimensions. Furthermore, cells can be dimensioned as a multiple of the grid (0803, 0804) or have any shape that fits into the grid (0805).
  • the integrated circuit of the present invention is manufactured as follows:
  • the memory capacities, computing power, input / output requirements, etc. of the integrated circuit 1 required for a specific application are determined. Then it is determined with which circuits such as memory, floating point arithmetic, integer arithmetic, adder, multiplier, encryption, connection, input and / or output circuits etc. these functions can be implemented. These circuits are now grouped together in blocks in order to form respective cell types define, for example RAM cells (memory cell for random access), I / O cells, floating point unit cells, arithmetic unit cells, multiplying cells, etc. If necessary, it is checked whether these functions are already provided for previously manufactured integrated circuits were. An attempt is made to distribute the desired functions over different cell types in such a way that all cell types have at least approximately the same area requirement. The cell type with the highest space requirement determines the size of all cell types.
  • RAM cells memory cell for random access
  • I / O cells floating point unit cells
  • multiplying cells etc.
  • the connecting lines 5 required between the cells are determined. Then a spatial arrangement of the connecting lines 5 on the cells is determined.
  • the cells of the respective cell types 2a to 2e are then designed in each case without being influenced by the design of the other cell types. In this case, 2 line connections 5 are placed from the inside of the cells to the cell edge 4.
  • some may be designed in each cell so that they can be programmed during runtime in order to be able to perform a required task with the cell. This is the case if, for example, the connection structure can be changed, i.e. the evaluated connections and / or the function of an arithmetic unit, etc. can be changed.
  • each individual cell type is then checked for itself without the functionality and / or geometry of other cell types having to be checked at the same time. This significantly reduces the overall computing effort for checking the integrated circuit and thus enables the simple design of highly complex circuits from regularly repeating, even complex units.
  • an overall design is created in which the different cell types are placed side by side so that the corresponding input and output lines are in an electrically conductive connection. Then, if necessary, the electrical connections between the cells are checked functionally and / or geometrically. The inspection effort for this is also very low, in particular because mostly every edge between the cells (or each strip) can be inspected individually.
  • non-repeating units such as overvoltage protection circuits, the seals, ie chip terminations, line terminations for connecting lines located at the edge of the circuit, test structures, interface structures, controls, memories, etc.
  • single configuration manager can be provided, the has a connection line arrangement that differs from the other cell types.
  • the cells do not necessarily have to be square.
  • other configurations of other cell forms can be used, which allow an overlapping arrangement next to or on top of one another.
  • hexagonal or triangular cells is conceivable.
  • two or more cell forms e.g. Triangles with trapezoids.
  • the connections at the cell boundaries are then positioned for all cell forms in such a way that a neighborly arrangement of the various cell forms is possible as desired. This means that the connections are also at at least substantially identical positions of the cell, so as to enable the cell type mixing according to the invention in the adjacent arrangement of the cells.
  • the corresponding input and output lines on adjacent sides of the cells do not necessarily have to be connected via a bus structure, so it is in particular possible to output data other than the one fed in on one side on the opposite.
  • the data can be changed, for example, by the calculator.
  • the wiring can also be carried out by optical means in addition to a conventional electrical configuration.
  • RAM cell memory cell for random access

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un circuit intégré comprenant plusieurs cellules voisines, de deux types au moins, qui présentent des connexions. Selon l'invention, les cellules présentent une taille suffisante pour l'intégration d'une multitude d'éléments logiques : au moins un élément logique est programmable sur au moins quelques-unes des cellules et les connexions sont situées à des positions au moins pratiquement concordantes de la cellule pour permettre un mélange des types de cellules pour l'agencement voisin des cellules.
PCT/EP2001/008534 2000-07-24 2001-07-24 Circuit integre WO2002008964A2 (fr)

Priority Applications (31)

Application Number Priority Date Filing Date Title
EP01969493A EP1377919A2 (fr) 2000-07-24 2001-07-24 Circuit integre
AU2001289737A AU2001289737A1 (en) 2000-07-24 2001-07-24 Integrated circuit
JP2002570104A JP2004536373A (ja) 2001-03-05 2002-03-05 データ処理方法およびデータ処理装置
PCT/EP2002/002402 WO2002071196A2 (fr) 2001-03-05 2002-03-05 Procede et dispositif pour la mise en forme et/ou le traitement de donnees
EP02724198.3A EP1386220B1 (fr) 2001-03-05 2002-03-05 Procede et dispositif pour la mise en forme et/ou le traitement de donnees
PCT/EP2002/002398 WO2002071248A2 (fr) 2001-03-05 2002-03-05 Procedes et dispositifs pour mettre en forme et/ou traiter des donnees
AU2002257615A AU2002257615A1 (en) 2001-03-05 2002-03-05 Methods and devices for treating and/or processing data
JP2002570052A JP4011488B2 (ja) 2001-03-05 2002-03-05 データ加工および／またはデータ処理方法および装置
EP02727358A EP1540507B1 (fr) 2001-03-05 2002-03-05 Dispositif pour traiter des données avec un réseau d'élements reconfigurables
US10/471,061 US7581076B2 (en) 2001-03-05 2002-03-05 Methods and devices for treating and/or processing data
EP02712937A EP1454258A2 (fr) 2001-03-05 2002-03-05 Procede et dispositif pour mettre en forme et/ou traiter des donnees
US10/469,910 US20070299993A1 (en) 2001-03-05 2002-03-05 Method and Device for Treating and Processing Data
AU2002254921A AU2002254921A1 (en) 2001-03-05 2002-03-05 Methods and devices for treating and processing data
JP2002570103A JP2004535613A (ja) 2001-03-05 2002-03-05 データ処理方法およびデータ処理装置
PCT/EP2002/002403 WO2002071249A2 (fr) 2001-03-05 2002-03-05 Procede et dispositif pour mettre en forme et/ou traiter des donnees
JP2008249099A JP2009032281A (ja) 2001-03-05 2008-09-26 データ伝送方法
JP2008249112A JP2009020909A (ja) 2001-03-05 2008-09-26 グラフのパーティショニング方法
JP2008249116A JP2009043276A (ja) 2001-03-05 2008-09-26 Ｆｉｆｏ記憶方法
JP2008249106A JP2009054170A (ja) 2001-03-05 2008-09-26 データ流の管理方法
JP2008249115A JP2009043275A (ja) 2001-03-05 2008-09-26 シーケンスの形成方法
US12/496,012 US20090300262A1 (en) 2001-03-05 2009-07-01 Methods and devices for treating and/or processing data
US12/944,068 US9037807B2 (en) 2001-03-05 2010-11-11 Processor arrangement on a chip including data processing, memory, and interface elements
US13/043,102 US20110173389A1 (en) 2001-03-05 2011-03-08 Methods and devices for treating and/or processing data
US13/653,639 US9075605B2 (en) 2001-03-05 2012-10-17 Methods and devices for treating and processing data
US14/219,945 US9552047B2 (en) 2001-03-05 2014-03-19 Multiprocessor having runtime adjustable clock and clock dependent power supply
US14/231,358 US9436631B2 (en) 2001-03-05 2014-03-31 Chip including memory element storing higher level memory data on a page by page basis
US14/318,211 US9250908B2 (en) 2001-03-05 2014-06-27 Multi-processor bus and cache interconnection system
US14/500,618 US9141390B2 (en) 2001-03-05 2014-09-29 Method of processing data with an array of data processors according to application ID
US15/225,638 US10152320B2 (en) 2001-03-05 2016-08-01 Method of transferring data between external devices and an array processor
US15/408,358 US10331194B2 (en) 2001-03-05 2017-01-17 Methods and devices for treating and processing data
US16/190,931 US20190102173A1 (en) 2001-03-05 2018-11-14 Methods and systems for transferring data between a processing device and external devices

Applications Claiming Priority (16)

Application Number Priority Date Filing Date Title
DE10036221.4 2000-07-24
DE10036221 2000-07-24
DE10036627.9 2000-07-27
DE10036627A DE10036627A1 (de) 2000-07-24 2000-07-27 Integrierter Schaltkreis
EPPCT/EP00/10516 2000-10-09
EPPCT/EP00/10516 2000-10-09
EP01102674.7 2001-02-07
EP01102674 2001-02-07
DE10110530 2001-03-05
DE10110530.4 2001-03-05
DE10111014.6 2001-03-07
DE10111014 2001-03-07
PCT/EP2001/006703 WO2002013000A2 (fr) 2000-06-13 2001-06-13 Protocoles et communication d'unites de configuration de pipeline
EPPCT/EP01/06703 2001-06-13
DE10129237.6 2001-06-20
DE10129237A DE10129237A1 (de) 2000-10-09 2002-06-20 Verfahren zur Bearbeitung von Daten

Publications (2)

Publication Number Publication Date
WO2002008964A2 true WO2002008964A2 (fr) 2002-01-31
WO2002008964A3 WO2002008964A3 (fr) 2003-10-23

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2001/008534 WO2002008964A2 (fr) 2000-07-24 2001-07-24 Circuit integre

Country Status (3)

Country Link
EP (1) EP1377919A2 (fr)
AU (1) AU2001289737A1 (fr)
WO (1) WO2002008964A2 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003083696A1 (fr) * 2002-04-03 2003-10-09 Centre National De La Recherche Scientifique - Cnrs - Architecture de calcul logique comprenant plusieurs modes de configuration
EP2043000A2 (fr) 2002-02-18 2009-04-01 PACT XPP Technologies AG Systèmes de bus et procédé de reconfiguration

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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