AU2002254921A1 - Methods and devices for treating and processing data - Google Patents

Methods and devices for treating and processing data

Info

Publication number
AU2002254921A1
AU2002254921A1 AU2002254921A AU2002254921A AU2002254921A1 AU 2002254921 A1 AU2002254921 A1 AU 2002254921A1 AU 2002254921 A AU2002254921 A AU 2002254921A AU 2002254921 A AU2002254921 A AU 2002254921A AU 2002254921 A1 AU2002254921 A1 AU 2002254921A1
Authority
AU
Australia
Prior art keywords
treating
devices
methods
processing data
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002254921A
Inventor
Volker Baumgarte
Martin Vorbach
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PACT Informationstechnologie GmbH
Original Assignee
PACT Informationstechnologie GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to DE10110530.4 priority Critical
Priority to DE10110530 priority
Priority to DE10111014.6 priority
Priority to DE10111014 priority
Priority to EPPCT/EP01/06703 priority
Priority to PCT/EP2001/006703 priority patent/WO2002013000A2/en
Priority to EP01115021 priority
Priority to EP01115021.6 priority
Priority to DE10129237.6 priority
Priority to DE10135211.5 priority
Priority to DE10135210.7 priority
Priority to EPPCT/EP01/08534 priority
Priority to DE10135210 priority
Priority to DE10135211 priority
Priority to PCT/EP2001/008534 priority patent/WO2002008964A2/en
Priority to DE10139170.6 priority
Priority to DE10139170 priority
Priority to DE10142231.8 priority
Priority to DE10142231 priority
Priority to DE10142903.7 priority
Priority to DE10142903 priority
Priority to DE10142904 priority
Priority to DE10142894 priority
Priority to DE10142904.5 priority
Priority to DE10142894.4 priority
Priority to US31787601P priority
Priority to US60/317,876 priority
Priority to DE10144732.9 priority
Priority to DE10144733 priority
Priority to DE10144733.7 priority
Priority to DE10144732 priority
Priority to DE10145795.2 priority
Priority to DE10145795 priority
Priority to DE10145792.8 priority
Priority to DE10145792 priority
Priority to DE10146132 priority
Priority to DE10146132.1 priority
Priority to US09/967,847 priority patent/US7210129B2/en
Priority to US09/967,847 priority
Priority to EP0111299 priority
Priority to EPPCT/EP01/11299 priority
Priority to PCT/EP2001/011593 priority patent/WO2002029600A2/en
Priority to EPPCT/EP01/11593 priority
Priority to DE10154260 priority
Priority to DE10154259.3 priority
Priority to DE10154260.7 priority
Priority to DE10154259 priority
Priority to EP01129923.7 priority
Priority to EP01129923 priority
Priority to EP02001331 priority
Priority to EP02001331.4 priority
Priority to DE10202044.2 priority
Priority to DE10202044 priority
Priority to DE10202175.9 priority
Priority to DE10202175 priority
Priority to DE10206653.1 priority
Priority to DE10206653 priority
Priority to DE10206857.7 priority
Priority to DE10206856.9 priority
Priority to DE10206857 priority
Priority to DE10206856 priority
Priority to DE10207225 priority
Priority to DE10207226 priority
Priority to DE10207225.6 priority
Priority to DE10207226.4 priority
Priority to DE10207224.8 priority
Priority to DE10207224 priority
Priority to DE10208435.1 priority
Priority to DE10208434 priority
Priority to DE10208434.3 priority
Priority to DE10208435 priority
Application filed by PACT Informationstechnologie GmbH filed Critical PACT Informationstechnologie GmbH
Priority to PCT/EP2002/002402 priority patent/WO2002071196A2/en
Priority to DE10129237A priority patent/DE10129237A1/en
Publication of AU2002254921A1 publication Critical patent/AU2002254921A1/en
Application status is Abandoned legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/40Transformation of program code
    • G06F8/41Compilation
    • G06F8/44Encoding
    • G06F8/447Target code generation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/17Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
AU2002254921A 2000-06-13 2002-03-05 Methods and devices for treating and processing data Abandoned AU2002254921A1 (en)

Priority Applications (73)

Application Number Priority Date Filing Date Title
DE10110530.4 2001-03-05
DE10110530 2001-03-05
DE10111014.6 2001-03-07
DE10111014 2001-03-07
PCT/EP2001/006703 WO2002013000A2 (en) 2000-06-13 2001-06-13 Pipeline configuration unit protocols and communication
EPPCT/EP01/06703 2001-06-13
EP01115021.6 2001-06-20
DE10129237.6 2001-06-20
EP01115021 2001-06-20
DE10135210.7 2001-07-24
EPPCT/EP01/08534 2001-07-24
DE10135210 2001-07-24
DE10135211 2001-07-24
PCT/EP2001/008534 WO2002008964A2 (en) 2000-07-24 2001-07-24 Integrated circuit
DE10135211.5 2001-07-24
DE10139170 2001-08-16
DE10139170.6 2001-08-16
DE10142231 2001-08-29
DE10142231.8 2001-08-29
DE10142903 2001-09-03
DE10142904 2001-09-03
DE10142894 2001-09-03
DE10142904.5 2001-09-03
DE10142894.4 2001-09-03
DE10142903.7 2001-09-03
US31787601P true 2001-09-07 2001-09-07
US60/317,876 2001-09-07
DE10144733 2001-09-11
DE10144733.7 2001-09-11
DE10144732 2001-09-11
DE10144732.9 2001-09-11
DE10145795 2001-09-17
DE10145792.8 2001-09-17
DE10145792 2001-09-17
DE10145795.2 2001-09-17
DE10146132.1 2001-09-19
DE10146132 2001-09-19
US09/967,847 2001-09-28
US09/967,847 US7210129B2 (en) 2001-08-16 2001-09-28 Method for translating programs for reconfigurable architectures
EP0111299 2001-09-30
EPPCT/EP01/11299 2001-09-30
PCT/EP2001/011593 WO2002029600A2 (en) 2000-10-06 2001-10-08 Cell system with segmented intermediate cell structure
EPPCT/EP01/11593 2001-10-08
DE10154259.3 2001-11-05
DE10154260 2001-11-05
DE10154260.7 2001-11-05
DE10154259 2001-11-05
EP01129923.7 2001-12-14
EP01129923 2001-12-14
EP02001331.4 2002-01-18
EP02001331 2002-01-18
DE10202044 2002-01-19
DE10202044.2 2002-01-19
DE10202175 2002-01-20
DE10202175.9 2002-01-20
DE10206653.1 2002-02-15
DE10206653 2002-02-15
DE10206857.7 2002-02-18
DE10206856.9 2002-02-18
DE10206857 2002-02-18
DE10206856 2002-02-18
DE10207226 2002-02-21
DE10207225.6 2002-02-21
DE10207226.4 2002-02-21
DE10207224.8 2002-02-21
DE10207225 2002-02-21
DE10207224 2002-02-21
DE10208434 2002-02-27
DE10208434.3 2002-02-27
DE10208435 2002-02-27
DE10208435.1 2002-02-27
PCT/EP2002/002402 WO2002071196A2 (en) 2001-03-05 2002-03-05 Methods and devices for treating and processing data
DE10129237A DE10129237A1 (en) 2000-10-09 2002-06-20 Integrated cell matrix circuit has at least 2 different types of cells with interconnection terminals positioned to allow mixing of different cell types within matrix circuit

Publications (1)

Publication Number Publication Date
AU2002254921A1 true AU2002254921A1 (en) 2002-09-19

Family

ID=56290255

Family Applications (2)

Application Number Title Priority Date Filing Date
AU2002257615A Abandoned AU2002257615A1 (en) 2000-06-13 2002-03-05 Methods and devices for treating and/or processing data
AU2002254921A Abandoned AU2002254921A1 (en) 2000-06-13 2002-03-05 Methods and devices for treating and processing data

Family Applications Before (1)

Application Number Title Priority Date Filing Date
AU2002257615A Abandoned AU2002257615A1 (en) 2000-06-13 2002-03-05 Methods and devices for treating and/or processing data

Country Status (4)

Country Link
EP (2) EP1540507B1 (en)
JP (3) JP2004536373A (en)
AU (2) AU2002257615A1 (en)
WO (2) WO2002071248A2 (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1466264B1 (en) 1995-12-29 2011-09-14 Richter, Thomas Method for configuration of the connection between data processing cells
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
AU2003214003A1 (en) 2002-02-18 2003-09-09 Pact Xpp Technologies Ag Bus systems and method for reconfiguration
WO2005045692A2 (en) * 2003-08-28 2005-05-19 Pact Xpp Technologies Ag Data processing device and method
DE10357284A1 (en) * 2003-12-05 2005-07-14 Pact Xpp Technologies Ag Data processor comprises multidimensional array of coarse grained logic elements operating at clock rate greater than that of bus and/or communication line connecting logic elements mutually and with other elements
US20060126770A1 (en) * 2004-12-15 2006-06-15 Takeshi Yamazaki Methods and apparatus for providing an asynchronous boundary between internal busses in a multi-processor device
JP4909588B2 (en) * 2005-12-28 2012-04-04 ルネサスエレクトロニクス株式会社 Information processing apparatus and method of using reconfigurable device
US7693257B2 (en) 2006-06-29 2010-04-06 Accuray Incorporated Treatment delivery optimization
FR2922663B1 (en) * 2007-10-23 2010-03-05 Commissariat Energie Atomique Structure and method of backup and restoration of data
US9086973B2 (en) 2009-06-09 2015-07-21 Hyperion Core, Inc. System and method for a cache in a multi-core processor
CN102281054A (en) * 2011-04-25 2011-12-14 浙江大学 Reconfigurable computing array data coupler for data-driven
JP2016178229A (en) 2015-03-20 2016-10-06 株式会社東芝 Reconfigurable circuit

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06101043B2 (en) * 1988-06-30 1994-12-12 三菱電機株式会社 Micro computer
US5193202A (en) * 1990-05-29 1993-03-09 Wavetracer, Inc. Processor array with relocated operand physical address generator capable of data transfer to distant physical processor for each virtual processor while simulating dimensionally larger array processor
DE4416881C2 (en) 1993-05-13 1998-03-19 Pact Inf Tech Gmbh A method of operating a data processing device
IT1260848B (en) * 1993-06-11 1996-04-23 Finmeccanica Spa Multiprocessor System
EP0721157A1 (en) * 1994-12-12 1996-07-10 Advanced Micro Devices Inc. Microprocessor with selectable clock frequency
US5892370A (en) * 1996-06-21 1999-04-06 Quicklogic Corporation Clock network for field programmable gate array
DE19651075A1 (en) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Unit for processing numerical and logical operations used in processors (CPU's), multiprocessor systems, Datenflußprozessoren (DFP's), digital signal processors (DSP's) or the like
DE19654593A1 (en) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh Reconfiguration method for programmable devices at runtime
DE19654846A1 (en) 1996-12-27 1998-07-09 Pact Inf Tech Gmbh A method for automatic dynamic reloading of Datenflußprozessoren (DFP) and modules having a two- or multi-dimensional programmable cell structure (FPGAs, DPGAs, o. The like).
DE19704044A1 (en) 1997-02-04 1998-08-13 Pact Inf Tech Gmbh Address generation with systems having programmable modules
DE19704728A1 (en) * 1997-02-08 1998-08-13 Pact Inf Tech Gmbh A method for self-synchronization of configurable elements of a programmable block
DE19861088A1 (en) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Repairing integrated circuits by replacing subassemblies with substitutes
DE19807872A1 (en) 1998-02-25 1999-08-26 Pact Inf Tech Gmbh Method of managing configuration data in data flow processors
EP1228440B1 (en) * 1999-06-10 2017-04-05 PACT XPP Technologies AG Sequence partitioning in cell structures
DE10028397A1 (en) 2000-06-13 2001-12-20 Pact Inf Tech Gmbh Registration method in operating a reconfigurable unit, involves evaluating acknowledgement signals of configurable cells with time offset to configuration
DE10036627A1 (en) 2000-07-24 2002-02-14 Pact Inf Tech Gmbh Integrated cell matrix circuit has at least 2 different types of cells with interconnection terminals positioned to allow mixing of different cell types within matrix circuit

Also Published As

Publication number Publication date
JP2004535613A (en) 2004-11-25
JP2004538675A (en) 2004-12-24
WO2002071248A2 (en) 2002-09-12
WO2002071196A8 (en) 2003-10-30
EP1540507A2 (en) 2005-06-15
JP2004536373A (en) 2004-12-02
EP1540507B1 (en) 2012-05-23
WO2002071196A3 (en) 2003-12-04
WO2002071248A3 (en) 2005-04-21
WO2002071196A2 (en) 2002-09-12
WO2002071248A8 (en) 2004-01-29
AU2002257615A1 (en) 2002-09-19
EP1454258A2 (en) 2004-09-08
JP4011488B2 (en) 2007-11-21

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase