WO2001080549A1 - Dispositif pour traiter des signaux video numeriques en temps reel - Google Patents

Dispositif pour traiter des signaux video numeriques en temps reel Download PDF

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Publication number
WO2001080549A1
WO2001080549A1 PCT/EP2001/004364 EP0104364W WO0180549A1 WO 2001080549 A1 WO2001080549 A1 WO 2001080549A1 EP 0104364 W EP0104364 W EP 0104364W WO 0180549 A1 WO0180549 A1 WO 0180549A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
arrangement according
video signals
interface
digital video
Prior art date
Application number
PCT/EP2001/004364
Other languages
German (de)
English (en)
Inventor
Sieghard Hasenzahl
Rolf Ernst
Peter Rueffer
Kersten Henriss
Original Assignee
Koninklijke Philips Electronics N.V.
Philips Corporate Intellectual Property Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V., Philips Corporate Intellectual Property Gmbh filed Critical Koninklijke Philips Electronics N.V.
Priority to EP01945011A priority Critical patent/EP1417830A1/fr
Publication of WO2001080549A1 publication Critical patent/WO2001080549A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/443—OS processes, e.g. booting an STB, implementing a Java virtual machine in an STB or power management in an STB
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/46—Receiver circuitry for the reception of television signals according to analogue transmission standards for receiving on more than one standard at will

Definitions

  • the invention relates to an arrangement for processing digital video signals in real time.
  • Real-time processing is generally required in professional television studios and within television technology equipment. This can consist, for example, of mixing different signals, filtering or influencing the video signals with respect to their characteristic (gradation, black contrast, overall amplitude and the individual components of a color video signal with one another).
  • circuits for processing these signals also became known, but because of the relatively high data rate - for example in the CCIR 601 standard, 270 Mbit / s - they are special "hardware" circuits.
  • the object of the present invention is to propose an arrangement for real-time processing of digital video signals which is largely neutral on the hardware side and can be configured and reconfigured by appropriate software.
  • This object is achieved according to the invention by at least one field-programmable gate array which can be configured by a program for the respective processing.
  • a particularly cheap and fast signal processing enables a further development of the arrangement according to the invention in that a memory is formed by at least one SDRAM, into which video data streams to be processed, processed and forming intermediate results can be written and read out from the memory such that the Arrangement supplied digital video signals recorded in real time and processed digital video signals are output in real time. It is preferably provided that a plurality of memory banks are formed in the memory, which are activated overlapping in time for memory accesses.
  • this development can be designed in such a way that data from a plurality of pixels is processed as a data block and stored in the memory under a start address. This makes optimal use of the available memory bandwidth.
  • the arrangement according to the invention can have two inputs and two
  • Outputs for digital video signals can be provided.
  • the arrangement according to the invention can be used for standard television, for example for digital video signals in accordance with CCIR 601, or for high-definition television (HDTV), for example in accordance with the SMPTE 274M standard.
  • One embodiment of the invention is that two independent video
  • Inputs with 20 bits each in parallel and two synchronous 20 bit parallel video outputs are provided for high-definition television, whereby only 10 bits are required for standard television according to CCIR 601.
  • parameters and / or tables for processing the digital video signals can also be stored in the memory.
  • These parameters or tables can represent, for example, non-linear characteristic curves.
  • the processing of digital video signals in real time does not mean that the video signals are present at the outputs without delay. For example, there may be delays of a few lines or even images if processing so requires - for example if signals from several images are integrated for the purpose of noise reduction.
  • the at least one field-programmable gate array contains a video Interface area, an interface area for the memory, an interface area for a digital signal processor and an interface area for an arithmetic unit also formed by the field programmable gate array.
  • a configuration of the field-programmable gate array can be carried out by a program that is stored outside the arrangement, for example on a hard disk.
  • the digital signal processor is used, among other things, to initiate and control the loading of this program.
  • the digital signal processor can also take on administrative tasks in the operation of the arrangement according to the invention. If individual interface areas access the memory several times in succession, it could happen that other interface areas cannot make memory accesses that are necessary for real-time processing. In order to prevent such congestion, a priority management for the access of the interface areas to the memory can be provided in the arrangement according to the invention. For example, the priority of a memory access can be passed on in turn.
  • Equalization of the clocks of the supplied and the output digital video signals and a further clock used for processing the video data streams are provided.
  • the formation of bursts is also possible, that is to say that in each case several pixel data are combined and processed as a data block, for example stored in the memory under a start address.
  • the memory is also operated with the further clock.
  • the digital signal processor is operated with a third clock and that the area of the interface for the digital signal processor is buffer memory to compensate for
  • FIG. 1 shows a block diagram of an arrangement according to the invention
  • FIG. 2 shows the write and read processes in the SDRAM.
  • Fig. 1 single lines are thin and multiple lines thick with correspondingly wide arrows that indicate the direction of data transmission.
  • the supplied and processed video signals as well as the processed video signals are referred to as digital video signals.
  • the data transmitted with the aid of a data bus 37 which for the most part also represent image information, are referred to as video data or video data streams, in order to emphasize that there is no pixel-by-bit serial data stream here.
  • FIG. 1 shows an arrangement according to the invention with a field-programmable gate array 1, which is configured via a permanently installed configuration interface 2 with the aid of a program supplied at 3 in the form of a JT AG program code.
  • a field-programmable gate array For example, a reconfigurable Xilinx Virtex XCV600 or XC4085 field programmable gate array (FPGA) is suitable for the invention.
  • the following areas are formed by the configuration:
  • DSP interface for a digital signal processor
  • FIG. 1 Of the interfaces 4, 5, 6 and 8, only FIFO memories 9, 10, 11, 12 are shown, which are important for understanding the timing of the signal processing. Further functions, in particular the control of the signal curve between the interfaces and the further components, are not shown in FIG. 1.
  • An SDRAM 13 and a digital signal processor 14 are connected to the field-programmable gate array 1. Both the SDRAM 13 and the digital signal processor 14 each have their own clock generator 15, 16.
  • an arithmetic extension 17 can be connected. This can be a coprocessor or a processing unit formed from a further field programmable gate array.
  • the digital signal processor operates with a memory unit 18 which contains an SRAM and EPROM.
  • the SRAM serves as a working memory, while data for initializing the arrangement after switching on are stored in the EPROM, which is the basis for further configuration of the arrangement with the aid of the data supplied at 3. Further data can be routed via a gate interface 19 and an input / output 20.
  • two 20 bit wide inputs 21, 22 are provided with corresponding clock inputs 23, 24.
  • two 20 bit wide outputs 25, 26 are also arranged with a common output, to which a clock input 27 is assigned , External synchronization of the two further inputs 28 can also take place.
  • bus lines 29, 30, 31 serve as control lines, in particular for the transmission of the information "request, acknowledge, read / write, read FIFO, write FIFO.
  • bus lines 32, 33, 34 serve for the transmission of frame, field
  • video synchronization signals derived within the gate array are distributed via a line 35 in the video interface to the interfaces 5, 6 and 8.
  • clock signal sD R A M generated at 15, for which purpose this is fed via lines 36 to the FIFO memories 9 to 12 and the SDRAM interface 6.
  • the clock signal fbsp from the clock generator 16 is also fed to the FIFOs 11 as an input clock as an input clock ,
  • the bus system 37 connects the outputs of the FIFO memory 9, the inputs of the FIFO memory 10, inputs and outputs of the FIFO memory 11 and the FIFO memory 12 to the data inputs / outputs of the SDRAM 13. It has the Embodiment a width of 64 bits. Other bus lines are shown in Fig. 1 corresponding to that transported by them
  • Fig. 2 illustrates the addressing as well as the write and read process with SDRAM 13.
  • the upper line represents the control data, while the lower line represents the data read or written in each case.
  • ACT means activate, NOP no operation or no operation, WR write and RD read.
  • NOP no operation or no operation
  • WR write and RD read.
  • the write process for a data block consisting of four data words Da, Da + 1, Da + 2 and Da + 3 is started at WR.
  • the data block is written from the data words Db to Db + 3.
  • the following control data cause a data block Qc to Qc + 3 to be read, whereupon again a read command comes, which results in the reading of a data block from Qd to Qd + 3.
  • the SDRAM 13 (FIG. 1) can be operated very effectively.
  • the video signals supplied according to the CCIR 601 standard comprise 10- Bit-
  • the sampling frequency is 74.25 MHz. If the SDRAM works at the same frequency, then three memory accesses per sample or data word are possible. Since the clocks of the SDRAM, the digital video signals and the digital signal processor are independent of one another through the use of FIFO memories, the number of accesses per data word of the video signals can be increased by a corresponding increase in the clock frequency fs DRAM . The write / read speed and thus also the overall processing speed can be increased by using DDR SDRAMs (double data rate SDRAMs), in which read and write processes take place on the leading and trailing edges.
  • DDR SDRAMs double data rate SDRAMs

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Software Systems (AREA)
  • Studio Circuits (AREA)

Abstract

L'invention concerne un dispositif pour traiter des signaux vidéo numériques en temps réel, comprenant au moins un circuit intégré prédiffusé à contenu programmable par l'utilisateur, qui peut être programmé pour un traitement déterminé. L'invention est caractérisée en ce que de préférence une mémoire d'au moins un SDRAM est constituée, où les flux de données vidéo devant être traités, traités et formant des résultats intermédiaires (6) peuvent y être inscrits ou lus de manière telle que les signaux vidéo numériques envoyés au dispositif sont enregistrés en temps réel et les signaux vidéo numériques traités sont émis en temps réel.
PCT/EP2001/004364 2000-04-17 2001-04-17 Dispositif pour traiter des signaux video numeriques en temps reel WO2001080549A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP01945011A EP1417830A1 (fr) 2000-04-17 2001-04-17 Dispositif pour traiter des signaux video numeriques en temps reel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP00108407.8 2000-04-17
EP00108407 2000-04-17

Publications (1)

Publication Number Publication Date
WO2001080549A1 true WO2001080549A1 (fr) 2001-10-25

Family

ID=8168493

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2001/004364 WO2001080549A1 (fr) 2000-04-17 2001-04-17 Dispositif pour traiter des signaux video numeriques en temps reel

Country Status (2)

Country Link
EP (1) EP1417830A1 (fr)
WO (1) WO2001080549A1 (fr)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5497498A (en) * 1992-11-05 1996-03-05 Giga Operations Corporation Video processing module using a second programmable logic device which reconfigures a first programmable logic device for data transformation
DE19535100A1 (de) * 1994-10-21 1996-04-25 Mitsubishi Electric Corp Bildverarbeitungseinrichtung, die Pixeldaten mit einer hohen Datenübertragungsrate übertragen kann
WO1998047292A1 (fr) * 1997-04-11 1998-10-22 Eidos Technologies Limited Procede et systeme de traitement d'informations numeriques
WO2000017766A2 (fr) * 1998-09-22 2000-03-30 Cybex Computer Products Corporation Systeme et procede permettant l'acces et l'exploitation a distance sur ordinateur personnel
US6151682A (en) * 1997-09-08 2000-11-21 Sarnoff Corporation Digital signal processing circuitry having integrated timing information
WO2001008017A1 (fr) * 1999-07-23 2001-02-01 Apex Inc. Procede et systeme destines a la commande intelligente d'un ordinateur hors-site

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5497498A (en) * 1992-11-05 1996-03-05 Giga Operations Corporation Video processing module using a second programmable logic device which reconfigures a first programmable logic device for data transformation
DE19535100A1 (de) * 1994-10-21 1996-04-25 Mitsubishi Electric Corp Bildverarbeitungseinrichtung, die Pixeldaten mit einer hohen Datenübertragungsrate übertragen kann
WO1998047292A1 (fr) * 1997-04-11 1998-10-22 Eidos Technologies Limited Procede et systeme de traitement d'informations numeriques
US6151682A (en) * 1997-09-08 2000-11-21 Sarnoff Corporation Digital signal processing circuitry having integrated timing information
WO2000017766A2 (fr) * 1998-09-22 2000-03-30 Cybex Computer Products Corporation Systeme et procede permettant l'acces et l'exploitation a distance sur ordinateur personnel
WO2001008017A1 (fr) * 1999-07-23 2001-02-01 Apex Inc. Procede et systeme destines a la commande intelligente d'un ordinateur hors-site

Also Published As

Publication number Publication date
EP1417830A1 (fr) 2004-05-12

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