WO2001078475A1 - Procede et dispositif de fabrication d'elements de connexion electrique, et element de connexion resultant - Google Patents

Procede et dispositif de fabrication d'elements de connexion electrique, et element de connexion resultant Download PDF

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Publication number
WO2001078475A1
WO2001078475A1 PCT/CH2001/000200 CH0100200W WO0178475A1 WO 2001078475 A1 WO2001078475 A1 WO 2001078475A1 CH 0100200 W CH0100200 W CH 0100200W WO 0178475 A1 WO0178475 A1 WO 0178475A1
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WO
WIPO (PCT)
Prior art keywords
perforation
layer
conducting
substrate
tip
Prior art date
Application number
PCT/CH2001/000200
Other languages
English (en)
Inventor
Walter Schmidt
Kurt Grohmann
Original Assignee
Dyconex Patente Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Dyconex Patente Ag filed Critical Dyconex Patente Ag
Priority to PCT/CH2001/000200 priority Critical patent/WO2001078475A1/fr
Priority to AU2001242204A priority patent/AU2001242204A1/en
Publication of WO2001078475A1 publication Critical patent/WO2001078475A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
    • H05K3/041—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by using a die for cutting the conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4084—Through-connections; Vertical interconnect access [VIA] connections by deforming at least one of the conductive layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0376—Flush conductors, i.e. flush with the surface of the printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/091—Locally and permanently deformed areas including dielectric material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
    • H05K2203/0108—Male die used for patterning, punching or transferring
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0191—Using tape or non-metallic foil in a process, e.g. during filling of a hole with conductive paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0195—Tool for a process not provided for in H05K3/00, e.g. tool for handling objects using suction, for deforming objects, for applying local pressure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0285—Using ultrasound, e.g. for cleaning, soldering or wet treatment
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/09—Treatments involving charged particles
    • H05K2203/095—Plasma, e.g. for treating a substrate to improve adhesion with a conductor or for cleaning holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1189—Pressing leads, bumps or a die through an insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
    • H05K3/046—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4632—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating thermoplastic or uncured resin sheets comprising printed circuits without added adhesive materials between the sheets
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H05K3/4658—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern characterized by laminating a prefabricated metal foil pattern, e.g. by transfer

Definitions

  • the invention relates to methods for fabricating electrical connecting elements such as Printed Circuit Boards (PCBs), High-Density-Interconnects (HDIs), Ball-Grid- Array- (BGA-) substrates, Chip Scale Packages (CSP), Multi-Chip-Module- (MCM) substrates, etc. It also relates to a electrical connecting element and to an apparatus for fabricating electrical connecting elements.
  • PCBs Printed Circuit Boards
  • HDIs High-Density-Interconnects
  • BGA- Ball-Grid- Array-
  • CSP Chip Scale Packages
  • MCM Multi-Chip-Module-
  • microvias In modern circuit board technology, due to increasing miniaturization, conventionally drilled through holes are more and more replaced by microvias. Methods for fabricating such microvias include laser drilling and plasma drilling as well as photochemical structuring. A new method for fabricating microvias has been disclosed in WO 00/13062. This new technology approach, the Micro-Perforation, is a method including mechanical embossing of micro-holes into deformable dielectric material. With Micro-Perforation, any shape of a microvia is feasible. By controlling the length and size of perforation-tips also the formation of very small blind microvias can be achieved.
  • a via fabricating step has to be followed by a contacting step between the conducting layers or pads across the via.
  • a contacting step may be a chemical or physical deposition of some conductor material as a seed layer followed by an electroplating step.
  • Plating of very small blind holes of lOO ⁇ m Diameter and less is very tricky and often results in non-plated holes and consequently scrapped boards.
  • incomplete plating of side walls of the holes affects the reliability of the boards. It therefore would be desirable to have a method which allows to omit this plating step. Omitting the plating step, apart from the elimination of the above shortcomings, would also lead to a considerable reduction of production cost and of environmental impact caused by wet chemical bathes .
  • the invention is essentially characterized in that a mechanical via forming step is combined with a metal connecting step such as a cold welding process or a soldering process.
  • the method according to the invention thus combines a perforation step with a contacting step and thus eliminates plating after perforation.
  • the connecting step may be a cold welding step which is performed at the appropriate temperature between conductor material of a first conducting layer and conductor material of a second conducting layer, the layers being separated by an insulating layer.
  • the first conducting layer is locally pressed through the insulating layer by a perforation tip.
  • the connecting step may also be any other metal connecting and/or fusing step between conductor material of two layers, the only restriction being that the metals of two layers in some way coalesce.
  • a further example is e.g. a soldering step. In this case, conductor material of a conductor layer to be connected to an other conductor layer is in a previous step provided with soldering material.
  • Other examples of a connecting step according to the invention include welding with energy input such as hot welding or ultrasonic welding.
  • Perforation can according to the invention be combined with a connecting step if it results in a mechanical deformation of the materials involved, rather than in piercing of one or more layers.
  • additional energy is supplied.
  • This energy may be supplied in the form of heat.
  • the energy may also be supplied as ultrasonic energy.
  • This embodiment makes the fabrication of well fused and thus reliable connections particularly easy and straightforward.
  • Supplying energy in the form of ultrasonic vibrations can ideally be combined with a piezo actuated perforation tool. This can be done by modulating the piezo voltage by a signal with ultrasonic frequency.
  • Figs. la through Id schematically show a PCB HDI substrate (or a component of such a PCB HDI substrate, respectively) during different stages of the production
  • FIGS. 2a and 2b also schematically show a PCB HDI substrate (or a component of such a PCB/HDI substrate, respectively) during different stages of the production if it is produced according to an other embodiment of the invention
  • Figures 3a through 3c schematically represent a top cap or a bottom cap of a four layer build up PCB HDI during different stages of the production
  • Figures 4a and 4b schematically show the production of a component of a four layer build-up using components produced according to figures la through Id and 3a through 3c,
  • Figures 5a and 5b show examples of tip shapes
  • Figures 6a and 6b show the principle of the piezo perforation technique and a voltage/time chart of the piezo actuator if the piezo perforation technique is used
  • Figure 7 shows a photograph of a cut through a product produced according to the invention
  • Figures 8a-8g, 9a- 9e, and 10a- 10c show a process sequence for the production of a 4-layer foil-based PCB/HDI with micro-perforation and micro-punching technology.
  • Figures la, lb, lc and Id show a process to manufacture PCB HDI substrates or semi-finished products for the production thereof by means of a combination of micro-perforation and a special connecting technology according to the invention.
  • Figures la-Id or 2a-2c
  • 3a-3c and 4a-4b a process for manufacturing a four layer build-up is described.
  • a PCB/HDI substrate of two layers can be produced using the procedure of Fig. la-Id or Fig. 2a-2d.
  • Fig. la-Id Fig. 2a-2d.
  • the appropriate number of semifinished products produced according to Fig. 3a-3c has to be added.
  • the core base material 1 which is already coated by a first conducting layer 3 and a second conducting layer 5, is shown.
  • the base material (or substrate material) 1 is a dielectric, e.g. epoxy, polyimide, a liquid crystal polymer (LCP), polysulfone, polyester (PEEK), Polycarbonate etc.
  • the conducting material may be copper or a copper alloy. It may also be an other conducting material such as silver or a silver alloy.
  • the conducting layers are clad copper layers.
  • the thickness of the base material by be around 25-100 ⁇ m, the thickness of each clad copper layer around 5- 35 ⁇ m. It however goes without saying that the invention also works for other material thicknesses.
  • a perforation tool 11 is shown schematically. It is e.g. made of a coated, relatively hard metal such as a Nickel or Chromium or any other hard material. It may also be made of a combination of materials, e.g. may be a Tungsten Carbide coated metal.
  • the perforation tool 11 comprises perforation tips 11a.
  • the perforation equipment also comprises a support plate 13 which is also made of a hard material, e.g. steel or any other relatively hard material.
  • the shape of the perforation tips is crucial for the cold welding process to take place.
  • Two examples of usable tip shapes are schematically shown in Figures 5a and 5b, resprectively.
  • the shape depends on other manufacturing parameters such as the polymer layer thickness, the copper layer thicknesses, the perforation speed, etc. It may, e.g. be formed as a cone with rounded tip (Fig. 5a).
  • the opening angle ⁇ of the cone may then vary between 30° and 90°.
  • the radius r of the tip curvature is then e.g. between 5 ⁇ m and 100 ⁇ m. Generally, a low curvature radius will be combined with a large opening angle.
  • the opening angle will be larger than for lower perforation speed and polymer layer thicknesses.
  • the tip may also be formed as truncated cone with a rounded edge 91 (Fig. 5b).
  • the curvature radius of the edge rounding then is between 2 ⁇ m and 20 ⁇ m. It may also have other shapes, especially including not rotationally symmetric shapes. It is important, however, that it does not comprise, on a micrometer scale, any sharp tips or edges in order not to pierce through the copper layer but to deform the copper material during the MP-cold- welding-process.
  • the Micro-Perforation (MP) process may e.g. be carried out at room temperature. It may, depending on the type of the polymer layer, also be performed at a different temperature, e.g. at a temperature between room temperature and 300°C or 400°C.
  • the perforation tool 11 is pressed against the support plate 13, the clad base material 1, 3, 5 being sandwiched between the perforation tool 11 and the support plate 13 (Fig. lb).
  • the dielectric material is deformed and thrust aside.
  • the copper is formed by the die, like in a metal-forming-process and is pressed against the opposite copper layer. Since the flat support plate 13 is relatively hard, the copper is crushed against the other copper layer and is permanently connected by a cold-welding process.
  • the two conductor layers are thus electrically and mechanically connected to each other.
  • FIG. 7 a photograph of a product produced according to the above method in section is shown. As can be seen, in a connection region, the two metal layers 101, 103 are fused together.
  • the height of stroke of the perforation process is determined by the tip length, as can be seen from the drawings.
  • the perforation tips are just about as long as the sum of the thicknesses of the base material 1 and the first conducting layer 3. More precisely, for the length of the tips, the following formula holds:
  • d ⁇ M is the thickness of the base material 1
  • d ⁇ the thickness of the conducting top layer
  • dc 2 the thickness of the conducting bottom layer
  • l ⁇ i P the length of the perforation tip. It should be noted, however, that in certain setups the perforation tip height of stroke is determined by other mechanisms. Then, l ⁇ i p in the above formula should be replaced by a quantity representing the tip height of stroke in the material, i.e. the distance over which the tip is advanced after having touched the conductor material surf ce.
  • the perforation tool 11 may be configured so as to form all the required microvias in one perforation step.
  • perforation and welding may also be carried out in more than one step and using one or more dies.
  • the die and the support plate are removed (Fig. lc).
  • the copper can be structured in accordance with the layout. (Fig. Id).
  • the photo-patterning process may e.g. be carried out according to state-of-the-art photo-patterning processes and is not further described here.
  • the semifinished product resulting is denoted by 21 in the figure.
  • the perforation die 11 is pressed against an essentially flat support plate 13 for forming the microvias.
  • the method may also be adapted to be performed using two perforation dies for both opposing faces of the layer.
  • the support then is not a support plate but a further perforation tool having perforation tips, too.
  • the perforation tools may or may not correspond to each other, i.e. they may or may not have perforation tips to be placed at corresponding spots of the opposing surfaces.
  • the photo-patterning process can also be carried out before the perforation steps, as shown schematically in Figures 2a and 2b.
  • the perforation steps according to this embodiment of the method are performed analogously to the embodiment described with reference to Figures la through Id. It is, however, important that the pressure exerted on the material is reduced as soon as the distance between the perforation tool and the support plate reaches a minimum value corresponding to the thickness of the clad base material since otherwise the conductor tracks are crushed.
  • the semifinished product produced according to Fig. la-Id or Fig. 2a-2b, in the example described here may serve as core of a four layer build-up.
  • the top and the bottom cap layer are made in a way that is different from the forming of the core.
  • the copper layer 33 which is clad on one side of an uncured dielectric material 31 only, as represented in Figure 3a, is perforated by the MP process analogously to the core.
  • the copper clad side of the dielectric material in the following is called the top side, the opposing side will be named the back side.
  • a perforation tool 41 analogous to the perforation tool 11 is used.
  • a softer support plate 43 such as e.g. a hard plastic (any plastic is usable, e.g. an epoxy resin) is used.
  • solder material e.g. PbSn or a different tin alloy or any solder material known in the field may be used.
  • the copper 33 may penetrate the opposite surface, resulting in a small copper protrusion 3a.
  • the solder material is also subjected to some pressure. Therefore, solder material sticks to the protruding copper material even after the solder foil 45 is removed. This results in solder caps 45' and/or a partial intermixing of solder material with copper ( Figure 3c).
  • a sheet of solder material may also be placed on top of the structure, i.e. between the copper layer and the perforation die (not shown).
  • the resulting semifinished product is denoted by 51 in the figure.
  • a plasma cleaning step may be carried out on the back side of the product 51 in order to clean away possible pollutants and to remove some dielectric material around the copper protrusions.
  • the top and bottom layers 51, 51' are laminated to the core as shown in Figures 4a and 4b.
  • a 4-layer HDI build-up is formed.
  • the tinned copper protrusions are pressed towards correspondingly aligned copper pads of the semifinished product 21.
  • This laminating step may be carried out at room temperature or, depending on the layer materials, at an elevated temperature, so that the pre-tinned copper tips are soldered to the core, this soldering process being a second fusing step.
  • the polymer material is e.g. a Liquid Crystal Polymer (LCP)
  • the temperature may e.g. be between 200°C and 450°C.
  • Fig. 4a shows the semifinished products 21, 51, 51' and Fig. 4b depicts the lamination/soldering process.
  • the reference numeral 61 denotes two plates (which can be replaced by reels) between which the pressure for laminating is developed. Because of the elevated temperature, by which the soldering is made possible, the base material may, depending on its composition, may be cured simultaneously to the soldering process. Finally, the outer layers are structured in a conventional way by means of photochemical methods (Fig. 4b).
  • Fig. 6a shows an example of a part of such a device, namely a perforation tip 73 driven by a piezo activator 75.
  • Such piezo- activators 75 are built using piezo-ceramic materials, like lead- zirconium-titanium- oxides or other known piezoelectric materials.
  • a piezo perforation tool 71 comprising a piezo-activator 75, a perforation tip 73 and a mounting 77 for the piezo- activator 75 is shown very schematically. Piezo-activators allow a very fast actuation.
  • the perforation frequency can be as high as 20kHz, because no mechanical parts have to be moved. In addition, wear-out is also eliminated.
  • a multitude of piezo perforation tools 71 with a small diameter may be densely packed in an array resulting in a quasi-parallel process with a high throughput.
  • a piezo perforation tool mounted on a piezo activator may comprise several perforation tips formed by one miniature perforation die mounted on the piezo activator. The perforation tips of this one perforation tool are arranged close to each other and may, during a perforation step, all be positioned so that they cover the same contacting area or the same conductor path. All microvias formed in one perforation stage then serve the same contacting purpose, the method thus resulting in enhanced reliability by redundancy.
  • additional energy for the metal fusing process according to the invention may optionally be fed in.
  • a first example of such a feeding in of additional energy is a simple heating of the layered structure, as shown very schematically in Fig. lb by the dashed arrow 22.
  • a second example of a feeding of additional energy for the metal fusing process, namely for a cold welding process, is by means of ultrasonic energy.
  • a piezo activated perforation tip of the kind of the perforation tip shown in Fig. 6a can be provided with a high frequency voltage superposed on the piezo activating DC signal as shown schematically in Fig. 6b.
  • the voltage/time curve 81 of a piezo process without feeding of additional ultrasonic energy is compared to a voltage/time curve 83 of a piezo process where ultrasonic energy is fed in.
  • an ultrasonic modulation is superposed on the piezo actuating voltage.
  • the perforation tool and support schematically shown in the previously described figures are both supposed to be an essentially flat plate. It may, however, as well be that either or both of these items may be formed as a reel.
  • the substrate is e.g. a foil which is formed by a continuous perforation process and which is only then divided into individual interconnects.
  • essentially flat perforation tools and/or supports may be mounted on a reel, one reel may be combined with an essentially flat tool or support (e.g. formed as conveyor belt) etc.
  • a further modification of the above described method pertains to the (cold, hot or ultrasonic) welding process. It is equally well imaginable that instead of a pure welding process, welding may be combined with soldering or even be replaced by soldering. To this end, an appropriate solder material may be placed underneath the perforation tool of Figure 1. During the perforation step using a hard support plate, it intermixes with the copper material of the first conducting layer and also with the conducting material of the second conducting layer. As an alternative, solder material may directly be placed between the first conducting layer and the dielectric substrate layer before the perforation process, as a modification of the clad substrate of Figure la.
  • a device for carrying out the method described here can be arranged in various ways. It comprises means for holding a substrate. These may be formed as a plurality of reels between which the substrate is stretched and by which it is transported. They may also be configured to be some sort of a table , e.g. comprising suction means for creating a depression between a surface and the substrate. By these means the substrate may temporarily, during a perforation step, be attached to the table.
  • the device further has means for heating the substrate to a certain desired temperature, which means may or may not be integrated in the means for holding the substrate.
  • Crucial to the device is the perforation tool. This tool may e.g.
  • a perforation die possibly mounted on a reel or formed as a reel
  • a perforation tool may be configured to be or mounted on a reel.
  • the perforation tip or perforation tips are formed in the previously described manner, i.e., on a micrometer scale, they do not have any sharp points or edges.
  • the lateral position of the sample with respect to the perforation tool has to be determined. This can be done by some camera or may alternatively be provided by the means for holding the substrate.
  • the perforation tip penetration depth is approximately equal to the sum of the thicknesses of the substrate material an of the first conducting layer, i.e. that d ⁇ M+0.5* dc ⁇ (Penetration depth) ⁇ d ⁇ +dcLi+ dc 2 -
  • This can be achieved by choosing the tip length to be within this penetration depth range and by pressing the perforation die against the substrate.
  • the perforation tool is a piezo perforation tool
  • a control electronics then be programmed to then advance the perforation tip by exactly a pre-defined penetration depth determined according to the above formula.
  • a dielectric foil material coated on both sides with a Cu foil, which is adhering to the material because the surface is tacky (Fig. 8a) is loaded into an embossing equipment (Fig. 8b).
  • the dies shown above and below the foil in the Figure include not only the traces and other features but also the tips for the microvias.
  • the stack is pressed together and the copper is formed, where rounded tips are pressing into the copper layer, and is punched through, where the die has sharp edges, which cut through the copper (Figs. 8c and 8d).
  • the principle of cold welding is applied for the blind via.
  • the resulting product is shown in Fig. 8d.
  • top or bottom cap layer is shown in Figures 9a-9e.
  • the top and bottom cap layers are formed analogue to the core, but with a soft support plate, which results in copper protrusions, like shown for the previous embodiments.
  • the embossing is done, to form the copper pattern (Figs. 9a-9c).
  • the excess of copper is removed with a tacky tape and the outer layers are finished (Figs. 9d, 9e).
  • FIG. 10a- 10c An example of fixing a top and a bottom cap to the core is shown in Figures lOa-lOc.
  • the same tinning process as explained above can be applied to get a solderable surface.
  • Another method, shown in the Figures is to use a pre-coated Cu foil.
  • the foil is coated on the outer side with a thin layer of lower melting metal, which remains on the surface, throughout the whole process.
  • Core and pre-formed outer layers are then laminated together and the pre-coated copper surface on the core provides for the solder to get an inter-metallic connection between the copper protrusion and the corresponding pads on the core ( Figures 10a- 10c).
  • the copper surfaces may be plasma activated for the process to be (even better) bondable.
  • the lamination process shown in Figures 10a and 10b can be combined with the embossing process for the outer layers shown in Figure 9b. This technology combines a variety of advantages:

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'invention concerne un procédé de fabrication d'éléments de connexion électrique ou de produits semi-finis. A partir d'une couche de substrat diélectrique plastiquement déformable (1) dont les surfaces sont revêtues par une première et une seconde couche conductrice (3, 5), on effectue une microperforation combinée avec une opération de soudage ou de brasage. Pour ce faire, la couche de substrat diélectrique revêtue (1) est placée entre un outil de perforation (11) muni de pointes de perforation (11a) et un support (13), une pression étant appliquée entre cet outil de perforation (11) et ce support (13) de manière que les pointes de perforation (11a) de l'outil de perforation (11) pénètrent dans la matière du substrat (1). Les matières, la dimension et la forme des pointes de perforation (11a) sont choisies de façon à pouvoir déformer la matière conductrice (5) et pousser la matière du substrat diélectrique (1) sur le côté. La matière conductrice de la première couche conductrice (5) est alors déplacée et mise en contact avec la matière conductrice de la seconde couche conductrice (3) de manière à être connectée électriquement et mécaniquement à la matière conductrice de la seconde couche conductrice.
PCT/CH2001/000200 2000-03-31 2001-03-30 Procede et dispositif de fabrication d'elements de connexion electrique, et element de connexion resultant WO2001078475A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CH2001/000200 WO2001078475A1 (fr) 2000-03-31 2001-03-30 Procede et dispositif de fabrication d'elements de connexion electrique, et element de connexion resultant
AU2001242204A AU2001242204A1 (en) 2000-03-31 2001-03-30 Method and device for fabricating electrical connecting elements, and connectingelement

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US19337000P 2000-03-31 2000-03-31
US60/193,370 2000-03-31
PCT/CH2001/000200 WO2001078475A1 (fr) 2000-03-31 2001-03-30 Procede et dispositif de fabrication d'elements de connexion electrique, et element de connexion resultant

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012104023A1 (fr) * 2011-02-02 2012-08-09 Heraeus Materials Technology Gmbh & Co. Kg Procédé de fabrication d'un stratifié à mise en contact électrique conductrice

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2912746A (en) * 1955-10-10 1959-11-17 Erie Resistor Corp Method of making printed circuit panels
US3346950A (en) * 1965-06-16 1967-10-17 Ibm Method of making through-connections by controlled punctures
US4663840A (en) * 1984-12-11 1987-05-12 U.S. Philips Corporation Method of interconnecting conductors of different layers of a multilayer printed circuit board
DE19522338A1 (de) * 1995-06-20 1997-01-02 Fraunhofer Ges Forschung Verfahren zur Herstellung einer Durchkontaktierung sowie Chipträger und Chipträgeranordnung mit einer Durchkontaktierung
WO1999049708A1 (fr) * 1998-03-27 1999-09-30 Minnesota Mining And Manufacturing Company Procede de realisation de connexions electriques entre des conducteurs separes par un dielectrique
WO2000013062A1 (fr) * 1998-08-28 2000-03-09 Dyconex Patente Ag Procede de production de micro-orifices

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2912746A (en) * 1955-10-10 1959-11-17 Erie Resistor Corp Method of making printed circuit panels
US3346950A (en) * 1965-06-16 1967-10-17 Ibm Method of making through-connections by controlled punctures
US4663840A (en) * 1984-12-11 1987-05-12 U.S. Philips Corporation Method of interconnecting conductors of different layers of a multilayer printed circuit board
DE19522338A1 (de) * 1995-06-20 1997-01-02 Fraunhofer Ges Forschung Verfahren zur Herstellung einer Durchkontaktierung sowie Chipträger und Chipträgeranordnung mit einer Durchkontaktierung
WO1999049708A1 (fr) * 1998-03-27 1999-09-30 Minnesota Mining And Manufacturing Company Procede de realisation de connexions electriques entre des conducteurs separes par un dielectrique
WO2000013062A1 (fr) * 1998-08-28 2000-03-09 Dyconex Patente Ag Procede de production de micro-orifices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012104023A1 (fr) * 2011-02-02 2012-08-09 Heraeus Materials Technology Gmbh & Co. Kg Procédé de fabrication d'un stratifié à mise en contact électrique conductrice

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