WO2001075892A3 - Synchronous flash memory with concurrent write and read operation - Google Patents

Synchronous flash memory with concurrent write and read operation Download PDF

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Publication number
WO2001075892A3
WO2001075892A3 PCT/US2001/010375 US0110375W WO0175892A3 WO 2001075892 A3 WO2001075892 A3 WO 2001075892A3 US 0110375 W US0110375 W US 0110375W WO 0175892 A3 WO0175892 A3 WO 0175892A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
data
write
flash memory
array
Prior art date
Application number
PCT/US2001/010375
Other languages
English (en)
Other versions
WO2001075892A2 (fr
Inventor
Frankie F Roohparvar
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/628,184 external-priority patent/US6851026B1/en
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to DE10196002T priority Critical patent/DE10196002B3/de
Priority to AU2001251169A priority patent/AU2001251169A1/en
Priority to JP2001573484A priority patent/JP3779209B2/ja
Publication of WO2001075892A2 publication Critical patent/WO2001075892A2/fr
Publication of WO2001075892A3 publication Critical patent/WO2001075892A3/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2281—Timing of a read operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/229—Timing of a write operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/22—Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously

Landscapes

  • Dram (AREA)
  • Read Only Memory (AREA)

Abstract

A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. A write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections. The memory can write data to one location, such as a memory array block, while data is read from a second location, such as a second memory array block. The write and read operations are performed on a common addressable row of the array blocks.
PCT/US2001/010375 2000-03-30 2001-03-30 Synchronous flash memory with concurrent write and read operation WO2001075892A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE10196002T DE10196002B3 (de) 2000-03-30 2001-03-30 Synchroner nichtflüchtiger Speicher und Verfahren zum Betrieb eines synchronen nichtflüchtigen Speichers
AU2001251169A AU2001251169A1 (en) 2000-03-30 2001-03-30 Synchronous flash memory with concurrent write and read operation
JP2001573484A JP3779209B2 (ja) 2000-03-30 2001-03-30 読み出し処理および書き込み処理を並列に実行する機能を有するシンクロナスフラッシュメモリ

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US19350600P 2000-03-30 2000-03-30
US60/193,506 2000-03-30
US09/628,184 US6851026B1 (en) 2000-07-28 2000-07-28 Synchronous flash memory with concurrent write and read operation
US09/628,184 2000-07-28

Publications (2)

Publication Number Publication Date
WO2001075892A2 WO2001075892A2 (fr) 2001-10-11
WO2001075892A3 true WO2001075892A3 (fr) 2002-05-23

Family

ID=26889068

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/010375 WO2001075892A2 (fr) 2000-03-30 2001-03-30 Synchronous flash memory with concurrent write and read operation

Country Status (5)

Country Link
JP (1) JP3779209B2 (fr)
KR (1) KR100438634B1 (fr)
AU (1) AU2001251169A1 (fr)
DE (1) DE10196002B3 (fr)
WO (1) WO2001075892A2 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101002276B (zh) 2004-07-29 2010-09-01 斯班逊有限公司 在非易失性存储装置中信息设定之方法及设备
WO2007023544A1 (fr) * 2005-08-25 2007-03-01 Spansion Llc Dispositif de mémoire, procédé de commande de dispositif de mémoire et procédé de commande d'appareil de commande de mémoire
JP2007164938A (ja) 2005-12-16 2007-06-28 Matsushita Electric Ind Co Ltd 半導体記憶装置
US7639540B2 (en) 2007-02-16 2009-12-29 Mosaid Technologies Incorporated Non-volatile semiconductor memory having multiple external power supplies
KR101293226B1 (ko) 2011-06-30 2013-08-05 (주)아토솔루션 비휘발성 메모리 소자, 전자제어 시스템, 및 비휘발성 메모리 소자의 동작방법
US11269779B2 (en) 2020-05-27 2022-03-08 Microsoft Technology Licensing, Llc Memory system with a predictable read latency from media with a long write latency
DE102021107044A1 (de) 2021-03-10 2022-09-15 Elmos Semiconductor Se Sicherheitsrelevantes Rechnersystems mit einem Datenspeicher und einem Datenspeicher
CN113343319B (zh) * 2021-06-29 2024-04-02 珠海一微半导体股份有限公司 一种flash的类型识别方法及类型识别系统

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5602781A (en) * 1994-03-17 1997-02-11 Hitachi, Inc. Memory device having a plurality of sets of data buffers
US5666322A (en) * 1995-09-21 1997-09-09 Nec Electronics, Inc. Phase-locked loop timing controller in an integrated circuit memory
US5959887A (en) * 1997-07-09 1999-09-28 Fujitsu Limited Electrically erasable programmable nonvolatile semiconductor memory having dual operation function
US6011751A (en) * 1997-12-25 2000-01-04 Kabushiki Kaisha Toshiba Sychronous semiconductor memory device with burst address counter operating under linear/interleave mode of single data rate/double data rate scheme

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5245572A (en) * 1991-07-30 1993-09-14 Intel Corporation Floating gate nonvolatile memory with reading while writing capability

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5602781A (en) * 1994-03-17 1997-02-11 Hitachi, Inc. Memory device having a plurality of sets of data buffers
US5666322A (en) * 1995-09-21 1997-09-09 Nec Electronics, Inc. Phase-locked loop timing controller in an integrated circuit memory
US5959887A (en) * 1997-07-09 1999-09-28 Fujitsu Limited Electrically erasable programmable nonvolatile semiconductor memory having dual operation function
US6011751A (en) * 1997-12-25 2000-01-04 Kabushiki Kaisha Toshiba Sychronous semiconductor memory device with burst address counter operating under linear/interleave mode of single data rate/double data rate scheme

Also Published As

Publication number Publication date
KR100438634B1 (ko) 2004-07-02
DE10196002B3 (de) 2012-11-08
WO2001075892A2 (fr) 2001-10-11
DE10196002T1 (de) 2003-03-13
JP2003529880A (ja) 2003-10-07
KR20020086746A (ko) 2002-11-18
AU2001251169A1 (en) 2001-10-15
JP3779209B2 (ja) 2006-05-24

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