WO2001067271A1 - Dispositif de traitement d'informations - Google Patents

Dispositif de traitement d'informations Download PDF

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Publication number
WO2001067271A1
WO2001067271A1 PCT/JP2000/001475 JP0001475W WO0167271A1 WO 2001067271 A1 WO2001067271 A1 WO 2001067271A1 JP 0001475 W JP0001475 W JP 0001475W WO 0167271 A1 WO0167271 A1 WO 0167271A1
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WO
WIPO (PCT)
Prior art keywords
bus
cpu
data
memory
storage device
Prior art date
Application number
PCT/JP2000/001475
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English (en)
Japanese (ja)
Inventor
Hiroshi Hatae
Hiromi Watanabe
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP2000/001475 priority Critical patent/WO2001067271A1/fr
Publication of WO2001067271A1 publication Critical patent/WO2001067271A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor

Definitions

  • the present invention relates to an information processing apparatus, and in particular, relates to two CPUs (central processing units) having a master-slave relationship, specifically, a host CPU and a CPU in an accelerator.
  • the present invention relates to an information processing device having two CPUs.
  • this mobile terminal is often composed of a host CPU as a master, and an accelerator as a slave that assists the processing of the host CPU.
  • the audio part is processed by the host CPU, and the image part is left to a dedicated LSI (axelator) that processes MPEG4.
  • this portable terminal is required to be able to perform signal processing of a plurality of standards with low power consumption.
  • the LSI used inside the device is used from a combination of the conventional host CPU and an accelerator configured with hardware to a combination of the host CPU and an accelerator that has a built-in processor and operates with software. It is possible.
  • the processor incorporated in the accelerator is referred to as an accelerator CPU.
  • the processing content can be changed by changing the program transferred to the accelerator.
  • the first CPU which acts as the host CPU
  • the address bus (AB) and data bus (DB) connected to the first CPU and accelerator
  • the accelerator CPU AC PU
  • the accelerator CPU Internal address bus (INTAB) and internal data bus (INTDB)
  • SEL1 first selector
  • SEL 2 second selector for selectively connecting each bus to memory (RAM) (SEL 2).
  • the first selector and the second selector are switched to the bus side of the first CPU, and the program of the accelerator CPU is transferred to the memory.
  • the selector is switched to the bus of the accelerator CPU (AC PU), the program stored in the memory is read, and the accelerator CPU executes the processing.
  • the CPU in the accelerator connected to the CPU as the master is often composed of about five pipelines.
  • the contents of the five stages are instruction fetch, instruction decode, execution, memory access, and write-back.
  • contention occurs because both use the address bus and data bus of the accelerator CPU. For this reason, there is a problem that the performance of the information processing device, that is, the processing speed is reduced, because measures are usually taken to delay one of the stages by one clock.
  • the related related patent application publications include Japanese Patent Application Laid-Open Nos. Hei 5-94305, Hei 5-233 191, Hei 6-19704 and Hei 10-254 776. There are seven. However, none of the publications discloses or suggests the problems in the above-described configuration, and it can be said that there is no publication showing the configuration of the present invention shown in this specification.
  • an object of the present invention is to provide an information processing apparatus having a CPU serving as a master and a CPU serving as a slave.
  • An object of the present invention is to provide an information processing apparatus which prevents contention for access and does not degrade performance.
  • a further object of the invention is of the Neumann type.
  • An object of the present invention is to provide a high-performance information processing device by using a PU and a harbor type CPU.
  • the first central processing unit includes an instruction. And the data are output to the storage device via the same bus, and the second central processing unit accesses the storage device via the instruction bus and the data bus.
  • the first central processing unit a first bus connected to the first central processing unit to transfer instructions and data, a second central processing unit, A second bus connected to the central processing unit for transferring instructions; a third bus connected to the second central processing unit for transferring data; a storage device; a first bus and a second bus A first selection circuit connected to the first bus or the second bus and connected to the storage device by selecting the first bus or the second bus; and a first bus or the third bus connected to the first bus and the third bus.
  • a second selection circuit for selecting a bus and connecting it to the storage device.
  • the invention according to claim 10 is characterized in that the first central processing unit, a first bus connected to the first central processing unit to transfer instructions and data, a second central processing unit, A second bus connected to the second central processing unit; a third bus connected to the second central processing unit; a first memory port and a second memory.
  • a storage device having a report, and a first selection circuit connected to the first bus and the second bus, for selecting the first bus or the second bus and connecting to the first memory port of the storage device
  • the third bus is connected to a second memory port of the storage device.
  • a first central processing unit having a Neumann architecture
  • a second central processing unit having a Harvard architecture for processing a program transferred by the first central processing unit. It is like that.
  • the first central processing unit is connected to the storage device via the first bus
  • the second central processing unit is connected to the second central processing unit. It is connected to a storage device via a bus and a third bus.
  • the storage device is a dual port memory having a first memory port and a second memory port.
  • the storage device has a first storage device for storing instructions and a second storage device for storing data.
  • the information processing apparatus further includes: a first selection circuit that selectively connects the first bus and the second bus to the first storage device; and a first bus and a third bus. And a second selection circuit connected to the second storage device.
  • the accelerator connected to the host CPU can use the processor of the herb-and-door architecture, so that the processing content can be made programmable. Further, since instruction fetch and memory access can be operated in parallel, a high-speed information processing device can be realized.
  • FIG. 1 is a configuration diagram of the information processing apparatus according to the first embodiment.
  • FIG. 2 is a detailed configuration diagram of the control block shown in FIG.
  • FIG. 3 is a detailed configuration diagram of the logic block shown in FIG.
  • FIG. 4 is a configuration diagram of the information processing apparatus according to the second embodiment.
  • FIG. 5 is a diagram showing a first allocation of instruction and data areas.
  • FIG. 6 is a diagram showing a second allocation of instruction and data areas.
  • FIG. 7 is a configuration diagram of the information processing device according to the third embodiment.
  • FIG. 8 is a configuration diagram of the information processing apparatus according to the fourth embodiment.
  • FIG. 9 is a configuration diagram according to the information processing apparatus of the fifth embodiment.
  • FIG. 10 is a configuration diagram of a conventional information processing apparatus. BEST MODE FOR CARRYING OUT THE INVENTION
  • the information processing device shown in the present embodiment is used in a portable information terminal, although not particularly limited. It consists of a host CPU acting as a master and an accelerator acting as a slave connected to it.
  • the host CPU may perform voice processing
  • the accelerator may process MPEG4.
  • CPU 1 is a first CPU as a host CPU
  • CPU 2 is a second CPU as a CPU in an accelerator (AC).
  • the CPU of this embodiment performs a five-stage pipeline process including instruction fetch, instruction decode, execution, memory access, and write-back. What has been described above is not limited to the first embodiment, but can be applied to the embodiments described later.
  • CT L controls the second CPU, CPU 2, A control block for controlling a first selector (SEL 1), a second selector (SEL 2), a third selector (SEL 3), and a fourth selector (SEL 4) described later. It is.
  • the control block (CTL) is connected to the second CPU, CPU 2 and the first to fourth selectors (SEL1, SEL2, SEL3, SEL4) by signal lines.
  • the control signal for starting the second CPU (CPU 2) and the control signal to each selector (SEL1, SEL2, SEL3, SEL4) are transmitted via the signal line.
  • the first CPU (CPU 1) is connected to the address bus (AB) and the data bus (DB).
  • the second CPU (CPU 2) is connected to the instruction address bus (IAB), the instruction data bus (IDB), the data address bus (DAB), and the data bus for data (DDB).
  • the first selector (SEL 1) has an address bus (AB) connected to the first CPU (CPU 1) and an instruction address bus (I PU) connected to the second CPU (CPU 2). AB).
  • the second selector (SEL 2) switches between the data bus (DB) connected to the first CPU (CPU 1) and the instruction data bus (IDB) connected to the second CPU. is there.
  • the third selector (SEL3) has an address bus (AB) connected to the first CPU (CPU1) and a data address bus (DAB) connected to the second CPU (CPU2). ) This is a selector that switches between and.
  • the fourth selector (SEL 4) has a data bus (DB) connected to the first CPU (CPU 1) and a data bus (DDB) connected to the second CPU (CPU 2). ).
  • the first to fourth selectors are configured to connect any of the connected buses to the memory by the control signal, but there is a problem even if there is a state where none of the buses is connected to the memory. There is no.
  • the instruction memory (IM) is a memory for storing instructions of the second CPU (CPU 2).
  • An address terminal is connected to an address bus (AB) or an instruction address bus (IAB) via a first selector (SEL 1), and a data terminal is connected to a second selector (SEL 2).
  • Is connected to a data bus (DB) or an instruction data bus (IDB).
  • the data storage device (DM) is a storage device for instructions for storing data.
  • the address terminal is connected to an address bus (AB) or a data address bus (DAB) via a third selector (SEL3).
  • the data terminal is connected to a data bus (DB) or a data bus for data (DDB) via a fourth selector (SEL 4).
  • the instruction storage device (IM) and the data storage device of this embodiment are RAM (random access memory), but they are not part of the essence of the present invention. There is no particular problem even with a non-volatile memory.
  • the data address bus (DAB) and data data bus (DDB) connected to the second CPU are connected to the logic block (BLK) built in the accelerator (AC).
  • the configuration of this embodiment is characterized in that the second CPU has a Harvard architecture in which an instruction bus (IAB, IDB) and a data bus (DAB, DDB) are separated.
  • the first CPU has a so-called Neumann architecture in which an instruction bus and a data bus are not separated. That is, in the above description, the instruction address, the data address, and the data are transferred to the address bus (AB), and the instruction data and the data data are transferred to the data bus (DB).
  • the terms Harvard architecture, Harvard type, and Neumann architecture or Neumann type are used, but other names may be used without departing from the spirit of this specification. No problem.
  • the first CPU and the second CPU shown in the first embodiment take the memory efficiency into consideration when storing instructions into memory. 475
  • control block (CTL) shown in FIG. 1 will be described in detail.
  • the control block has therein a control circuit (CTLC) connected to an address bus (AB) connected to the first CPU and a data bus (DB).
  • CT LC decodes the address supplied from the address bus (AB), and if the supplied address indicates the address of the control register (CTLR), the control register (CTLR) CT LR) is written.
  • the control signal for activating the second CPU (CPU 2) is transmitted via the signal line to the second CPU.
  • a control signal is supplied to the first to fourth selectors via signal lines according to the value of the first bit (Ibit) of the control register (CTLR).
  • FIG. 3 describes the logical block (BLK) shown in FIG. 1 in detail.
  • the logical block (BLK) is a block configured with a hardware card, although not particularly limited. In this embodiment, as an example, DC The block that performs T (discretecosinetransform) processing is described.
  • the logic block (BLK) has a control circuit (BLKC) connected to a data address bus (DAB) connected to the second CPU and a data bus for data (DDB).
  • DDB data bus for data
  • the control circuit (BLKC) in the logic block decodes the address supplied via the data address bus (DAB), and buffers (BLKB) and registers (BLKR) according to the supplied address. Are controlled.
  • the data to be processed is written from the data bus for data (DDB) to the buffer (B LKB), and then "1" is written to the start bit of the register (B LKR). (DCTU) starts operation and writes the conversion result back to the buffer (B LKB).
  • the second selector (SEL 2) and the fourth selector (SEL 4) are connected to the data connected to the first CPU.
  • Select the bus (DB) and the instruction storage (IM) and data storage (DM) are the data bus (DB) Connected. That is, when the signal line for controlling the first to fourth selectors is "L”, the instruction storage device and the data storage device are connected to the first CPU.
  • the first CPU (CPU 1) is connected to the address bus (AB), the first selector (SEL 1), and the data bus (DB).
  • the instruction for the second C PU (C PU 2) was transferred to the instruction Symbol ⁇ device (IM), further, the address bus (AB) a third selector
  • the data for the second CPU (CPU2) is transferred to the data storage device (DM) via the data bus (DB) and the fourth selector (SEL4).
  • the control circuit (CT LC) in the control block (CTL) writes "1" to the first bit (1 bit) of the control register (CT LR).
  • the control signals for controlling the respective selectors become “H”, and the first selector (SEL 1) sets the instruction address bus (I 2) connected to the second CPU (CPU 2).
  • AB) is connected to the address terminal of the instruction storage device (IM), and the second selector (SEL 2) is connected to the instruction data bus connected to the second CPU (CPU 2).
  • the third selector (SEL3) connects the data address bus (DAB) connected to the second CPU (CPU2) to the address terminal of the data storage device (DM), and the fourth selector (SEL3).
  • Selector (SEL 4) connects the data bus (DDB) connected to the second CPU (CPU 2) to the data terminal of the data storage device (DM).
  • CT LR control register
  • the control signal transmitted through the signal line connected to the second CPU (CPU 2) becomes “H”, and the second CPU is activated.
  • the second CPU (CPU 2) The processing is started using the instructions stored in the storage device (IM) and the data stored in the data storage device (DM).
  • the central processing unit in the accelerator (AC) connected to the first CPU performing host-like operation (the second processing in the present embodiment) It is possible to use a Harvard architecture CPU in which the instruction bus and the data bus are separated for the CPU. Therefore, when the second CPU in the accelerator performs memory access, it is possible to access data and instructions on different buses, which may occur during pipeline processing. High contention between buses does not occur, and there is no need to delay the pipeline stage for processing, thereby enabling higher performance operation without lowering the processing speed.
  • DPM dual port memory
  • IM instruction storage device
  • DM data storage device
  • the first CPU (CPU 1) is a host CPU
  • the second CPU (CPU 2) is a CPU provided in an accelerator (AC).
  • the control block (CTL) controls the CPU 2 which is the second PU, and controls the first selector (SEL 1) and the second selector (SEL 2) described later. Do.
  • the control block (CTL) is connected to the second CPU, CPU 2 and the first selector (SEL 1) and the second selector (SEL 2) by signal lines, and via those signal lines.
  • the first CPU (CPU 1) is connected to the address bus (AB) and the data bus (DB).
  • the second CPU (CPU 2) is connected to the instruction address bus (IAB), the instruction data bus (IDB), the data address bus (DAB), and the data bus for data (DDB).
  • the first selector (SEL 1) includes an address bus (AB) connected to the first CPU (CPU 1) and an instruction address bus (AB) connected to the second CPU (CPU 2). I AB).
  • the second selector (SEL2) disconnects the data bus (DB) connected to the first CPU (CPU1) from the instruction data bus (IDB) connected to the second CPU. This is a selector for switching.
  • the dual port memory has a first memory port (P 1) and a second memory port (P 1), each of which comprises an address terminal for inputting an address and a data terminal for inputting and outputting data.
  • P 2) is a memory that has two independent memory locations, and since it is conventionally known, its internal description is omitted.
  • the dual-port memory (DPM) is a storage device for instructions of the second CPU (CPU 2) and instructions for storing data processed by the second CPU.
  • the address terminal of the first port (P1) of the dual port memory (DPM) is connected to the address bus (AB) or the instruction address bus (IAB) via the first selector (SEL1)
  • the data terminal is connected to a data bus (DB) or an instruction data bus (I DB) via a second selector (SEL 2).
  • the address terminal of the second port (P2) of the dual-port memory is connected to the data address bus (DAB), and the data terminal is connected to the data bus for data (DDB).
  • the internal configuration of the control block (CTL) and logical block (BLK) is not particularly limited, but is the same as the configuration shown in FIGS. 2 and 3. Further, the configuration of the second embodiment 75
  • the second CPU is a Harvard architecture in which the instruction bus (IAB, IDB) and the data bus (DAB, DDB) are separated.
  • the first CPU has a so-called Neumann architecture in which the instruction bus and the data bus are not separated. That is, in the above description, the instruction address, the data address, and the power are transferred to the address bus (AB); and the instruction data and the data data are transferred to the data bus (DB).
  • the first selector (SEL1) connects the address bus (AB) connected to the first CPU (CPU1) to the dual-port memory (D PM) is connected to the address terminal of the first port (P 1)
  • the second selector (SEL 2) connects the data bus (DB) connected to the first CPU to the dual port memory. Connected to the data terminal of the first port (P 1).
  • the first CPU (CPU 1) dual-ports the instruction and data for the second CPU (CPU 2) in the accelerator (AC) or a program in which the instruction and data are mixed. Via the first port of the remote memory.
  • the second CPU is connected to the first port (P1) of the dual port memory (DPM), the instruction address bus (IAB), and the instruction data bus (IDB). Starts the fetch operation of the instruction executed by the second CPU stored in the CPU.
  • the dual-port memory can access the same physical memory space in parallel from the two ports (Pl, P2), so the instruction buses (I AB, I DB ) And data buses (DAB, DDB) can operate in parallel.
  • the second CPU (CPU 2) in the accelerator (AC) has an instruction area and a data area to be accessed in the same physical space, so that the second CPU has a Harvard architecture. Even if you have one, it is possible to use a program in which instructions and data are mixed. Furthermore, the transfer of the program from the first CPU (CPU 1), which is the host CPU, can be performed at one time. Further, two selectors, which were required in the first embodiment, are now required. As described above, in the second embodiment, the hardware scale can be reduced as compared with the first embodiment, and the performance can be further improved. Also, because the same physical space can be used for instructions and data, the entire RAM space is 40% for the instruction area (IR) and 60% for the data area (DR) as shown in Figure 5.
  • the selectors (SEL1, SEL2) are connected between the buses (AB, DB) connected to the first CPU and the instruction buses (IAB, IDB) of the second CPU. ), But the bus (AB, AB) connected to the first CPU and the data bus (DAB, DD B).
  • the selector is provided between one bus of the second CPU and the bus connected to the first CPU. Is also good.
  • the configuration is the same as that of the first embodiment in which the instruction storage device and the data storage device are replaced with one dual-port memory.
  • the storage device in the accelerator (AC) has three memory ports including an address terminal for inputting an address and a data terminal for inputting and outputting data. It is characterized by using triple port memory (TPM). Although this tri-port memory is sometimes called a three-port memory, the same RAM space is allocated to the first memory port (P 1), the second memory port (P 2), and the third memory port (P It is a memory that can be accessed in parallel by the three ports in P3).
  • the first CPU (CPU 1) that performs host-like operation and the address bus (AB) connected to the first CPU are used.
  • DB data bus
  • the accelerator radiator (AC) connected via these buses is connected to the second CPU (CPU 2) and the address bus (AB) and the data bus (DB).
  • the control block (CTL), the instruction address bus (IAB) and the instruction data bus (IDB) connected to the second CPU, and the second CPU and the logic block ( A data address bus (DAB) and a data bus for data (DDB) connected to the BLK) and the triple port memory (TPM) described above are formed.
  • the triple-port memory (TPM) of the third embodiment has three memory ports, so that each bus can be connected.
  • the first memory port (P 1) of the triple port memory includes: The address bus (AB) connected to the first CPU and the data bus (DB) are connected, and the second memory port (P2) has the instruction address connected to the second CPU.
  • the bus (IAB) is connected to the instruction data bus (IDB)
  • the third memory port has a data address bus (DAB) and a data bus (DDB) connected to the second CPU. And are connected. Therefore, there is no need to provide a selector that was required in the first and second embodiments. That is, the control block (CTL) does not require the signal lines connected to the control block and the selector described in the first and second embodiments. Further, the setting of the first bit (1 bit) of the control register for controlling the selector described in FIG. 2 is not required.
  • the configuration of the logic block (BLK) is not particularly limited, but there is no problem even if the configuration is the same as that shown in FIG.
  • the host CPU 2 transfers a program in which instructions and data for the accelerator CPU 26 are mixed to the triple port RAM 50.
  • the accelerator CPU 26 is activated, and the accelerator CPU 26 fetches the instruction of the triple port RAM 50 and starts the operation.
  • the dress bus (IAB) and the instruction data bus (IDB) are the first memory port (PPM) of the triple port memory (TPM), respectively.
  • the fourth embodiment is a modification of the second embodiment using the dual port memory described above.
  • the fifth selector (SEL5) for switching between the lower bit and the upper bit is provided on the instruction data bus of the second CPU (CPU2) in the accelerator (AC). It is unique.
  • the second CPU (CPU 2) of the fourth embodiment has an instruction length of 16 bits and an operation bit length of 32 bits.
  • the bit width of the dual port memory (DPM) is 32 bits. Therefore, the second CPU accesses the dual-port memory with the instruction bus (IAB, IDB) and the data bus (DAB, DDB) with 32 bits.
  • the fifth selector (SEL5) receives the information of the instruction address bus (IAB) output from the second CPU, and converts the 32-bit instruction data output from the dual port memory (DPM). Select the required upper 16 bits or lower 16 bits and output it to the second CPU.
  • the dual-port RAM can be used even when the bit length of the instruction is different from the bit length of the data.
  • FIG. 9 illustrates a fifth embodiment.
  • the fifth embodiment is also a modification of the second embodiment using the dual port memory described above.
  • This embodiment In 5 the data bus of the second CPU (CPU 2) in the accelerator (AC) has a sixth selector (SEL 6) that switches between lower and upper bits. There is a feature.
  • the second CPU (CPU 2) of the fifth embodiment has an instruction length of 16 bits and an operation bit length of 32 bits.
  • the bit width of the dual port memory (DPM) is 32 bits. For this reason, the second CPU accesses the dual-port memory with the instruction bus (IAB, IDB) and the data bus (DAB, DDB) with 32 bits.
  • the fifth selector (SEL 5) receives the address information output from the second CPU and selects the necessary upper or lower 16 bits from the accessed 32 bits. Output.
  • the dual-port RAM can be used.
  • the instruction storage device (IM) and the data storage device (DM) of the first embodiment, the dual-port memory (DPM) of the second, fourth, and fifth embodiments, and the triple-port memory (TPM) of the third embodiment PM) may be composed of flash memory. As a result, data can be retained even when the power supply is stopped, so that when the power supply is restarted, it is possible to reproduce the same state as at the end of the previous time.

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  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

L'invention concerne des moyens servant à améliorer les performances ou la vitesse de traitement d'un processeur d'informations comprenant une unité centrale de traitement hôte, en tant que maître, et un accélérateur, en tant qu'esclave connecté au maître. L'unité hôte possède une architecture de Neumann et l'unité de l'accélérateur possède une architecture de Harvard. En outre, une mémoire partagée par les deux unités de traitement comprend un sélecteur, lequel connecte de façon sélective la mémoire avec les bus associés à chaque unité de traitement. Cette mémoire partagée est composée d'une mémoire à deux ports. Cette configuration augmente la vitesse de traitement du processeur d'informations, lequel comprend une unité de traitement maître et une unité de traitement esclave.
PCT/JP2000/001475 2000-03-10 2000-03-10 Dispositif de traitement d'informations WO2001067271A1 (fr)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005096169A1 (fr) * 2004-04-01 2005-10-13 Matsushita Electric Industrial Co., Ltd. Dispositif à semi-conducteur et téléphone cellulaire utilisant celui-ci
JP2005346672A (ja) * 2004-06-07 2005-12-15 Canon Inc メモリ制御方法、メモリ制御システム、プログラム及び記憶媒体
US9373372B2 (en) 2013-03-18 2016-06-21 Fujitsu Limited Register file device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01234962A (ja) * 1988-03-16 1989-09-20 Nec Corp バス制御方式
US4912636A (en) * 1987-03-13 1990-03-27 Magar Surendar S Data processing device with multiple on chip memory buses
JPH05233519A (ja) * 1992-02-19 1993-09-10 Ricoh Co Ltd メモリ増設方法
JPH10254767A (ja) * 1997-03-10 1998-09-25 Sharp Corp メモリ制御装置及び該メモリ制御装置によるメモリシステム

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4912636A (en) * 1987-03-13 1990-03-27 Magar Surendar S Data processing device with multiple on chip memory buses
JPH01234962A (ja) * 1988-03-16 1989-09-20 Nec Corp バス制御方式
JPH05233519A (ja) * 1992-02-19 1993-09-10 Ricoh Co Ltd メモリ増設方法
JPH10254767A (ja) * 1997-03-10 1998-09-25 Sharp Corp メモリ制御装置及び該メモリ制御装置によるメモリシステム

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005096169A1 (fr) * 2004-04-01 2005-10-13 Matsushita Electric Industrial Co., Ltd. Dispositif à semi-conducteur et téléphone cellulaire utilisant celui-ci
JP2005346672A (ja) * 2004-06-07 2005-12-15 Canon Inc メモリ制御方法、メモリ制御システム、プログラム及び記憶媒体
US9373372B2 (en) 2013-03-18 2016-06-21 Fujitsu Limited Register file device

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