WO2001038997A1 - Module informatique et carte-mere - Google Patents

Module informatique et carte-mere Download PDF

Info

Publication number
WO2001038997A1
WO2001038997A1 PCT/GB1999/003946 GB9903946W WO0138997A1 WO 2001038997 A1 WO2001038997 A1 WO 2001038997A1 GB 9903946 W GB9903946 W GB 9903946W WO 0138997 A1 WO0138997 A1 WO 0138997A1
Authority
WO
WIPO (PCT)
Prior art keywords
motherboard
computer module
cpu
bus
memory
Prior art date
Application number
PCT/GB1999/003946
Other languages
English (en)
Inventor
Kevin Paul Heawood
Neil Thompson
Original Assignee
Nmi Electronics Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nmi Electronics Limited filed Critical Nmi Electronics Limited
Priority to EP99956229A priority Critical patent/EP1232443A1/fr
Priority to AU12872/00A priority patent/AU1287200A/en
Priority to CA002392503A priority patent/CA2392503A1/fr
Priority to PCT/GB1999/003946 priority patent/WO2001038997A1/fr
Publication of WO2001038997A1 publication Critical patent/WO2001038997A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling

Definitions

  • the present invention relates to a computer module (particularly but not exclusively when in the form of a daughterboard) , to a motherboard for such a daughterboard and to a control arrangement comprising the daughterboard and motherboard in combination.
  • the daughterboard is a single-board computer (SBC) in which all the essential computer components required to perform the desired computer functions are substantially contained on a single printed wiring module or board.
  • SBC single-board computer
  • the heart of such a machine is one or more central processing units (CPUs) or micro processor units (MPUs).
  • the CPU controls the operation of the machine and performs various types of input/output (I/O) operations, calculations and logical operations in accordance with computer program instructions. In order to do so, the CPU is generally supported by memory and I/O circuits on the printed wiring module.
  • Single-board computers are often adapted for specific functions. For example, they may be used as controllers for other machines or systems, and SBCs are often designed with this flexibility in mind.
  • Included in the memory is a portion which is typically but not necessarily read-only, and which contains a set of customised program instructions directing the CPU to perform the specific task for which the SBC is adapted.
  • the flexibility afforded by reprogramming may not be adequate to adapt current SBCs to all the tasks to which they may otherwise be successfully applied because for sufficiently different tasks, different CPUs, memory types and sizes and support logic devices may be desirable.
  • US 5898846 discloses a computer module comprising a CPU or microprocessor coupled to local memory, the module further comprising bus connector means for connecting the module to an external bus.
  • An object of the present invention is to provide a computer module that is not subject to this requirement.
  • the invention provides a computer module characterised by electronic control means arranged to modify and/or re-route inputs and/or outputs of the CPU or microprocessor to conductors of the connector means in accordance with stored configuration information.
  • the inputs or outputs could be inverted or their timing could be altered.
  • the invention provides a motherboard for such a computer module, the motherboard having a bus for connection to said bus connector means and means for controlling such an electronic control means.
  • said means for controlling the electronic control means comprises an electronic configuration device having at least one output line connected to said bus and a memory containing a stored configuration program, the configuration device or electronic control means being arranged to be controlled by the configuration program.
  • the motherboard has further circuitry connected to input or output ports on the motherboard for interfacing with external circuitry, said further circuitry having one or more control inputs or outputs coupled to said bus.
  • the invention provides a control arrangement comprising a daughterboard in accordance with the first mentioned aspect connected to a motherboard in accordance with the second mentioned aspect, the electronic controlling means being arranged to configure the bus connections of the daughterboard to match the bus of the motherboard.
  • an interconnect system for a computer, the computer including a CPU sub-system (CPU, memory, support logic and interconnections) and the computer further including application [specific] input/ output connections.
  • the interconnect system comprises a programmable logic circuit having a first set of input/ output lines connected to the CPU sub-system and a second set of input/ output lines connected to the application [specific] input/ output connections; and a memory containing a configuration program including instructions to the programmable logic circuit to map the lines of the CPU sub-system to the application [specific] input/ output connections and connected such that it programs the programmable logic circuit each time a predetermined event occurs.
  • a CPU-based daughtercard including a CPU sub-system, being electrically connected to a programmable logic circuit and the programmable logic circuit also being electrically connected to a connector on the daughtercard.
  • the CPU-based daughtercard comprises a daughtercard connector adapted to mate with the connector included on an application motherboard; a CPU having input/ output lines electrically connected to the programmable logic circuit, CPU sub-system and daughtercard connector; memory containing a configuration program for the programmable logic circuit; and a programmable logic circuit having lines electrically connected to the daughtercard connector and lines connected to a CPU sub-system and memory bus wherein loading the configuration program configures the programmable logic circuit to map between the CPU sub-system and memory bus and the daughtercard connector input/output lines.
  • a CPU-based daughtercard including a CPU sub-system having a connector electrically connected to a programmable logic circuit, the programmable logic circuit further being electrically connected to a connector on the daughtercard, capable of being connected to an application motherboard.
  • the motherboard comprises a connector adapted to mate with the daughtercard connector; and various circuits to allow the motherboard to perform specific application functions.
  • Such circuits may include peripherals, memory and connectors.
  • the application motherboard contains configuration hardware to allow the CPU-based daughtercard to self configure; wherein reading the configuration hardware allows the CPU-based daughtercard to configure the programmable logic circuit to map between the CPU-based daughtercard input/ output lines and application motherboard.
  • a CPU interconnect system for a computer application, the computer including a CPU-based daughtercard having input/ output lines disposed on a first module and the computer further including application [specific] input/ output connections disposed on a second module.
  • the interconnect system may include elements for connecting the CPU sub-system to the application [specific] input/ output connections in accordance with a mapping not fixed in the elements for connecting, disposed on the first module; and elements for loading the mapping in to the elements for connecting, the elements for loading operative upon the occurrence of a predetermined event.
  • the elements for connecting may include such conductors and connectors or sockets as may be required to electrically connect signals from their sources to their destinations.
  • the elements for holding or memory may be any of a variety of types of non-volatile memory, such as read-only memory (ROM), electrically alterable readonly memory (EAROM) such as Flash or EEPROM, non -volatile random access memory (NVRAM) or battery backed up random access memory.
  • the CPU may further be one of a plurality of CPU types.
  • the CPU types supported may include, but not limited to processors of various data and address but widths made by Intel, Hitachi, NEC, AMD, IBM, etc.
  • the mapping held by the elements for holding or memory corresponds to the CPU type and the application interface.
  • the programmable logic circuit may be a field programmable logic array (FPGA) or other similar programmable circuit, for example, the programmable logic circuit could be programmable array logic (PAL), an application-specific integrated circuit (ASIC), or other circuit including programmable and reprogrammable logic.
  • FPGA field programmable logic array
  • PAL programmable array logic
  • ASIC application-specific integrated circuit
  • the predetermined event may be any convenient event, such as power up or some form of operator intervention.
  • Figure 1 is a schematic block diagram of one CPU-based daughtercard and motherboard in accordance with the invention
  • FIG. 2 is a schematic block diagram of a daughterboard in accordance with the invention.
  • Figure 3 is a diagram of the memory contents of the daughterboard of Figure 2;
  • FIG. 4 is a schematic block diagram of a further daughterboard in accordance with the invention showing an interface connection to configuration information in a memory on a motherboard;
  • Figure 5 is a diagram of the memory contents of the memory of the daughterboard of Figure 4.
  • FIG. 6 is a schematic block diagram of a further daughterboard in accordance with the invention showing an interface connection to configuration information on a motherboard, and
  • Figure 7 is a diagram of the memory contents of the configuration memory in Figure 6.
  • FIG. 1 illustrates an embodiment of the invention wherein there is provided a daughtercard 102, including a central processing unit (CPU) or micro processor unit (MPU) 103, memory 104 and reprogrammable logic 107, connected to a connector 105 on an application motherboard 101 by an edge connector 105a.
  • CPU central processing unit
  • MPU micro processor unit
  • the application motherboard includes substantially all necessary functions for a particular application, except for the central processing sub-system functions.
  • the central processing sub-system functions required by a particular application are supplied by plugging in the CPU- based daughtercard 102.
  • the interconnection between the CPU-based daughtercard 102 and the motherboard 101 is now described in greater detail.
  • the CPU-based daughtercard 102 communicates with other components of the application motherboard 101 via signals sent over a plurality of input/ output lines 106, 106a and 106b.
  • different CPUs are defined to have one or more different input/ output lines and electrical characteristics. Therefore, at least some of the connections between the CPU 103 input/ output lines and the motherboard are programmable (i.e. input/output lines 106b).
  • the CPU-based daughtercard input/ output lines are connected to the motherboard through an interface including edge connector 105a on the daughterboard and socket connector 105 on the motherboard.
  • the individual conductors of such connectors would be defined to correspond to specific functions of the CPU-based daughtercard input/output lines 106a and 106b
  • the CPU- based daughtercard may be associated with the conductors and connectors associated with input/output lines 106b in any convenient fashion.
  • the CPU sub-system connections 108 may be routed to any conductors of the connector 105 on the daughtercard.
  • the daughtercard may be routed to different conductors of the connector 105.
  • some of the CPU-based daughtercard input/output lines 106b are mapped on to an electronic switching device such as a field-programmable gate array (FPGA) 107.
  • FPGA field-programmable gate array
  • An FPGA is one type of programmable logic circuit device including a collection of general logic devices which may be connected together to form a desired logic function by programming. Programming usually involves loading a map of interconnections between the general logic devices into the FPGA.
  • the general logic devices are usually serial logic elements, such as gates, but also include parallel and clock elements in many versions.
  • the logic function embodied in a programmed FPGA may be as simple as a routing of signals, such as might be performed by a switch.
  • the logic function may include such processing of signals as changing timing or polarity or function, may produce output signals not found among the input signals, or may include complete functional blocks such as universal Asynchronous Receive/Transmitters (UARTS) or Direct memory Access Controllers (DMACs).
  • UARTS universal Asynchronous Receive/Transmitters
  • DMACs Direct memory Access Controllers
  • the FPGA may be programmed, but not limited to, any or all of the tasks noted above.
  • the FPGA 107 performs the overall logic function necessary to map the collection of functions required by the CPU sub-system connections 108 to the input/output lines 106b of the daughtercard connector 105. For example, a particular CPU 103 may issue memory read and write requests using one set of signals transmitted over the CPU sub-system connections 108, whereas the motherboard connections 106 may include a different set of signals to perform read and write functions in an attached memory 109.
  • the FPGA logic function is thus designed to map between the two distinct representations of a similar function.
  • the CPU-based daughtercard FPGA logic function may configure the input/ output lines to conform to standard bus configurations, such as ISA or PCI, bespoke bus configurations such as CPU native, or application motherboard custom connections such as peripherals 1 11, and include connections to functional blocks within the FPGA.
  • standard bus configurations such as ISA or PCI
  • bespoke bus configurations such as CPU native, or application motherboard custom connections such as peripherals 1 11, and include connections to functional blocks within the FPGA.
  • the motherboard 101 in this embodiment contains additional program memory 109 containing application program information specific to an individual motherboard that can be executed by the CPU or MPU 103 on the daughtercard 102.
  • the motherboard also contains configuration hardware 1 10 such as switches, jumpers and resistors that can be read by the daughtercard and allow the daughtercard to configure itself according to the configuration hardware information.
  • the motherboard also contains configuration memory 112 that can be read by the daughtercard, and which allows the daughtercard to configure itself according to the configuration memory information.
  • FIGS 2 and 3 show the read-only memory (ROM) 104 and its contents on the CPU-based daughtercard 102.
  • ROM read-only memory
  • Each CPU 103 is accompanied by a ROM 104 containing a program which properly maps the CPU sub-system connections 108 for the CPU 103 to the application motherboard connector 105 and the motherboard connections 106.
  • the FPGA 107 may be loaded via the CPU subsystem connections 108 with different programs corresponding to the mapping required for different CPUs 103 and motherboards 101.
  • Figure 3 shows an example memory map for the daughtercard 102.
  • the programs and data of Figure 3 are stored in memory 104 of the daughtercard.
  • the daughtercard starts executing a program in the ROM 104, it first accesses a Reprogrammable Logic Loader Program 201 which tells the CPU or MPU 103 to program the reprogrammable logic 107 with the information stored in a Reprogrammable Logic Application Interface Image 203 area of memory.
  • the CPU executes the program (and uses data) from the Application Program and Data area 202 of the memory.
  • the memory 104 provided on the CPU-based daughtercard 102 need not be strictly read-only but should include a non-volatile memory type. Any suitable type of memory which retains its contents while power is not applied to the daughtercard 102 may be employed. Thus, although the program for the FPGA 107 is retained during intervals of power being off, the CPU-based daughtercard 102 could be reprogrammed, when improvements are made to the FPGA program corresponding to the CPU 103 or the application motherboard 101 or a new application or motherboard is produced. Electrically alterable read-only (EAROM) is an example of a memory which is non-volatile and hence, used primarily in a read-only mode, but whose contents may be changed from time to time as required.
  • EAROM Electrically alterable read-only
  • the program for FPGA 107 need not be the only function of a ROM or similar memory 104 on the CPU-based daughtercard 102.
  • the ROM 104 may include instructions for programming other devices, additional configuration data for use by the CPU 103, or program instructions for one or more CPU functions. Other applications of that space in the ROM 104 which is not used by the FPGA program will become apparent to those designing specific applications.
  • the FPGA 107 may be loaded with the configuration program contained in the ROM 104 upon the occurrence of any convenient event.
  • the FPGA 107 may be loaded at system power up, or upon issuance of a reset signal as a result of operator intervention.
  • Other automatic and operator intervention events which may be used at appropriate times to load or partially reload the FPGA 107 will be readily apparent to those skilled in the art who may be developing any particular application.
  • the circuitry described above as being associated with a daughtercard may be included in some type of hybrid or other integrated module, including integration onto a single component.
  • the FPGA 107 and connector 105 technologies may be similarly varied, in accordance with generally accepted design techniques.
  • the connectors 105 may simply be a socket into which all hybrid CPU sub- system modules 102 may be designed to fit. Therefore, it is intended that the terms motherboard 101, daughtercard 102 and related terms in this application be broadly construed to include any technology by which the separation of function and connections between those functions discussed above may be accomplished.
  • Figures 4 and 5 show a further daughterboard.
  • Read-only memory 104 may, for example, contain more than one FPGA map, and configuration hardware 110 included on the motherboard show the identification of the type of motherboard 101. This may for example, take the form of switches or wire jumpers or the like, or a memory containing configuration data.
  • the CPU would read this motherboard configuration hardware 110.
  • the CPU-based daughtercard Upon receipt of a motherboard identification from configuration hardware 110, the CPU-based daughtercard would then correctly and appropriately self-configure the programmable logic circuits 107. If no correct identification was found, the CPU-based daughtercard could put itself into a safe state.
  • Figure 5 shows an example memory map for the daughtercard 102 of Figure 4 which would configure itself based on configuration information from the motherboard 101 ( Figure 1).
  • the daughtercard starts executing a Reprogrammable Logic Configuration Checker Program 301 in the ROM, it first accesses the motherboard to read the configuration information in the configuration hardware 110 ( Figure 1).
  • the Reprogrammable Logic Loader Program 301 tells the CPU or MPU 103 to program the reprogrammable logic with the correct Reprogrammable Logic Application Interface Image 303, 304, 305 appropriate to the configuration hardware found on the motherboard.
  • the CPU executes the program (and uses data) from the Application Program and Data area 302 of the memory.
  • This example shows 3 configurations stored, but this could be any number appropriate to the number of motherboard configurations required.
  • Figures 6 and 7 show a further variant of the daughtercard 102.
  • Read-only memory 112 may for example, be on the motherboard.
  • This memory contains Reprogrammable Logic Application Interface Image 401 to be used by the daughtercard 102.
  • the daughtercard Reprogrammable Logic block 107 (suitably an FPGA) reads this memory and then self-configures the programmable logic circuits.
  • the CPU-based daughtercard 102 could retrieve a new Reprogrammable logic Application Interface Image 401 for the FPGA and store this in its own memory 104.
  • the motherboard Configuration memory may contain other information 402 that is needed by the motherboard and daughtercard such as a program or data information.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)

Abstract

L'invention porte sur un module (102) informatique à carte unique doté d'une matrice FPGA (107) qui est disposée de façon à adapter des adresses et des fonctions de bus à partir d'une unité centrale (103) aux connexions (105) de bus requises d'une carte-mère (101). Le module peut être agencé de façon à desservir les connexions de bus requises et à adapter les adresses de bus.
PCT/GB1999/003946 1999-11-25 1999-11-25 Module informatique et carte-mere WO2001038997A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP99956229A EP1232443A1 (fr) 1999-11-25 1999-11-25 Module informatique et carte-mere
AU12872/00A AU1287200A (en) 1999-11-25 1999-11-25 Computer module and motherboard
CA002392503A CA2392503A1 (fr) 1999-11-25 1999-11-25 Module informatique et carte-mere
PCT/GB1999/003946 WO2001038997A1 (fr) 1999-11-25 1999-11-25 Module informatique et carte-mere

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/GB1999/003946 WO2001038997A1 (fr) 1999-11-25 1999-11-25 Module informatique et carte-mere

Publications (1)

Publication Number Publication Date
WO2001038997A1 true WO2001038997A1 (fr) 2001-05-31

Family

ID=10848196

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1999/003946 WO2001038997A1 (fr) 1999-11-25 1999-11-25 Module informatique et carte-mere

Country Status (4)

Country Link
EP (1) EP1232443A1 (fr)
AU (1) AU1287200A (fr)
CA (1) CA2392503A1 (fr)
WO (1) WO2001038997A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2384334A (en) * 2002-01-19 2003-07-23 Inc Technologies Control module and expansion board, with a control processor module, for connection to a motherboard bus
CN1299213C (zh) * 2002-09-19 2007-02-07 华为技术有限公司 利用系统板上的cpu进行集中控制处理的方法
WO2016127578A1 (fr) * 2015-02-12 2016-08-18 中兴通讯股份有限公司 Sous-carte de processeur, carte d'alimentation adaptée à la sous-carte de processeur, et carte système

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994027224A1 (fr) * 1993-05-07 1994-11-24 National Semiconductor Corporation Appareil et procede pour la reconnaissance et la configuration automatiques d'un peripherique
EP0860781A2 (fr) * 1997-02-21 1998-08-26 Vlsi Technology, Inc. Dispositif de connexion d'interface multiple et méthode de reconfiguration d'interface de carte PC standard
US5898846A (en) * 1994-09-19 1999-04-27 Kelly; Michael CPU interconnect system for a computer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994027224A1 (fr) * 1993-05-07 1994-11-24 National Semiconductor Corporation Appareil et procede pour la reconnaissance et la configuration automatiques d'un peripherique
US5898846A (en) * 1994-09-19 1999-04-27 Kelly; Michael CPU interconnect system for a computer
EP0860781A2 (fr) * 1997-02-21 1998-08-26 Vlsi Technology, Inc. Dispositif de connexion d'interface multiple et méthode de reconfiguration d'interface de carte PC standard

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2384334A (en) * 2002-01-19 2003-07-23 Inc Technologies Control module and expansion board, with a control processor module, for connection to a motherboard bus
GB2384334B (en) * 2002-01-19 2004-07-07 Inc Technologies Kiosk technology kit
CN1299213C (zh) * 2002-09-19 2007-02-07 华为技术有限公司 利用系统板上的cpu进行集中控制处理的方法
WO2016127578A1 (fr) * 2015-02-12 2016-08-18 中兴通讯股份有限公司 Sous-carte de processeur, carte d'alimentation adaptée à la sous-carte de processeur, et carte système

Also Published As

Publication number Publication date
AU1287200A (en) 2001-06-04
CA2392503A1 (fr) 2001-05-31
EP1232443A1 (fr) 2002-08-21

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