WO2001029990A1 - Procede et appareil de commande de synchronisation dans des systemes de communication numerique - Google Patents

Procede et appareil de commande de synchronisation dans des systemes de communication numerique Download PDF

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Publication number
WO2001029990A1
WO2001029990A1 PCT/US2000/041221 US0041221W WO0129990A1 WO 2001029990 A1 WO2001029990 A1 WO 2001029990A1 US 0041221 W US0041221 W US 0041221W WO 0129990 A1 WO0129990 A1 WO 0129990A1
Authority
WO
WIPO (PCT)
Prior art keywords
transceivers
transceiver
time
signal
common
Prior art date
Application number
PCT/US2000/041221
Other languages
English (en)
Inventor
Teresa H. Meng
Original Assignee
Atheros Communications, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atheros Communications, Inc. filed Critical Atheros Communications, Inc.
Priority to JP2001531227A priority Critical patent/JP2003528483A/ja
Priority to CA002388040A priority patent/CA2388040A1/fr
Priority to IL14924600A priority patent/IL149246A0/xx
Priority to EP00982682A priority patent/EP1222757A1/fr
Priority to AU19681/01A priority patent/AU1968101A/en
Publication of WO2001029990A1 publication Critical patent/WO2001029990A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H04W56/004—Synchronisation arrangements compensating for timing error of reception due to propagation delay
    • H04W56/0045—Synchronisation arrangements compensating for timing error of reception due to propagation delay compensating for timing error by altering transmission time
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H04W56/0005—Synchronisation arrangements synchronizing of arrival of multiple uplinks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H04W56/0055—Synchronisation arrangements determining timing error of reception due to propagation delay
    • H04W56/0065—Synchronisation arrangements determining timing error of reception due to propagation delay using measurement of signal travel time
    • H04W56/007—Open loop measurement
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H04W56/0055—Synchronisation arrangements determining timing error of reception due to propagation delay
    • H04W56/0065—Synchronisation arrangements determining timing error of reception due to propagation delay using measurement of signal travel time
    • H04W56/009—Closed loop measurements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
    • H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
    • H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
    • H04B2201/7097—Direct sequence modulation interference
    • H04B2201/709709—Methods of preventing interference

Definitions

  • Synchronous and asynchronous packet based communications systems are well known
  • packet transmissions must be synchronized so that packets are received by the receiver with a time of arrival that falls within a narrow predetermined detection window If a packet is transmitted such that it is not received within the predetermined detection window , the receiver will not detect it
  • asynchronous packet based communications systems do not require synchronization of the time of arrival with a narrow predetermined window, but instead typically require either a much longer detection window in order to detect the incoming asynclironous communication or simply limit the number of users, or a dynamic allocation of packets to different users
  • timing control is not attempted in asynchronous environments, such as the reverse link of an IS-95 compliant communication system, the signals from multiple users arrive at random times and the interference rejection capabilities become reduced.
  • the present invention provides an apparatus and method for detecting the relative time of arrival of different signals at a single receiver from different respective transmitters, and causing the different respective transmitters to alter the time that they transmit their signals so that the time of arrival of signals from different transmitters is within a predetermined period.
  • the present invention uses either a closed loop timing control, a GPS based timing control, or an open loop based timing control, to determine the time that signals from different transmitters needs to be altered in order to obtain time of arrival for different signals within the predetermined period.
  • any detection algorithms requiring time synchronism for example multi-user detection, can be much more effective in interference rejection for the data transmitted from multiple transmitters to a single receiver.
  • This invention can be applied to many different types of communications systems, and has particular applicability to code division multiple access (CDMA) systems, which CDMA systems may or may not use multi-user detection schemes in which interference rejection can then be more effective.
  • CDMA code division multiple access
  • This invention can also be applied to multiple antenna systems, where the timing of signal arrivals from multiple antennas (either from a single transmitter or from multiple transmitters) is also of importance.
  • the present invention can be applied to orthogonal frequency division multiplexing (OFDM) systems where multiple users transmit data at the same time, which require precise timing control at the receiver
  • OFDM orthogonal frequency division multiplexing
  • TDMA time division multiple access
  • Fig 1 illustrates an overview of a multi-user system according to the invention
  • Fig 2 illustrates the relative time of arrival of the first sample of arbitrary packets from different transmitters at a receiver prior to application of timing control according to the invention
  • Fig 3 illustrates the relative time of arrival of the first sample of arbitrary packets from different transmitters at a receiver after application of timing control according to the invention
  • Fig 4 further illustrates the definitions of delay and advance from a design point of view
  • Fig 5 illustrates a block diagram of a circuit for implementing closed loop timing control according to a preferred embodiment of the invention
  • Fig 6 illustrates a block diagram of a circuit for implementing open loop timing control according to a preferred embodiment of the invention
  • Fig 7 illustrates an example of multiple base-stations each with multiple end-users DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • the present invention implements timing control so that signals from a plurality of transceivers 100-1, 100-2, 100-3 100-n have a semi-synchronous time of arrival with respect to each other at a transceiver 120, such as illustrated in Fig 1 While not limited to the specific embodiment, the following discussion will be made with reference to a CDMA system that employs multi-user detection in the reverse link
  • consistent interval is not intended to mean synchronous or asynchronous, but only a repetition of consecutive packets such that communications can continue within the system.
  • the present invention manipulates the time that these signals are transmitted, so that their time of arrival at the receiver becomes semi-synchronous.
  • signals 100-1 to 100-4 become semi-synchronous with respect to the reference timing point 210.
  • Fig. 4 illustrates the sequence of events as a function of time.
  • transmitter 100-i starts the computation in preparation for the transmission of the next packet.
  • T2 the computation is completed and transmission starts.
  • the time between T2 and Tl is called the computation latency.
  • the delay and advance can be implemented by a delay line buffer, which holds the data to be transmitted in an array of pipeline registers. If the reference time is to be in between T2 and T3, as illustrated in Fig. 4, the buffer is about half deep, which means that the transmitted data would be delayed by (T3-T2V2 seconds.
  • the depth of the delay line buffer is adjusted accordingly.
  • the number of the pipeline registers that implement the delay line buffer is bounded by the maximum propagation delay between all the end-user transceivers to the base station. It should be understood that other manners of implementing the advance or delay could be used.
  • Fig. 5 illustrates a block diagram of a circuit 500 for implementing timing control according to a preferred embodiment of the present invention.
  • this Figure illustrates those circuits within the end-user transceiver (such as l OO-i), as well as within a base station transceiver 120 that are needed to implement the present invention.
  • Other parts of receivers, transmitters or transceivers can be made using conventional techniques and methods, and will therefore not be further discussed.
  • the base station transceiver 120 As illustrated, at the base station transceiver 120.
  • timing acquisition circuit 510 dedicated to that user
  • a timing comparatoi 530 gathers the timing information from each timing acquisition circuit 510 and performs time alignment in order to determine the advance or delay of the packets to be transmitted by that user's transceiver
  • the information on the amount of advance or delav that needs to be inserted by that particular transceiv er 100-1, which is performed separately for each individual user, is sent to that user as a timing control signal that is part of the data packet, which packet is assembled m the transceiver 120 using a conventional data packet assembler 580
  • This information, once receiv ed and decoded by the data packet decoder 570 associated with the transceiver 100-1 of the intended user is used to control a delay line buffer 540, which receives the data packet to be transmitted to the transceiver 120 from its own data packet assembler 550 before transmitting the next packet to the transceiver
  • timing extraction circuit Since the timing acquisition function at the receiver is necessary to determine the precise sampling phase of the incoming signal for signal detection, the extraction of the timing control signal from the incoming signal is relatively easily implemented by the timing extraction circuit, which extracts the timing information using conventional timing acquisition techniques, such as those proposed in H Meyr, M Moeneclaey, and S Fechtel, Chapters 5 & 10, Digital Communication Receivers, John Wiley and Sons, 1998, New York, K. H Mueller and H Muller, "Timing recovery in digital synchronous data receivers," IEEE Trans Communications, Vol COM-24, pp 516-531 , May 1976, and B Sklar.
  • the accuracy of closed-loop timing control implemented by the circuit 500 should preferably be within a fractional of a sample period, or at most a couple of sample periods, in order to provide for effective interference rejection in a CDMA system or concurrent multi- carrier signal detection in an OFDM system If the timing control does not align all packets from the various users to within a few sample periods, then the effectiveness that the present invention is able to ha ⁇ e will become substantially reduced
  • the multi-user detection algorithms such as described in Sergio Verdu, Muluusci Detection.
  • Fig 6 illustrates a block diagram of a circuit 600 for implementing open loop timing contiol accoidmg to a preferred embodiment of the present invention
  • this Figure lllustiates those circuits within the end-user transceiver (such as lOO-i)
  • the present invention can be implemented by making adaptations to end-user transceivers, without significantly affecting the design and operation of the base station transceiv er 120
  • other parts of receivers, transmitters or transceivers not mentioned herein can be made using conventional techniques and methods, and w ill therefore not be further discussed
  • each transceiver lOO-i to 100-n associated with each user keeps a time reference synchronized with base station transceiv er 120 This time synchronization within each transceiv er 100-1 to 100-n is maintained by either a GPS or through other means of global synchronization
  • the accuracy of open loop timing control implemented by the circuit 600 is a function of the channel multipath profile and the mobility of the users Assuming that the delay spread of the channel is relatively short compared to the required length of coherence for detection, the open loop timing control according to the invention can synchronize the incoming signals to within a fractional of one data symbol period (on the same older of the delay spread) It is noted that open loop timing control is typically not as precise as closed-loop timing control, since the uncertainty in multi-path channel is largei than the uncertainty of the timing acquisition circuit at the receiver.
  • the uncertainty in the timing can, therefore, be viewed as a form of multipath Since a properly designed multi-user detection system should perform well in the face of multipath in the forward link, the semi-synchronous reception as enabled by the present invention allows the system to deliver similar performance m the reverse link.
  • a specific example implementing the present invention using the system desc ⁇ bed above is the use of timing control in a CDMA system that employs multi-user detection. It is known how to perform interference rejection on asynchronous channels in a reverse link, but conventional interference rejection techniques are not used on time-aligned signals The application of the present invention in such systems allows all reverse link signals to become semi-synchronous, thereby simplifying the asynchronous detection algorithm to a synchronous detection algorithm.
  • the present mv ention allows multiple users m an OFDM system to transmit data at the same time because the signals transmitted from different users can be time-aligned at the receiver, as long as these users use different carrier frequencies in their transmission Since the signals from different users are time- aligned, FFT can be performed on the received signal without destroying the coherent properties of the tiansmitted data
  • the present invention provides a method such that signals transmitted from the transceivers 100 typically arrive at the base station transceiver 120 within a predetermined period of time, such as a few sample periods
  • the present invention can still be utilized if only substantially all, or any portion, of the signals arrive within the predetermined penod In that event, however, the overall signal detection capability may be degraded as compared to the case where all signals are time-aligned, but partially aligned systems should still perform better than those without using the present invention
  • any detection scheme that takes advantage of synchronous reception for example CDMA, multi-user detection, smart antenna, multiple antenna systems, TDMA, or multi-user OFDM, can benefit from this invention
  • the present invention can also be applied to a communication system where multiple base-stations are deployed, such as used m the cellular phone system
  • the relative timing information of the multiple transceivers detected by each base-station can be communicated to other base-stations
  • the exact amount of time advance or delay that should be exercised by each transceiver can be negotiated amongst the base-stations, for the purpose of achieving the best overall system performance
  • Base-station 710 performs timing control to its end-users transceivers 710-1
  • base-station 720 performs timing control to its end-users transceivers 720-1 Since transceiver 720-1 is closer to base- station 710 than to base-station 720.
  • transceiv er 720-1 it may be more advantageous for transceiv er 720-1 to be time-aligned with the reception of base-station 710, rather than to be time aligned ith the reception of base-station 720 Since, for the above example, the transceiv er 720-1 is closer to base-station 710. if it is time-aligned with base-station 710 then the interference that it may otherwise be creating for base-station 710 can be removed Although transceiver 720-1 will not necessa ⁇ lv be time aligned w ith base station 720 although it w ill be communicating w ith it.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

L'invention concerne un appareil et un procédé qui permettent de détecter l'heure d'arrivée relative, à un récepteur simple, de différents signaux provenant de différents émetteurs-récepteurs respectifs, et d'amener ces derniers à modifier l'heure à laquelle ils transmettent leurs signaux afin que l'heure d'arrivée desdits signaux se situe dans un intervalle de temps préétabli. Le procédé de l'invention met en oeuvre soit un synchronisateur en boucle fermée, soit un synchronisateur GPS, soit encore un synchronisateur en boucle ouverte, pour déterminer l'heure à laquelle des signaux provenant de différents émetteurs-récepteurs doivent être modifiés pour déterminer l'heure d'arrivée pour différents signaux dans les limites dudit intervalle de temps préétabli. Il résulte du caractère 'semi-synchrone' des signaux entrants que les algorithmes de détection exploitant le synchronisme temporel, tel qu'une détection multi-usager ou un rejet des bruits, peuvent être beaucoup plus efficaces en détection de signaux pour les données transmises à un récepteur simple à partir de plusieurs émetteurs-récepteurs.
PCT/US2000/041221 1999-10-21 2000-10-17 Procede et appareil de commande de synchronisation dans des systemes de communication numerique WO2001029990A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2001531227A JP2003528483A (ja) 1999-10-21 2000-10-17 デジタル通信システムのタイミング制御の方法および装置
CA002388040A CA2388040A1 (fr) 1999-10-21 2000-10-17 Procede et appareil de commande de synchronisation dans des systemes de communication numerique
IL14924600A IL149246A0 (en) 1999-10-21 2000-10-17 Method and apparatus for timing control in digital communication system
EP00982682A EP1222757A1 (fr) 1999-10-21 2000-10-17 Procede et appareil de commande de synchronisation dans des systemes de communication numerique
AU19681/01A AU1968101A (en) 1999-10-21 2000-10-17 Method and apparatus for timing control in digital communication systems

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US42282999A 1999-10-21 1999-10-21
US09/422,829 1999-10-21

Publications (1)

Publication Number Publication Date
WO2001029990A1 true WO2001029990A1 (fr) 2001-04-26

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PCT/US2000/041221 WO2001029990A1 (fr) 1999-10-21 2000-10-17 Procede et appareil de commande de synchronisation dans des systemes de communication numerique

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EP (1) EP1222757A1 (fr)
JP (1) JP2003528483A (fr)
AU (1) AU1968101A (fr)
CA (1) CA2388040A1 (fr)
IL (1) IL149246A0 (fr)
WO (1) WO2001029990A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113484504A (zh) * 2021-07-19 2021-10-08 江苏省建工建材质量检测中心有限公司 建筑墙体缺陷检测装置与方式

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101151525B1 (ko) 2006-09-28 2012-05-30 교세라 가부시키가이샤 Ｔｄｄ/ｏｆｄｍａ 통신 방식의 통신 제어 방법, 기지국 장치, 단말 장치 및 통신 제어 시스템

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2277232A (en) * 1993-03-20 1994-10-19 Motorola Inc Timing of transmission from a mobile unit in a TDMA communications system
US5499236A (en) * 1994-08-16 1996-03-12 Unisys Corporation Synchronous multipoint-to-point CDMA communication system
US5870427A (en) * 1993-04-14 1999-02-09 Qualcomm Incorporated Method for multi-mode handoff using preliminary time alignment of a mobile station operating in analog mode
WO1999049587A1 (fr) * 1998-03-20 1999-09-30 Koninklijke Philips Electronics N.V. Commande de synchronisation d'un creneau temporel de transmission

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2277232A (en) * 1993-03-20 1994-10-19 Motorola Inc Timing of transmission from a mobile unit in a TDMA communications system
US5870427A (en) * 1993-04-14 1999-02-09 Qualcomm Incorporated Method for multi-mode handoff using preliminary time alignment of a mobile station operating in analog mode
US5499236A (en) * 1994-08-16 1996-03-12 Unisys Corporation Synchronous multipoint-to-point CDMA communication system
WO1999049587A1 (fr) * 1998-03-20 1999-09-30 Koninklijke Philips Electronics N.V. Commande de synchronisation d'un creneau temporel de transmission

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113484504A (zh) * 2021-07-19 2021-10-08 江苏省建工建材质量检测中心有限公司 建筑墙体缺陷检测装置与方式
CN113484504B (zh) * 2021-07-19 2023-10-27 江苏省建工建材质量检测中心有限公司 建筑墙体缺陷检测装置与方式

Also Published As

Publication number Publication date
IL149246A0 (en) 2002-11-10
CA2388040A1 (fr) 2001-04-26
AU1968101A (en) 2001-04-30
EP1222757A1 (fr) 2002-07-17
JP2003528483A (ja) 2003-09-24

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