WO2001028165A1 - Methode de synchronisation-esclave d'horloge et dispositif correspondant - Google Patents

Methode de synchronisation-esclave d'horloge et dispositif correspondant Download PDF

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Publication number
WO2001028165A1
WO2001028165A1 PCT/JP1999/005681 JP9905681W WO0128165A1 WO 2001028165 A1 WO2001028165 A1 WO 2001028165A1 JP 9905681 W JP9905681 W JP 9905681W WO 0128165 A1 WO0128165 A1 WO 0128165A1
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WIPO (PCT)
Prior art keywords
clock
node
value
slave
route
Prior art date
Application number
PCT/JP1999/005681
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English (en)
Japanese (ja)
Inventor
Tsuyoshi Matsumoto
Hidetoshi Amari
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP1999/005681 priority Critical patent/WO2001028165A1/fr
Publication of WO2001028165A1 publication Critical patent/WO2001028165A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0641—Change of the master or reference, e.g. take-over or failure of the master
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/08—Intermediate station arrangements, e.g. for branching, for tapping-off
    • H04J3/085—Intermediate station arrangements, e.g. for branching, for tapping-off for ring networks, e.g. SDH/SONET rings, self-healing rings, meashed SDH/SONET networks

Definitions

  • the present invention relates to a clock-dependent synchronization method and a clock-dependent synchronization device.
  • the present invention relates to a clock-dependent synchronization method and a clock-dependent synchronization device, and more particularly to setting a node as a master node for all nodes in a network to prevent a failure of a current master node and a communication channel.
  • the present invention relates to a clock-dependent synchronization method and a clock-dependent synchronization device in which, when a failure or the like occurs, a node having the next highest value of 1S3 ⁇ 4g transitions to a mass node.
  • each node has ⁇ fejg (hereinafter, referred to as "clock ⁇ "), which is a ranking related to a clock, and has one of tii own clocks ⁇ in the knitting network.
  • clock ⁇ ⁇ fejg
  • the IUi nodes exchange data including the clock priority with each other to determine the master node.
  • the slave node is subordinately synchronized with the master node clock.
  • the network shown in the figure includes nodes 10 to 15, clock sources 50 to 52, and transmissions 30 to 43.
  • Nodes are classified into nodes 10, 12, and 14 having master clock sources 50, 51, and 52, respectively, and nodes having no clock source. As shown in the figure, each node is assigned a number corresponding to the clock rag.
  • Nodes 10, 12, and 14 with master clock sources 50, 51, and 52 are numbered lower than nodes without a clock source. Since the priority number is / J and the clock is higher, the nodes 10, 12 and 14 with the master clock source 50, 51 and 52 have the higher clock. Than a node without a source The clock is set high.
  • node 10 since the node with the lowest frequency is node 10, node 10 becomes the master node in the network of FIG. 1 and supplies the clock source to the other nodes 11 to 15. I have. In addition to the clock, the difficulty number # 1 of the master node 10 is also indicated as shown in the figure. Therefore, it is possible to know which node is the master node from the priority number of the master node given in ⁇ 5 ⁇ .
  • each node compares the obtained clock rate with its own clock rate, and if the node's clock ⁇ t degree is larger, it becomes a master node, and if it is lower, it becomes a slave node.
  • the node 14 having the highest clock priority other than the node 10 becomes the master node, and the system is maintained.
  • the master node always sends a sequence number (S) that changes every cycle to the communication path.
  • S sequence number
  • the experiment of the sequence number is checked.
  • the node that detects that the sequence number of a certain route has lost its flexibility stops the subordination of the clock to that route, becomes a temporary master node, and sends its node's ⁇ ; degree number. Then, the node is extracted again.
  • the absence of the master node can be detected from this sequence number. For example, if the master node bypasses the feit road and is disconnected from the it road, The ⁇ fe frequency number of the master node goes around the network. However, each slave node can detect the absence of a master node by detecting the continuity of sequence numbers.
  • a clock path may form an independent loop, and clock sources may exist separately in the network.
  • slips occur in the memory used to synchronize information frames, and the slippage occurs due to the difference between the speed at which the received information is written and the speed at which the received information is read out, and the lack or overlap occurs. I do. Therefore, the occurrence of a slip error or the like is prevented by checking the nature of the sequence number.
  • the network configuration may be operated in a complex mesh (lattice) state.
  • each node is artificially operated. This was achieved by providing a code patch (hard switch) function to the system and forcibly creating a clear clock path.
  • the absence of a master node and the elimination of! 3 loop formation can be performed by setting a clock number and a sequence number.
  • the clock path from the master node does not always form an appropriate tree shape. This is because the number of relay stages of the clock path cannot be determined by the sequence number.
  • the clock dependent synchronization method of the present invention comprises a plurality of nodes having clock degrees, and each node transmits and receives data including the clock degree, thereby providing the highest level of the self-clock ⁇ fc degree.
  • the self node becomes the master node that supplies the clock to the entire network, and the other 1JI self node sets the relay value to
  • a clock dependent synchronization method comprises the steps of: setting a relay value in the master node and transmitting the data; and, if the received relay value is larger than a predetermined value, receiving the received value. Synchronize with the feit path where the medium fiber value is large, further reduce the relay value of the received it's own data by a predetermined number, and fSt to the adjacent node, or the number of relays received at the slave node If the value is smaller than the predetermined value, a step of synchronizing the received data with a small relay value with the feited transmission line, further increasing the relay value of the received data by a predetermined number, and feiiing the adjacent node.
  • Each slave node determines the slave of the clock based on the clock level of the master node and the relay value set by the master node and increased or decreased by a predetermined value for each relay.
  • the clock dependent synchronizer of the present invention is composed of a plurality of nodes having a clock ⁇ , and ii each node transmits and receives data including the clock ⁇ , so that the clock is synchronized with the clock ⁇ .
  • the relay node, the master node becomes the master node that supplies the clock to the entire network, and the other it nodes, in the clock-dependent synchronizer in the network that becomes the slave nodes, are the relay values set by the jf master node.
  • ⁇ ⁇ ⁇ a processing unit for synchronizing with the clock of the channel, further reducing or increasing the il-self relay value of the received il-self data by a predetermined number, and transmitting the reduced value to an adjacent node.
  • the clock-dependent synchronizer includes: a receiving unit that receives data including a relay value set by a master node; and a receiver that receives a larger relay value when the received medium fiber value is larger than a predetermined value.
  • the relay value of the received data is reduced by a predetermined number and sent to the adjacent node, or if the received medium fiber value is smaller than the predetermined value,
  • FIG. 1 shows the conventional technology, and the clock in a steady state of the network.
  • FIG. FIG. 2 is a diagram illustrating a state of a clock path when a failure occurs in a master node according to the related art.
  • FIG. 3 is a diagram showing a state of a clock path when a road failure or the like occurs in the conventional technology.
  • FIG. 4 is a diagram illustrating a state of a clock and a clock at the time of recovery from a path failure or the like according to the related art.
  • FIG. 5 is a diagram illustrating the principle of the present invention.
  • FIG. 6 is a configuration diagram of the entire network in the embodiment of the present invention.
  • FIG. 7 is a diagram for explaining the clock dependent synchronizer of the present invention.
  • FIG. 8 is a diagram showing an example of a block configuration of a CPID (CPID: C1OckPriorityID) processing unit in the embodiment of the present invention.
  • FIG. 9 is a diagram showing a CP ID and a cell ZCP ID frame in the embodiment of the present invention.
  • FIG. 10 is a diagram showing an example of a block configuration of the clock interface unit in the embodiment of the present invention.
  • FIG. 11 is an operation flow of the CPID processing unit.
  • FIG. 12 is a diagram showing a flow of a clock path during normal operation in the embodiment of the present invention.
  • FIG. 13 is a diagram (part 1) illustrating a flow on a clock path at the time of failure in the embodiment of the present invention.
  • FIG. 14 is a diagram (part 2) illustrating a flow in the clock path at the time of failure in the example of the present invention.
  • FIG. 15 is a diagram (part 3) illustrating the flow on the clock path at the time of failure in the embodiment of the present invention.
  • FIG. 16 is a diagram (part 4) illustrating a flow in the clock path at the time of failure in the embodiment of the present invention.
  • the present invention provides a node relay stage number (here, NRID: Node Relay 10) which is a relay numerical value instead of the sequence number employed in the conventional technology.
  • NR node relay stage number
  • the node that has become the slave node compares the NR IDs received from multiple communication feit routes, and ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ Send it to the i3 ⁇ 4t route. Also, it does not depend on the fei road whose NRID value is "0".
  • the slave is suspended from the route, and the NR IDs received from other multiple communication ⁇ 5 ⁇ routes are compared. Synchronizes with the clock from the communication channel with the largest value.
  • the initial value of the NRID value is set in advance by the master node (10 in FIG. 5). This value may be set to a value greater than or equal to the value of the relay stage to the farthest node in the network. For example, in the case of the network shown in Fig. 5, when the communication fei path 30 and the communication feit path 39 fail, the relay stage value to the farthest node 13 is 4, so the master node 10 uses the NRID value as the NRID value. Set a value of 4 or more. As a result, each of the nodes 11 to 15 has a large NR ID value and can depend on the clock of the route. As a result, a clock path that minimizes the number of relay stages from the master node can be configured.
  • the slave synchronizes with the clock from the communication channel having the smallest value and the value from the channel, and increments the value of NR ID before sending it to the communication channel.
  • NP ID Node Priority ID. In the figure, it is described as NP.
  • the slave node compares the NP ID values and subordinates to the route with the higher degree. For example, in the node 14, since the NR ID value of the clock from the communication Si path 42 and the NR ID value of the clock from the communication path 40 are the same, it is not possible to determine which of the paths depends on the path. Therefore, look at the NP ID value. Communication ⁇ Since the NPID value from the communication path 42 is 102, and the NP ID value from the communication path 40 is 101, in this case, the node 14 Synchronizes with the clock from 0.
  • route clock should be synchronized only with the NR ID value and NP ID of its own.
  • the NR ID value and NP ID value are equal, so it is difficult to know which route to use.
  • ⁇ degrees are provided for each route unit, the route ⁇ t degrees is high, and the route is dependent on the route.
  • each node compares the values between the links for the clock ⁇ t degree, NR ID, NP ID, and the path ⁇ degrees in order to determine which route clock should be synchronized.
  • a comparison unit is provided. This comparison unit compares the clock received from each communication channel with the NR ID value (the ratio ra i) and the clock priority, NR ID, NP ID, and the route type. Prepare a block (comparing unit 2) to switch the ratio according to the conditions.
  • the switching of the master node in the system is performed at a preset ⁇ t degree. Therefore, before starting operation, set the clock of the master clock for all nodes.
  • This ⁇ feS information (hereinafter referred to as r ⁇ fcJt information) is transmitted to the communication channel on the network, and at each node, the ⁇ feS information received from the communication feii channel is set to the local node. If the own node has a higher degree, it becomes a master node, and thereafter sends its own degree information. If information with a higher priority than the own node is input from the communication transmission line, the slave node becomes a slave node that synchronizes dependently on that route.
  • the slave node sends priority information from the route performing slave synchronization to each route, so that the degree information is distributed to all nodes in the network, and the relationship between the master and the slave in the network is established. Holds.
  • ⁇ information in the present invention ⁇ .
  • FIG. 6 shows a configuration example of the entire network.
  • an ATM network configured in a mesh shape is assumed, and in the figure, an ATM node including four ATM devices is connected by a transmission path.
  • the inside of the ATM device is basically composed of a cell switch section 65 and a CPID processing section 64.
  • the cell switch section 65 refers to a VPI (virtual path identifier) in the ATM cell header and sets a preset table. Switching based on information. There are seven ports, numbered 0-6.
  • FIG. 7 shows the clock-dependent synchronizer of the present invention in the ATM device of FIG. It is shown together with the interface section.
  • FIG. 7 shows a cell switching section 65, a switching table 111, line interface sections 110 and 112, a CP ID processing section 64, and a clock interface section 114.
  • the cell switching unit 65 and the CP ID processing unit 64 are the same as those shown in FIG.
  • the cell switching unit 65 switches the ATM cell with reference to the switching table 111.
  • the line interface units 110, 112 take an interface between the fe route and the cell switching 65.
  • the CP ID processing section 64 includes a CP ID cell insertion section 85, a CP ID cell extraction section 86, a CP ID decellularization section 74, a CP ID cell conversion section 83, and a CP ID arbitration section 87.
  • the CP ID processing unit 64 extracts a power ⁇ CP ID cell, which will be described in detail later, compares the CP ID, NR ID, NPID, and route, and determines whether the node is a master node or a slave node.
  • the clock interface unit 114 is composed of an oscillator 10 and a PLL reference clock selection unit 113 and a PLL circuit 103. Based on a source clock selection signal from the CP ID processing unit 64, an external ⁇ ⁇ ⁇ ⁇ ⁇ clock is used. And its own clock 101 and output? And applied to the circuit 103. The output of the PLL circuit 103 becomes the internal operation clock.
  • FIG. 8 is a block diagram showing the processing of CPID in each node. This figure corresponds to the CP ID processing unit 64 in FIG.
  • the CP ID cell identification unit 71 which identifies whether or not the cell from the cell switching unit is a CP ID cell, sets the expected VPI value of the received cell and sets the transmission VPI value. It has been done.
  • the CP ID cell identification unit 7 K VPI setting register 72 and the VPI comparison unit 73 correspond to the CP ID cell extraction unit 86 in FIG.
  • a de-serialization unit 74 for decelerating and assembling a CP ID frame is provided for each port; a CP ID ratio crane 75 for comparing and judging each bit of the CP ID frame, a NR ID comparison unit 76, NP ID ratio ⁇ 77, and route comparison unit 78 are provided. Further, a frame unit 81 that assembles the CP ID frame of the own node based on the values set in the own node CP ID setting register 79 and the NR ID setting register 80, the CP of the received CP ID frame and the CP of the own node CP ID frame. A master / slave determination unit 82 that compares ID bits and determines whether the own node becomes a master node or a slave node is provided.
  • the finalized CP ID frame is converted to a cell by the celling unit 83, the transmission VPI value is inserted by the VPI input unit 84, and then the CP ID cell identifier is inserted again for transmission to the cell switch unit A CP ID cell identifier insertion unit 85 is provided.
  • the subordination is determined based on the CP ID comparison unit 75, the NR ID comparison unit 76, the NP ID comparison unit 77, and the route comparison unit 78.
  • the cell from the path is applied to the CP ID cell identification unit 71, and the register value of the VPI setting register 72 and the VPI value of the CP ID cell are compared by VP ⁇ 3.
  • VP ⁇ 3 As a result, in the case of a CP ID cell, it is decellularized by the decellularization unit 74 for each boat.
  • the decelerated CP ID frame is sent to the CP ID comparator 75, the NR ID comparator 76, the NP ID ratio crane 77, and the route comparator 78 for the CP ID, NR ID job, NP ID ⁇ t, A road-to-degree comparison is made.
  • the frame detector 81 sends a CP ID frame based on the values of the own node CP ID setting register 79 and the NR ID setting register 80.
  • the master / slave determination unit 82 is based on the CP ID frame from the frame sensitivity unit 81 and the result of the CP ID ratio 3 ⁇ 43 ⁇ 475, NR ID comparison unit 76, NP IDJtra77, and route comparison unit 78. Master / slave judgment is performed based on, and a source clock selection signal is output. Also, the output of the master Z slave determination unit 82 is converted into a cell in a cell unit 83, a VPI is inserted in a VPI insertion unit 84, and a CP ID identifier is inserted in a CP ID cell identification input unit 85. A CP ID cell is generated.
  • the CP ID is converted into an ATM cell and communicated through a path set in the network in advance.
  • the path form of the CP ID cell is formed between nodes.
  • the CP ID cell transmitted from a certain node is switched to the CP ID processing unit in the cell switch unit of the adjacent node, and after the CP ID processing unit performs processing such as a long-term determination, the adjacent node node is re-established. Sent to the server.
  • FIG. 9 shows the format of the CP ID cell and the CP ID frame.
  • the CPID cell is a signal feiied between each node.
  • the header part of the CP ID cell is composed of 5 bytes, and is composed of address information such as VPI and VCI.
  • a code for identifying the CP ID cell is added to the upper 3 bits of VC I, and this code identifies whether the cell is a CP ID cell.
  • the actual CP ID frame is embedded in the 48 bytes of the information field, and is composed of CP ID / NR ID / NP ID information, respectively.
  • the “P” in ⁇ is the parity bit, which is used to check the normality of the data.
  • a portion where the information field of the CP ID cell is extracted becomes a CP ID frame, and various priority determinations are performed by a CP ID determination unit.
  • FIG. 10 shows an example of a block configuration of the clock interface unit 114.
  • the master Z slave determination unit in FIG. 8 outputs a source clock selection signal.
  • This signal is used in FIG. 10 as a signal for determining which of the clock extracting unit 100 for extracting a clock from the 3 ⁇ 4 path and the clock source 101 should be selected.
  • the source clock selection signal is input to the source clock selection unit 102, and it is determined whether to select the clock from the feit path or the source of the own node. It is input as the source clock of the reference clock of the filter 103.
  • the output clock of the PLL unit 103 is transmitted to the fei path via the operation clock in the device and the clock insertion unit 104. In this way, the CP ID is ⁇ determined, which clock should be subordinate to which ⁇ path, and a clock path is sequentially formed.
  • the switchback mode the node repeater number (NR ID) and the opposite station clock ⁇ degree number (NP ID) are used in addition to the clock ⁇ fc degree information, so that the clock path
  • the clock path can be looked at and optimized so that the number of relay stages is always minimized.
  • switching back to the previous clock path will occur.
  • non-revertive mode is a mode in which the currently configured clock path is always maintained. If the fault occurs on the iSi path through which the clock path passes, switching of the subordinate path occurs, but no failback occurs when the fault is recovered. Failure occurrence When Z recovery is repeated, it is not possible to identify what kind of clock has been finally constructed, and in some cases, the number of relay stages has increased, and the clock component has increased. It is feared that.
  • FIG. 11 is a flowchart showing the operation of the CP ID processing unit 64. The operation will be described with reference to FIG. 8 corresponding to the steps.
  • the CP ID defines a value up to 1 255, with 1 being the highest priority. If it is 0, the degree is the smallest.
  • Each node receives the CP ID frame from the decelerator 74 (S101).
  • the CP ID of the CP ID frame received from the feii path is compared with the CP ID of its own node (S103 S104), and the highest priority value is assigned to the cell unit 83 VPI insertion unit 84 CP ID cell identifier Transmitted to each transmission path via the insertion unit 85 (S117) o
  • the own node becomes the master node and sends the own node's CP ID to each iSt path ( S 105 S 109).
  • the NR ID is a number indicating the number of relayed CP ID frames to the node. This is a lock relay stage number signal.
  • the master node sends out the NR ID value set in its own node to each i3 ⁇ 4t route (S106, S110).
  • the slave node decrements the NRD value received from the dependent ⁇ ! Route by "1" and sends it to each route (S108, S113).
  • NP ID indicates the CP ID of the opposing node as described above.
  • Each CP ID processing unit compares in the following order.
  • the master / slave determination unit 82 shown in FIG. 8 compares it with its own node's ⁇ t degree number, and if its own node's ⁇ t degree is higher, it performs clock master operation. Switch, if the CP ID value from one route is high, subordinate to that route
  • NR 1 D is decremented each time CP ID passes through the node, and a node receiving “0” does not depend on the corresponding route. Since the initial value of NR ID is determined in advance at the time of transmission, the higher the value, the smaller the number of times the node has passed. Therefore, the highest value is adopted and it depends on the route.
  • NR ID comparison is not performed, and only reception monitoring of "0" of the dependent route is performed (S114). However, when determining the route, the NR ID values are compared as in the switchback mode (S I 12).
  • the switchback mode if the CP ID and NR ID are equal, the NP ID value indicating the priority number of the opposing node is compared (S107), and the lowest value is adopted. I do.
  • the values of CPID and NR ID will be the same.Therefore, one route is determined by notifying the ⁇ fc degree number that is uniquely determined in the network between the opposite nodes. To determine.
  • NP ID values are not compared and this area is ignored.
  • the NR ID values are compared in the same manner as in the mode with switching back (S112).
  • nodes 120 to 128, and external clocks 130 and 131 are surrounded by nodes 120 and 128.
  • the number in parentheses is the clock ⁇ number.
  • the shaded node is the master node, and the route indicated by: ⁇ is the clock path (each node is subordinate to the route marked).
  • Information flowing through each communication transmission line is shown in the figure, and the initial value of NR ID is set to "5".
  • Figure 12 shows the flow of the clock path during “normal operation” when the fault occurs between node 120 and node 121 (“feit failure occurs (1) J).
  • FIG. 12 shows the flow of the clock path during “normal operation” when the fault occurs between node 120 and node 121 (“feit failure occurs (1) J).
  • FIG. 13 illustrates how the clock path is switched in the case of “fe3 ⁇ 4 fault occurrence (2)” in which a fault has occurred between the nodes 120 and 123.
  • FIG. 14 illustrates the switching of the clock path when the master node transitions from the node 120 to the node 128 due to the failure of the external clock source 130.
  • the power number automatically changes (001 ⁇ 101).
  • Figures 15 and 14 assume a duplicated fei road in a mesh network. The priority number of the route is added to each route.
  • Figure 15 shows “The flow of the clock path during normal operation j is shown.
  • the CP ID, NR ID and NP ID are the same between the node 1 and node 2 0, but the dependent synchronization destination is determined by the route number.
  • Figure 16 shows the flow of the clock path in the event of a failure between nodes 120 and 121.
  • the clock path is switched to a clock path that forms an appropriate grid and minimizes the number of relay stages even if a failure in the communication channel occurs. be able to.
  • a clock path can be constructed even in a complicated network configuration such as a mesh network.
  • the number of relay stages in the clock path can be reduced, and an increase in clock component can be prevented.
  • the code patch function by an artificial operation which has been a problem in the technique of (1), is inevitably eliminated according to the present invention, and contributes to the improvement of network quality.

Abstract

Cette invention a trait à une méthode de synchronisation-esclave d'horloge et au dispositif correspondant permettant de faire en sorte qu'un noeud ayant le second degré de priorité le plus élevé devienne le noeud maître si le noeud maître en usage ou si la ligne de communication présentent une défaillance. Cette modification se fait par l'établissement de la priorité d'horloge qui détermine l'ordre dans lequel tous les noeuds du réseau sont placés comme noeud maître. Chaque noeud esclave détermine où l'horloge est dépendante en fonction de la priorité d'horloge du noeud maître, la valeur de relais variant avec chaque relais établi par le noeud maître selon une valeur prédéterminée, en fonction de la priorité d'horloge d'un noeud adjacent dans la ligne de transmission dans laquelle le noeud esclave est dépendant et en fonction de la priorité d'acheminement concernant l'acheminement au niveau de ce noeud.
PCT/JP1999/005681 1999-10-14 1999-10-14 Methode de synchronisation-esclave d'horloge et dispositif correspondant WO2001028165A1 (fr)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7580370B2 (en) 2002-06-21 2009-08-25 International Business Machines Corporation Method and structure for autoconfiguration of network destinations
US7769839B2 (en) 2002-06-21 2010-08-03 International Business Machines Corporation Method and structure for autoconfiguration of overlay networks by automatic selection of a network designated router
JP2016165034A (ja) * 2015-03-06 2016-09-08 Ｎｅｃエンジニアリング株式会社 同期ネットワークシステム、通信装置、同期方法、及び同期プログラム

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Publication number Priority date Publication date Assignee Title
US2986723A (en) * 1960-02-26 1961-05-30 Bell Telephone Labor Inc Synchronization in a system of interconnected units
JPH03188724A (ja) * 1989-12-19 1991-08-16 Nec Corp 通信ライン制御方式
WO1995024078A2 (fr) * 1994-02-25 1995-09-08 Nokia Telecommunications Oy Procede de synchronisation hierarchique
JPH11261552A (ja) * 1998-03-09 1999-09-24 Fujitsu Ltd クロック切替装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2986723A (en) * 1960-02-26 1961-05-30 Bell Telephone Labor Inc Synchronization in a system of interconnected units
JPH03188724A (ja) * 1989-12-19 1991-08-16 Nec Corp 通信ライン制御方式
WO1995024078A2 (fr) * 1994-02-25 1995-09-08 Nokia Telecommunications Oy Procede de synchronisation hierarchique
JPH11261552A (ja) * 1998-03-09 1999-09-24 Fujitsu Ltd クロック切替装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7580370B2 (en) 2002-06-21 2009-08-25 International Business Machines Corporation Method and structure for autoconfiguration of network destinations
US7769839B2 (en) 2002-06-21 2010-08-03 International Business Machines Corporation Method and structure for autoconfiguration of overlay networks by automatic selection of a network designated router
JP2016165034A (ja) * 2015-03-06 2016-09-08 Ｎｅｃエンジニアリング株式会社 同期ネットワークシステム、通信装置、同期方法、及び同期プログラム

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