WO2001028165A1

WO2001028165A1 - Clock slave-synchronizing method and clock slave-synchronizing device

Info

Publication number: WO2001028165A1
Application number: PCT/JP1999/005681
Authority: WO
Inventors: Tsuyoshi Matsumoto; Hidetoshi Amari
Original assignee: Fujitsu Limited
Priority date: 1999-10-14
Filing date: 1999-10-14
Publication date: 2001-04-19

Abstract

A clock slave-synchronizing method and clock slave-synchronizing device for placing a node having the second highest priority as the master node if the current master node fails or the communication line fails by setting the clock priority which determines the order in which all the nodes in a network are placed as the master node, wherein each slave node determines where the clock is dependent based on the clock priority of the master node, the relay value varying with each relay set by the master node by a predetermined value, the clock priority of an adjacent node in the transmission line on which the slave node is dependent, and the route priority concerning the route at the node.

Description

Assassin

TECHNICAL FIELD The present invention relates to a clock-dependent synchronization method and a clock-dependent synchronization device.

The present invention relates to a clock-dependent synchronization method and a clock-dependent synchronization device, and more particularly to setting a node as a master node for all nodes in a network to prevent a failure of a current master node and a communication channel. The present invention relates to a clock-dependent synchronization method and a clock-dependent synchronization device in which, when a failure or the like occurs, a node having the next highest value of 1S¾g transitions to a mass node. Background art

In a network composed of a plurality of nodes, each node has ^ fejg (hereinafter, referred to as "clock ^^"), which is a ranking related to a clock, and has one of tii own clocks ^ in the knitting network. The clock-dependent synchronization method in which the highest node becomes the master node that supplies the clock to the entire network and the other nodes become slave nodes is known from ^.

The IUi nodes exchange data including the clock priority with each other to determine the master node. In addition, the slave node is subordinately synchronized with the master node clock.

Conventional clock-dependent synchronization: will be described with reference to FIGS. 1 and 2.

The network shown in the figure includes nodes 10 to 15, clock sources 50 to 52, and transmissions 30 to 43.

Nodes are classified into nodes 10, 12, and 14 having master clock sources 50, 51, and 52, respectively, and nodes having no clock source. As shown in the figure, each node is assigned a number corresponding to the clock rag.

Nodes 10, 12, and 14 with master clock sources 50, 51, and 52 are numbered lower than nodes without a clock source. Since the priority number is / J and the clock is higher, the nodes 10, 12 and 14 with the master clock source 50, 51 and 52 have the higher clock. Than a node without a source The clock is set high.

Also, there is a difference in clocks between nodes 10, 12, and 14 having master clock sources 50, 51, and 52, and a difference in clocks between nodes without a clock source. There is.

In FIG. 1, since the node with the lowest frequency is node 10, node 10 becomes the master node in the network of FIG. 1 and supplies the clock source to the other nodes 11 to 15. I have. In addition to the clock, the difficulty number # 1 of the master node 10 is also indicated as shown in the figure. Therefore, it is possible to know which node is the master node from the priority number of the master node given in {5}.

However, as shown in Fig. 2, when the master node 10 (degree number # 1) stops functioning as a clock source due to a failure or the like, it has the next highest clock priority number (# 2). Node 50 transitions to the master node, and its priority number # 2 flows on the communication path.

That is, for example, if a failure of the master node or the like occurs and the ^: degree number of the master node is no longer received from the communication path, the adjacent nodes 11 and 15 become temporary master nodes. And sends out the number of the node. On the other hand, each node compares the obtained clock rate with its own clock rate, and if the node's clock ^ t degree is larger, it becomes a master node, and if it is lower, it becomes a slave node.

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Eventually, as shown in FIG. 2, the node 14 having the highest clock priority other than the node 10 becomes the master node, and the system is maintained.

Also, as shown in the figure, the master node always sends a sequence number (S) that changes every cycle to the communication path. In each slave node, the experiment of the sequence number is checked. The node that detects that the sequence number of a certain route has lost its flexibility stops the subordination of the clock to that route, becomes a temporary master node, and sends its node's ^; degree number. Then, the node is extracted again.

The absence of the master node can be detected from this sequence number. For example, if the master node bypasses the feit road and is disconnected from the it road, The ^ fe frequency number of the master node goes around the network. However, each slave node can detect the absence of a master node by detecting the continuity of sequence numbers.

In addition, in a complicated network such as a mesh network, when switching of dependents occurs, a clock path may form an independent loop, and clock sources may exist separately in the network. At this time, slips occur in the memory used to synchronize information frames, and the slippage occurs due to the difference between the speed at which the received information is written and the speed at which the received information is read out, and the lack or overlap occurs. I do. Therefore, the occurrence of a slip error or the like is prevented by checking the nature of the sequence number.

In a mesh network, the network configuration may be operated in a complex mesh (lattice) state. In order to configure the clock path from the master node in a uniform manner, each node is artificially operated. This was achieved by providing a code patch (hard switch) function to the system and forcibly creating a clear clock path.

The problem to be solved by the present invention will be described with reference to FIGS.

(1) According to the conventional technology, the absence of a master node and the elimination of! 3 loop formation can be performed by setting a clock number and a sequence number. In a complicated network, if the master node transitions or the switching of the dependent i-paths occur frequently due to clock disturbances, etc. From the viewpoint of resources, the clock path from the master node does not always form an appropriate tree shape. This is because the number of relay stages of the clock path cannot be determined by the sequence number.

As shown in FIG. 3, when a failure occurs in the communication paths 30 and 39 at two locations, a clock path is formed as indicated by a dotted line in the figure. Even if the failure on the communication feii path is restored, the clock path does not change, as shown in Figure 4. The communication transmission path dependent on the occurrence of the failure (in the figure, the communication path 43 between the nodes 11 and 14 and the communication path 38 between the nodes 12 and 13) is represented by P This is because even if chapter damage is restored, it looks normal. In FIG. 1, the number of relay stages up to node 13 is "2", whereas in FIG. 4, it is "4". In this way, as a result of frequent occurrences of master node transitions and subordinate fei-path switching, the number of relay stages in a multistage relayed clock path (in extreme cases, a write clock path) increases, so the clock jitter component increases. May increase, causing problems

In addition, when the number of relay stages increases, the time required to detect a clock abnormality, that is, a transition of the master node or a sequence error, becomes longer. In other words, the disturbance SR bundle time in the entire system becomes longer. However, depending on the required specifications of network characteristics, time reduction is required, and this is a problem.

(2) The above-mentioned problem (1) may be improved by a code patch function for artificially forming a clock path. However, there is a problem that it is difficult to respond flexibly due to changes in the network configuration due to human intervention. Therefore, hardware automation is required. Disclosure of the invention

The clock dependent synchronization method of the present invention comprises a plurality of nodes having clock degrees, and each node transmits and receives data including the clock degree, thereby providing the highest level of the self-clock ^ fc degree. The self node becomes the master node that supplies the clock to the entire network, and the other 1JI self node sets the relay value to | If the received relay numerical value is larger or smaller than the predetermined value at the slave node, it synchronizes with the route where the received relay numerical value is smaller or smaller, and Decreasing or increasing a predetermined number of it relayed values of the received edited data to an adjacent node.

A clock dependent synchronization method according to the present invention comprises the steps of: setting a relay value in the master node and transmitting the data; and, if the received relay value is larger than a predetermined value, receiving the received value. Synchronize with the feit path where the medium fiber value is large, further reduce the relay value of the received it's own data by a predetermined number, and fSt to the adjacent node, or the number of relays received at the slave node If the value is smaller than the predetermined value, a step of synchronizing the received data with a small relay value with the feited transmission line, further increasing the relay value of the received data by a predetermined number, and feiiing the adjacent node. Each slave node determines the slave of the clock based on the clock level of the master node and the relay value set by the master node and increased or decreased by a predetermined value for each relay.

Further, the clock dependent synchronizer of the present invention is composed of a plurality of nodes having a clock ^^, and ii each node transmits and receives data including the clock ^^, so that the clock is synchronized with the clock ^^. The relay node, the master node, becomes the master node that supplies the clock to the entire network, and the other it nodes, in the clock-dependent synchronizer in the network that becomes the slave nodes, are the relay values set by the jf master node. If the received relay value is larger or smaller than the specified value, and the received thigh value is larger or smaller than the specified value, 受信 ≤ a processing unit for synchronizing with the clock of the channel, further reducing or increasing the il-self relay value of the received il-self data by a predetermined number, and transmitting the reduced value to an adjacent node.

The clock-dependent synchronizer according to the present invention includes: a receiving unit that receives data including a relay value set by a master node; and a receiver that receives a larger relay value when the received medium fiber value is larger than a predetermined value. In the event that the evening is synchronized with the clock on the fei path, the relay value of the received data is reduced by a predetermined number and sent to the adjacent node, or if the received medium fiber value is smaller than the predetermined value, A processing unit for synchronizing with the clock of the iSi path on which the received relay value is small, and further increasing the relay value of the received data by a predetermined number and transmitting the data to an adjacent node; Determines the subordinate of the clock based on the master node clock ^^ and the relay value which is set by the master node and increased or decreased by a predetermined value for each relay. BRIEF DESCRIPTION OF THE FIGURES

Other objects, features and advantages of the present invention will become more apparent from the following description, read in conjunction with the accompanying drawings.

Figure 1 shows the conventional technology, and the clock in a steady state of the network. FIG. FIG. 2 is a diagram illustrating a state of a clock path when a failure occurs in a master node according to the related art.

FIG. 3 is a diagram showing a state of a clock path when a road failure or the like occurs in the conventional technology.

FIG. 4 is a diagram illustrating a state of a clock and a clock at the time of recovery from a path failure or the like according to the related art.

FIG. 5 is a diagram illustrating the principle of the present invention.

FIG. 6 is a configuration diagram of the entire network in the embodiment of the present invention.

FIG. 7 is a diagram for explaining the clock dependent synchronizer of the present invention.

FIG. 8 is a diagram showing an example of a block configuration of a CPID (CPID: C1OckPriorityID) processing unit in the embodiment of the present invention.

FIG. 9 is a diagram showing a CP ID and a cell ZCP ID frame in the embodiment of the present invention.

FIG. 10 is a diagram showing an example of a block configuration of the clock interface unit in the embodiment of the present invention.

FIG. 11 is an operation flow of the CPID processing unit.

FIG. 12 is a diagram showing a flow of a clock path during normal operation in the embodiment of the present invention.

FIG. 13 is a diagram (part 1) illustrating a flow on a clock path at the time of failure in the embodiment of the present invention.

FIG. 14 is a diagram (part 2) illustrating a flow in the clock path at the time of failure in the example of the present invention.

FIG. 15 is a diagram (part 3) illustrating the flow on the clock path at the time of failure in the embodiment of the present invention.

FIG. 16 is a diagram (part 4) illustrating a flow in the clock path at the time of failure in the embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

The US of the present invention will be described with reference to FIG. In order to solve the above-mentioned problem, the present invention provides a node relay stage number (here, NRID: Node Relay 10) which is a relay numerical value instead of the sequence number employed in the conventional technology. In the figure, NR is described.) Only the node (10 in Fig. 5) that became the master node communicates with the NR ID based on the predetermined initial value. To send to.

The node that has become the slave node compares the NR IDs received from multiple communication feit routes, andきレ同期に従属値値属属属属値値値値値値値値値値属属に従属値値値値してして属してしてしてしてしてしてしてして己してして雄してSend it to the i¾t route. Also, it does not depend on the fei road whose NRID value is "0". Further, when the NRID value from the route that has already been subjected to the slave synchronization changes to “0”, the slave is suspended from the route, and the NR IDs received from other multiple communication {5} routes are compared. Synchronizes with the clock from the communication channel with the largest value.

The initial value of the NRID value is set in advance by the master node (10 in FIG. 5). This value may be set to a value greater than or equal to the value of the relay stage to the farthest node in the network. For example, in the case of the network shown in Fig. 5, when the communication fei path 30 and the communication feit path 39 fail, the relay stage value to the farthest node 13 is 4, so the master node 10 uses the NRID value as the NRID value. Set a value of 4 or more. As a result, each of the nodes 11 to 15 has a large NR ID value and can depend on the clock of the route. As a result, a clock path that minimizes the number of relay stages from the master node can be configured.

Instead of decrementing the NRID value, you may increment it. In this case, the slave synchronizes with the clock from the communication channel having the smallest value and the value from the channel, and increments the value of NR ID before sending it to the communication channel.

Also, depending on the network configuration, there may be insufficient information on which clock should be synchronized with the NR ID value of the UI itself. For example, if a slave node has a communication fe path with the same number of relay stages from the master node, it is not possible to determine which path is good if it depends on which path. Therefore, a method of transmitting the clock ^ t degree value of the opposite station to the communication feit path (the clock degree value of the opposite station is referred to as NP ID: Node Priority ID. In the figure, it is described as NP.) Is adopted. each If the result of comparing the NR IDs input from multiple communication i-channels matches, the slave node then compares the NP ID values and subordinates to the route with the higher degree. For example, in the node 14, since the NR ID value of the clock from the communication Si path 42 and the NR ID value of the clock from the communication path 40 are the same, it is not possible to determine which of the paths depends on the path. Therefore, look at the NP ID value. Communication {Since the NPID value from the communication path 42 is 102, and the NP ID value from the communication path 40 is 101, in this case, the node 14 Synchronizes with the clock from 0.

In this way, if the NR ID value alone is not sufficient, depending on the network configuration, adopting the NP ID value allows the NR 1 D value to be the same regardless of whether the NR 1 D value is equal between the receiving and receiving routes. Can be determined.

Also, depending on the configuration of the network, there may be a shortage of information on which route clock should be synchronized only with the NR ID value and NP ID of its own. For example, if multiple communication feit routes are connected between a certain node, the NR ID value and NP ID value are equal, so it is difficult to know which route to use. In each node, ^: degrees are provided for each route unit, the route ^ t degrees is high, and the route is dependent on the route.

With this, if the NR ID value and NP ID value alone are not enough according to the network configuration, setting ^^ for each route will temporarily make the NR ID value and NPID value equal between the receivers. In any case, it is possible to determine which route to follow.

In addition, each node compares the values between the links for the clock ^ t degree, NR ID, NP ID, and the path ^ degrees in order to determine which route clock should be synchronized. A comparison unit is provided. This comparison unit compares the clock received from each communication channel with the NR ID value (the ratio ra i) and the clock priority, NR ID, NP ID, and the route type. Prepare a block (comparing unit 2) to switch the ratio according to the conditions.

When searching for which route should be used, such as when starting up a network, use the lUIfii comparator 2 to determine the optimal route. Once the route is determined, switch to the comparison unit 1 and compare the clock ^: degree and only when the NR ID value is the lowest. To ¾m.

Thus, by switching the ratios ran and 2 depending on the conditions, it is possible to suppress the switching of an undesired route. For example, if a subordinate is dependent on a certain route and an alarm or the like is detected for that route, the subordinate to that route is stopped, another route is searched, and subordinate synchronization to the optimal route is established. . After that, when the alarm of the jf own route is recovered, if all of the clock ^: degrees, NR ID, N P ID and route priority are used as the comparison and contrast, dependent synchronization is re-established for the MI own route. This is called switchback. Depending on the requirements of the network, it may be desirable to suppress this switchback. According to the present invention, when the vehicle is dependent on a certain route, unnecessary switching back can be suppressed by using the ratio ∞1.

Hereinafter, the details of the invention will be described based on embodiments shown in the drawings.

The switching of the master node in the system is performed at a preset Δt degree. Therefore, before starting operation, set the clock of the master clock for all nodes. This ^ feS information (hereinafter referred to as r ^ fcJt information) is transmitted to the communication channel on the network, and at each node, the ^ feS information received from the communication feii channel is set to the local node. If the own node has a higher degree, it becomes a master node, and thereafter sends its own degree information. If information with a higher priority than the own node is input from the communication transmission line, the slave node becomes a slave node that synchronizes dependently on that route. The slave node sends priority information from the route performing slave synchronization to each route, so that the degree information is distributed to all nodes in the network, and the relationship between the master and the slave in the network is established. Holds. This is the basis of ^ information in the present invention: ^.

Figure 6 shows a configuration example of the entire network. In this embodiment, an ATM network configured in a mesh shape is assumed, and in the figure, an ATM node including four ATM devices is connected by a transmission path. The inside of the ATM device is basically composed of a cell switch section 65 and a CPID processing section 64. The cell switch section 65 refers to a VPI (virtual path identifier) in the ATM cell header and sets a preset table. Switching based on information. There are seven ports, numbered 0-6.

FIG. 7 shows the clock-dependent synchronizer of the present invention in the ATM device of FIG. It is shown together with the interface section.

FIG. 7 shows a cell switching section 65, a switching table 111, line interface sections 110 and 112, a CP ID processing section 64, and a clock interface section 114.

The cell switching unit 65 and the CP ID processing unit 64 are the same as those shown in FIG.

The cell switching unit 65 switches the ATM cell with reference to the switching table 111. The line interface units 110, 112 take an interface between the fe route and the cell switching 65. The CP ID processing section 64 includes a CP ID cell insertion section 85, a CP ID cell extraction section 86, a CP ID decellularization section 74, a CP ID cell conversion section 83, and a CP ID arbitration section 87. The CP ID processing unit 64 extracts a power \ CP ID cell, which will be described in detail later, compares the CP ID, NR ID, NPID, and route, and determines whether the node is a master node or a slave node. Based on the result, a source clock selection signal is output, and a CP ID cell for another node is generated. The clock interface unit 114 is composed of an oscillator 10 and a PLL reference clock selection unit 113 and a PLL circuit 103. Based on a source clock selection signal from the CP ID processing unit 64, an external クロック ^ clock is used. And its own clock 101 and output? And applied to the circuit 103. The output of the PLL circuit 103 becomes the internal operation clock.

FIG. 8 is a block diagram showing the processing of CPID in each node. This figure corresponds to the CP ID processing unit 64 in FIG. The CP ID cell identification unit 71, which identifies whether or not the cell from the cell switching unit is a CP ID cell, sets the expected VPI value of the received cell and sets the transmission VPI value. It has been done. The CP ID cell identification unit 7 K VPI setting register 72 and the VPI comparison unit 73 correspond to the CP ID cell extraction unit 86 in FIG.

In addition, a de-serialization unit 74 for decelerating and assembling a CP ID frame is provided for each port; a CP ID ratio crane 75 for comparing and judging each bit of the CP ID frame, a NR ID comparison unit 76, NP ID ratio 鄉 77, and route comparison unit 78 are provided. Further, a frame unit 81 that assembles the CP ID frame of the own node based on the values set in the own node CP ID setting register 79 and the NR ID setting register 80, the CP of the received CP ID frame and the CP of the own node CP ID frame. A master / slave determination unit 82 that compares ID bits and determines whether the own node becomes a master node or a slave node is provided.

Decelerating unit 74, CP ID comparing unit 75, NR ID comparing unit 76, NP ID comparing unit 77, and route ratio ¾¾U78, own node CP ID setting register 79, NR ID setting register 80, frame ffiS: unit 81, E Z slave determination unit 82 force \ Corresponds to CP ID arbitration unit 87 in Fig. 7.

In addition, the finalized CP ID frame is converted to a cell by the celling unit 83, the transmission VPI value is inserted by the VPI input unit 84, and then the CP ID cell identifier is inserted again for transmission to the cell switch unit A CP ID cell identifier insertion unit 85 is provided.

In the switch-back mode described later, the subordination is determined based on the CP ID comparison unit 75, the NR ID comparison unit 76, the NP ID comparison unit 77, and the route comparison unit 78. On the other hand, in the non-revertive mode, the ability to determine subordination based on the CP ID ratio 75 \ Even if the NR ID value becomes 0, subordination to that route is stopped, and the NR ID comparison unit 76 and NPID The subordination is determined based on the comparison unit 77 and the route comparison unit 78.

The cell from the path is applied to the CP ID cell identification unit 71, and the register value of the VPI setting register 72 and the VPI value of the CP ID cell are compared by VP \ 3. As a result, in the case of a CP ID cell, it is decellularized by the decellularization unit 74 for each boat. The decelerated CP ID frame is sent to the CP ID comparator 75, the NR ID comparator 76, the NP ID ratio crane 77, and the route comparator 78 for the CP ID, NR ID job, NP ID ^ t, A road-to-degree comparison is made. Set the CPID and NR ID of the own node using the own node CP ID setting register 79 and the NR ID setting register 80. The frame detector 81 sends a CP ID frame based on the values of the own node CP ID setting register 79 and the NR ID setting register 80. The master / slave determination unit 82 is based on the CP ID frame from the frame sensitivity unit 81 and the result of the CP ID ratio ¾¾75, NR ID comparison unit 76, NP IDJtra77, and route comparison unit 78. Master / slave judgment is performed based on, and a source clock selection signal is output. Also, the output of the master Z slave determination unit 82 is converted into a cell in a cell unit 83, a VPI is inserted in a VPI insertion unit 84, and a CP ID identifier is inserted in a CP ID cell identification input unit 85. A CP ID cell is generated.

In this way, the CP ID is converted into an ATM cell and communicated through a path set in the network in advance. As shown in Fig. 6, the path form of the CP ID cell is formed between nodes. In other words, the CP ID cell transmitted from a certain node is switched to the CP ID processing unit in the cell switch unit of the adjacent node, and after the CP ID processing unit performs processing such as a long-term determination, the adjacent node node is re-established. Sent to the server.

Next, FIG. 9 shows the format of the CP ID cell and the CP ID frame. The CPID cell is a signal feiied between each node. The header part of the CP ID cell is composed of 5 bytes, and is composed of address information such as VPI and VCI. A code for identifying the CP ID cell is added to the upper 3 bits of VC I, and this code identifies whether the cell is a CP ID cell. The actual CP ID frame is embedded in the 48 bytes of the information field, and is composed of CP ID / NR ID / NP ID information, respectively. Finally, the “P” in {is the parity bit, which is used to check the normality of the data.

A portion where the information field of the CP ID cell is extracted becomes a CP ID frame, and various priority determinations are performed by a CP ID determination unit.

FIG. 10 shows an example of a block configuration of the clock interface unit 114. The master Z slave determination unit in FIG. 8 outputs a source clock selection signal. This signal is used in FIG. 10 as a signal for determining which of the clock extracting unit 100 for extracting a clock from the ¾ path and the clock source 101 should be selected. Specifically, the source clock selection signal is input to the source clock selection unit 102, and it is determined whether to select the clock from the feit path or the source of the own node. It is input as the source clock of the reference clock of the filter 103. The output clock of the PLL unit 103 is transmitted to the fei path via the operation clock in the device and the clock insertion unit 104. In this way, the CP ID is ^ determined, which clock should be subordinate to which ^ path, and a clock path is sequentially formed.

Next, two transfer modes of the priority information transfer, a mode with switchback and a mode without switchback, will be described. In the switchback mode, the node repeater number (NR ID) and the opposite station clock ^^ degree number (NP ID) are used in addition to the clock ^ fc degree information, so that the clock path The clock path can be looked at and optimized so that the number of relay stages is always minimized. However, after the failure of the fei road and the rebuilding of the clock after rebuilding the clock, switching back to the previous clock path will occur.

In contrast, non-revertive mode is a mode in which the currently configured clock path is always maintained. If the fault occurs on the iSi path through which the clock path passes, switching of the subordinate path occurs, but no failback occurs when the fault is recovered. Failure occurrence When Z recovery is repeated, it is not possible to identify what kind of clock has been finally constructed, and in some cases, the number of relay stages has increased, and the clock component has increased. It is feared that.

Next, a specific operation will be described.

FIG. 11 is a flowchart showing the operation of the CP ID processing unit 64. The operation will be described with reference to FIG. 8 corresponding to the steps.

The CP ID defines a value up to 1 255, with 1 being the highest priority. If it is 0, the degree is the smallest.

Each node receives the CP ID frame from the decelerator 74 (S101). The CP ID of the CP ID frame received from the feii path is compared with the CP ID of its own node (S103 S104), and the highest priority value is assigned to the cell unit 83 VPI insertion unit 84 CP ID cell identifier Transmitted to each transmission path via the insertion unit 85 (S117) o

If the CP ID value of the CP ID frame received from each fe path is smaller than the own node's CP ID value, the own node becomes the master node and sends the own node's CP ID to each iSt path ( S 105 S 109).

As described above, the NR ID is a number indicating the number of relayed CP ID frames to the node. This is a lock relay stage number signal. The master node sends out the NR ID value set in its own node to each i¾t route (S106, S110). The slave node decrements the NRD value received from the dependent ^! Route by "1" and sends it to each route (S108, S113).

NP ID indicates the CP ID of the opposing node as described above.

In addition, the operating principle of clock dependent synchronization using Ranki CP ID frames will be described.

Since the operation at each node differs depending on the mode, the description will be given for each mode.

Each CP ID processing unit compares in the following order.

(1) Comparison of CP ID values (processing with CP I Di 5 in Fig. 8: S103, S104)

Compare the CP IDs received from each route and use the lowest value. After selecting the highest CP ID, the master / slave determination unit 82 shown in FIG. 8 compares it with its own node's ^ t degree number, and if its own node's ^ t degree is higher, it performs clock master operation. Switch, if the CP ID value from one route is high, subordinate to that route

(2) Comparison of NR ID value (processing in NR ID comparison unit 76 in Fig. 8)

In the case of the mode with switchback, if the CP1D values are equal, then the CR ID values are compared (S107). NR 1 D is decremented each time CP ID passes through the node, and a node receiving “0” does not depend on the corresponding route. Since the initial value of NR ID is determined in advance at the time of transmission, the higher the value, the smaller the number of times the node has passed. Therefore, the highest value is adopted and it depends on the route.

In the non-revertive mode, if the route is dependent on a certain route, NR ID comparison is not performed, and only reception monitoring of "0" of the dependent route is performed (S114). However, when determining the route, the NR ID values are compared as in the switchback mode (S I 12).

(3) Comparison of NP ID values (processing in NP ID comparison unit 77 in Fig. 8)

In the switchback mode, if the CP ID and NR ID are equal, the NP ID value indicating the priority number of the opposing node is compared (S107), and the lowest value is adopted. I do. Depending on the form of the network, it is quite possible that the values of CPID and NR ID will be the same.Therefore, one route is determined by notifying the ^ fc degree number that is uniquely determined in the network between the opposite nodes. To determine.

In non-revertive mode, NP ID values are not compared and this area is ignored. However, when determining the route, the NR ID values are compared in the same manner as in the mode with switching back (S112).

(4) Route priority (Processing in route comparison unit 78 in Fig. 8)

In the case of a dual-fe route, etc., if there is a case where two or more roads are connected between a certain node, it is considered that all of the knit values are the same. Therefore, the priority of the route is defined in advance, and the dependent route is determined accordingly. With the above operation US, the master-slave operation is determined, and a complete path is established from the master node.

The above operation examples are shown in Figs.

It is composed of nodes 120 to 128, and external clocks 130 and 131 are surrounded by nodes 120 and 128.

In the figure, the number in parentheses is the clock ^^ number. The shaded node is the master node, and the route indicated by: ^ is the clock path (each node is subordinate to the route marked). Information flowing through each communication transmission line is shown in the figure, and the initial value of NR ID is set to "5".

Figure 12 shows the flow of the clock path during “normal operation” when the fault occurs between node 120 and node 121 (“feit failure occurs (1) J). FIG.

FIG. 13 illustrates how the clock path is switched in the case of “fe¾ fault occurrence (2)” in which a fault has occurred between the nodes 120 and 123.

FIG. 14 illustrates the switching of the clock path when the master node transitions from the node 120 to the node 128 due to the failure of the external clock source 130. When an external clock failure occurs in the node 120, as in the node 120 in FIG. 14, the power number automatically changes (001 → 101).

Figures 15 and 14 assume a duplicated fei road in a mesh network. The priority number of the route is added to each route.

Figure 15 shows “The flow of the clock path during normal operation j is shown.

In the node 1 2 1 etc., the CP ID, NR ID and NP ID are the same between the node 1 and node 2 0, but the dependent synchronization destination is determined by the route number.

Figure 16 shows the flow of the clock path in the event of a failure between nodes 120 and 121.

According to the present invention, even in such a complicated network form, the clock path is switched to a clock path that forms an appropriate grid and minimizes the number of relay stages even if a failure in the communication channel occurs. be able to.

As described above, according to the present invention, a clock path can be constructed even in a complicated network configuration such as a mesh network. By limiting the initial value of the number of relay stages, the number of relay stages in the clock path can be reduced, and an increase in clock component can be prevented.

In addition, by switching the ratio of the number of clock relay stages and the ratio of opposing node numbers, it is possible to suppress undesired switching due to disturbances, etc., and to reduce power and inevitably cause switching. In other words, it is possible to determine the optimum route as the switching destination route.

According to the present invention, the code patch function by an artificial operation, which has been a problem in the technique of (1), is inevitably eliminated according to the present invention, and contributes to the improvement of network quality.

The present invention is not limited to the specifically disclosed embodiments, and various modifications and embodiments can be considered without departing from the scope of the claimed invention.

Claims

The scope of the claims

1. Each node is composed of a plurality of nodes having a clock degree, and each of the nodes exchanges data including the clock degree, thereby obtaining the highest level of the clock degree. Node becomes the master node that supplies the clock to the entire network, and the other ri nodes become the slave nodes.

(ii) At the master node, the relay value is set in the IUI data and transmitted.

In the case of the Tsurumi slave node, if the received relay value is larger or smaller than a predetermined value, the received relay value is synchronized with the transmission line on which the larger or smaller data is transmitted, and if Reducing or increasing the relay value by a predetermined number to make it an adjacent node;

A clock dependent synchronization method comprising:

2. In the clock ¾έΜ synchronization method according to claim 1,

Furthermore, in the S slave node, a clock dependent synchronization method including a step of setting the clock of the own node to the autonomous clock and feathering to an adjacent node.

3. In the clock dependent synchronization method according to claim 1,

Further, a clock slave synchronization method including a step of setting a route, which is a degree of slave synchronization, for each route, when a plurality of routes are provided in the self-serving slave node.

4. In the dependent synchronization method according to claim 1,

| 1H At the slave node,

Determining a subordinate based on the master node's it value and the relay value;

it's own clock node i clock ^^, it's relay value, subordinate 隣 next to the road Determining the subordinates based on the degree of contact of the node in contact with it and the degree of UI self-direction

One of the above two steps

A clock dependent synchronization method comprising:

5. It is composed of a plurality of nodes having clock ^ ά, and each node sends and receives data including clock ^ t, so that il's clock has the highest clock ^ 度. If the own node becomes the master node that supplies the clock to the entire network, the other it node becomes the slave node.

A receiver that receives the knitting data including the relay value set by the knitting master node, and if the received medium fiber value is larger or smaller than a predetermined value I, the received relay value is larger or smaller. And a processing unit for synchronizing with the clock of the fS path subjected to iS, further reducing or increasing the self-relay value of the received it self data by a predetermined number, and transmitting the same to the adjacent node.

Clock-dependent synchronization device with

6. The clock-dependent synchronizer according to claim 5,

A clock-dependent synchronizer having a processing unit that sets the clock tt degree of the node where the clock-dependent synchronizer is provided to lf self-data, and performs processing to an adjacent node.

7. The clock-dependent synchronizer according to claim 5,

In the case where the node provided with the click slave synchronizer has a plurality of routes, a clock having a processing unit for setting 方 the degree of ^ 1 degree of route ^ fc degrees for each route for each route Dependent synchronous equipment go

8. The clock-dependent synchronizer according to claim 5,

a first ratio that determines the subordinate based on the n master node and the mi relay value of the na master node; and Dependency is determined based on the degree of the master node, the degree of lf relay, the value of the slave node, and the degree of the slave node adjacent to the route. A second comparing section,

Clock slave synchronization device that selects one of the comparison units and performs clock slave synchronization