Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
  • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
  • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
  • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
  • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
  • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
  • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
  • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
  • G06F11/1032—Simple parity
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
  • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
  • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
  • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
  • G06F11/1056—Updating check bits on partial write, i.e. read/modify/write

Definitions

• the invention relates to a method and a circuit arrangement for storing data words in a RAM module, in particular for safety-critical applications.
• RAM Random Access Memory
• RAM Random Access Memory
• the invention is therefore based on the object of providing a method and a circuit arrangement for storing data words in a RAM module, the space requirement of which is considerably smaller, without any restrictions with regard to data security having to be accepted.
• a method which is characterized by the following steps: generating a check bit word from at least one data word when writing the at least one data word into the RAM module, storing the check bit word, reading out the check bit word when reading out the at least one data word from the RAM module, generating the check bit word again from the at least one read out data word, comparing the read out check bit word with the newly generated one Check bit word and generate an error message if they do not match.
• the object is further achieved with a circuit arrangement which is characterized by: a first circuit unit for generating a test bit word from at least one data word when writing and reading the at least one data word, a number of registers for the associated storage of test bit words for the data words, as well as a second circuit unit with which the associated check bit word is compared with the check bit word generated by the first circuit unit when reading data words, and for generating an error message if the check bit words do not match.
• a particular advantage of this solution is that with essentially the same data security as in the fully redundant design mentioned at the outset, the required silicon area and thus also the circuit complexity and the costs are significantly lower.
• FIG. 1 shows a schematic representation of a first memory architecture
• FIG. 5 shows a schematic representation of a second memory architecture
• a RAM module essentially comprises a word-oriented array 10 consisting of a number of 32-bit data word registers 10a,... 10i,... 10x, which are shown arranged in rows one below the other.
• a 2-bit parity word register 11a, ... lli, ... llx is assigned to each data word register, so that a 2-bit parity array 11 results.
• a 32 bit parity word register 12 is provided, which in turn is assigned a 2 bit parity word register 13.
• this arrangement is connected in a known manner to a bus interface unit 14, via which a connection to a CPU bus can be established.
• the bus interface unit 14 furthermore comprises circuit units for generating and for comparing the parity words during write and read processes, which are shown in FIGS. 2 and 3.
• the relevant data words are led from a 32 bit data bus 20 to a first circuit unit 21 according to FIG. 2, with which a 2 bit parity word is generated for each data word.
• the data word is then written into one of the data word registers lOi in the RAM module and the 2 bit parity word into the assigned 2 bit parity word register lli.
• the addressed data word is first transferred to the first circuit unit 21 according to FIG.
• the assigned 2-bit parity word is transmitted to a second circuit unit 22.
• a 2-bit parity word is in turn generated from the read data word, which is transferred to the second circuit unit 22 and compared there with the 2-bit parity word read directly from the RAM module. If these two words do not match, an error signal F is generated or a corresponding error flag is set. If the 2-bit parity words match, the data word read out is transmitted to the data bus 20.
• each 32 bit data word is composed of a first and a second 16 bit half word HW, whereby a bit B of the 2-bit parity word is generated from each halfword.
• the 2-bit parity generation can also be replaced by a CRC (cyclic redundancy check) check with a CRC word calculated for each data word according to a polynomial.
• the memory architecture is chosen so that the width of the stored data words (memory words) is a multiple of the width of the data words on the data bus.
• the memory word preferably has a width of 128 bits and the CRC word has a width of 9 bits for optimum error security.
• FIG. 5 shows a corresponding arrangement which is connected to a 32-bit data bus (not shown) via the bus interface unit 14.
• the RAM module comprises an array 60 from a number of 128 bit memory word registers 60a,... 60x, which are shown arranged in rows one below the other. Each memory word register is assigned a CRC register 61a,... 6lx, each with 9 bits, for example, so that a CRC array 61 results.
• a unit 70 is connected between the array 60 and the bus interface unit 14, which has a multiplexer 71 for four 32 bit data words and a 128 bit CRC computation register 72 for receiving four 32 bit data words.
• the unit 70 further comprises a CRC arithmetic unit 73, with which a 9 bit CRC word is calculated from the content of the 128 bit CRC arithmetic register 72 using known arithmetic methods and is temporarily stored in a 9 bit CRC register 74, which in turn is stored on the bus - Interface unit 14 is connected.
• a CRC arithmetic unit 73 with which a 9 bit CRC word is calculated from the content of the 128 bit CRC arithmetic register 72 using known arithmetic methods and is temporarily stored in a 9 bit CRC register 74, which in turn is stored on the bus - Interface unit 14 is connected.
• an error check is to be carried out before writing a new 32-bit data word, which can be initiated, for example, by software with certain time intervals, the content of the relevant 128-bit memory word register 60i and the content of the assigned CRC- Register 61i read out.
• the 9-bit CRC word is then generated from it again with the CRC arithmetic unit 73 and compared with the CRC word read out. If these two CRC words do not match, an error signal F (or a corresponding error flag) is generated.
• a new 9 bit CRC word is calculated from the new 32 bit data word containing the 32 bit data word, and both are transferred to the corresponding 128 bit memory word register 60i or the assigned 9 Bit CRC register 61i of the RAM module read.
• the error check can also be carried out if a data word is to be read from the RAM module onto the data bus 20.
• the content of the memory word register 60i containing the relevant data word is transferred to the CRC arithmetic register 72 and the CRC word is calculated from this again.
• This CRC word is stored in the associated CRC word register 61i CRC word compared. If the two words do not match, an error message F is generated or a corresponding error flag is set. If both CRC words match, the 32-bit data word read out is transmitted to the data bus 20.
• the content of the CRC arithmetic register 72 is then fed back into the corresponding 128 bit memory word register 60i.
• FIG. 6 shows a number of memory word registers 10a, 10b,... LOx, for 32 bit data words and a 32 bit parity word - register 12, a bit with the value 0 or 1 being shown as an example for each position.
• a column-oriented parity is generated in accordance with FIG. 6, in which a parity bit is determined for the same positions of all data words, which is assigned to an assigned position in the 32-bit parity word Register 12 is registered. This results in a 32 bit parity word. Furthermore, a 2-bit parity word can now be generated for this 32-bit parity word in the same way as described for the word-oriented parity with reference to FIG. 4 and stored in the 2-bit parity word register 13 (see FIG. 1). According to the manner described above, a column-oriented parity check can also be carried out in the embodiment according to FIG. 5 with 128-bit data words.
• the content of the data word of the memory location to be written in the RAM module ie a 32 bit data word register lOi in the example, and the 32 bit parity word register 12 are read out.
• the value of the column-oriented 32-bit parity word is then determined again and described.
• the new data word is then written back into the corresponding data word register 10i and the content of the 32 bit parity word register 12 is newly determined. Subsequently, a 2 bit parity can again be generated for the 32 bit parity word and stored in the 2 bit parity word register 13 (see FIG. 1).
• An error check is preferably not carried out during a normal read operation.
• An additional error check can be carried out by reading out the contents of all data word register 10i, for example at the time during a read operation, generating the column-oriented 32 bit parity word again and using the in the parity word stored in the parity word register 12 is compared. If the parity words do not match, an error message F is generated or a corresponding error flag is set. If the parity words match, the read data word is transferred to the data bus 20.
• the embodiment described here for column-oriented error checking in the entire RAM is expediently not carried out with every write or read operation, but with certain time intervals, whereby the time intervals can be predetermined by the software used. The decision whether this Error checking or not, is preferably done by the software used.
• the 2 bit parity word of the 32 bit parity word can be used for error checking in the same way as was described with reference to FIGS. 2 to 4 for the 2 bit parity words of the data words.
• a column-oriented CRC Cyclic Redundancy Check
• the content of all data word register 10i and the check bit register 12 is first read out and the CRC word is determined again. If this CRC word does not match the stored CRC word, an error message F is generated or a corresponding error flag is set. If both CRC words match, the write or read process is completed in the manner described above for column-oriented parity word generation.

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• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Detection And Correction Of Errors (AREA)
• Techniques For Improving Reliability Of Storages (AREA)

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• 2000
  • 2000-08-29 EP EP00956493A patent/EP1222545B1/de not_active Expired - Lifetime
  • 2000-08-29 JP JP2001525526A patent/JP2004500623A/ja active Pending
  • 2000-08-29 US US10/088,957 patent/US6901552B1/en not_active Expired - Fee Related
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