Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/60—Software-defined switches
  • H04L49/606—Hybrid ATM switches, e.g. ATM&STM, ATM&Frame Relay or ATM&IP
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04Q—SELECTING
  • H04Q11/00—Selecting arrangements for multiplex systems
  • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
  • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
  • H04Q11/0478—Provisions for broadband connections
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04J—MULTIPLEX COMMUNICATION
  • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
  • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
  • H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/54—Store-and-forward switching systems 
  • H04L12/56—Packet switching systems
  • H04L12/5601—Transfer mode dependent, e.g. ATM
  • H04L2012/5629—Admission control
  • H04L2012/5631—Resource management and allocation
  • H04L2012/5632—Bandwidth allocation
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/54—Store-and-forward switching systems 
  • H04L12/56—Packet switching systems
  • H04L12/5601—Transfer mode dependent, e.g. ATM
  • H04L2012/5672—Multiplexing, e.g. coding, scrambling
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/64—Hybrid switching systems
  • H04L12/6418—Hybrid transport
  • H04L2012/6445—Admission control
  • H04L2012/6456—Channel and bandwidth allocation
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/64—Hybrid switching systems
  • H04L12/6418—Hybrid transport
  • H04L2012/6445—Admission control
  • H04L2012/6459—Multiplexing, e.g. TDMA, CDMA

Definitions

• the present invention relates generally to a network element for use in a telecommunications network in which the bandwidth utilized by various signals is dialably managed so as to improve efficiency. This management is selectively performed on an STS, VT, or data cell or packet basis.
• the present invention provides an apparatus and method for efficiently managing bandwidth in a telecommunications network carrying both TDM services and data services.
• bandwidth By efficiently managing bandwidth, network operators are able to save money on capital expenditures for equipment and thereby keep operating costs down. In the highly competitive telecommunications services arena, this provides network operators with a competitive advantage.
• An embodiment of the present invention provides a network element that is outfitted to accept signals from a telecommunications network.
• the signals are then routed to an STS selector that routes the signals to a bandwidth management device.
• the bandwidth management device for each signal being dialably selectable by a network operator.
• the bandwidth management devices include a device for managing signals on an STS level, on a VT level, and on a data packet or cell level.
• the word cell as used hereinafter, shall be understood to mean cell or packet, as the principles of the present invention are as easily applicable to packet-based signals as they are to cell-based signals.
• An embodiment of the present invention provides a network element for managing bandwidth capable of circuit-based multiplexing at and STS-n and a VT-n level and capable of cell-based multiplexing.
• An embodiment of the present invention provides that the device for managing signals at a cell level, manages both the virtual channel and virtual path of ATM cells. It is thus an object of present invention to selectively and effectively manage bandwidth utilized within telecommunications networks having both circuit-based and cell-based traffic.
• Figure 1 is a block diagram of a network element according to an embodiment of the present invention.
• Figure 2 is a more detailed block diagram of a network element according to an embodiment of the present invention.
• Figure 3 is an example of traffic flow through the network element depicted in figure 2.
• FIG. 4 is a block diagram of a network element according to another embodiment of the present invention. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
• Figure 1 depicts a network element 11 according to an embodiment of the present invention, equipped to accept various types of signals.
• a DS 1 signal from the telecommunications network (not shown) can be accepted into network element 11 through input interface 12
• a DS 3 signal from the telecommunications network can be accepted into network element 1 1 through input interface 13
• an OC-n signal from the telecommunications network can be accepted into network element 1 1 through input interface 14
• a data signal, from a LAN for instance, can be accepted into network element 11 through input interface 15.
• each of the interface cards 12 through 15 is be outfitted so as to be capable of receiving different types of signals.
• STS-n signals such as STS-1 s
• STS selector 23 then the routes each of the STS-n signals it receives from input interfaces 12 through 15 to STS time slot interchanger 20, VT time slot interchanger 21 or data switch 22 respectively.
• STS selector 23 may also multiplex and/or demultiplex STS-n signals to other STS rates prior to routing them for ease of transport within the network element 11.
• a network operator is able to select or dial, preferably for each individual STS-1 contained within the STS-n signals entering the STS selector 23, how the STS-n signals from the input interfaces 12 through 15 are routed by STS selector 23.
• the selection process is preferably implemented through software, although it may be performed through hardware, such as switches or relays, or through firmware. It should be noted that the selection process could be done in a manner that is automated, rather than a having a network operator make the selection. Further, in the case where a network operator is making the selection, it need not be on a real-time basis. For STS signals that are routed to STS time slot interchanger 20 by
• STS time slot interchanger 20 manages their bandwidth on an STS level, preferably on an STS-1 level.
• the management may be at any STS-n rate up to the lowest rate of an incoming signal into STS time slot interchanger 20.
• VT time slot interchanger 21 manages their bandwidth on a VT-n level, preferably a VT-1 level.
• data switch 22 manages bandwidth on a cell level. Should data switch 22 be an ATM switch, it should preferably manage both the virtual channel and virtual path of each cell.
• STS time slot interchanger 20, VT time slot interchanger 21 and data switch 22 then send managed signals built back up into STS-n signals, to STS distributor 24.
• STS distributor 24 then distributes the signals to the appropriate output interfaces 16 through 19. Output interfaces 16 through 19 then pass the outgoing signals back out to the network.
• the outgoing signals from the output interfaces 16 through 19 can be of any type, but preferably of an OC-n type.
• Fig. 2 depicts a more detailed view of STS selector 23, STS distributor 24 and their interworkings with STS time slot interchanger 20, VT time slot interchanger 21 and data switch 22 according to an embodiment of the present invention.
• redundant components are not shown.
• signals coming into STS selector 23 enter APS (Automatic Protection Switching) selector 26.
• APS selector 26 selects the signals received from those interfaces that are active.
• APS selector 26 may also demultiplex any higher rate STS-n signals it receives so that all STS-n signals it passes on will be of the same rate. Preferably, this is an STS-1 rate.
• APS selector 26 then provides the signals to a 1 :2 bridge 27.
• the 1 :2 bridge 27 provides selective connectivity between the signals received from APS selector 26 and STS time slot interchanger 20 or time slot interchanger 28. For instance, if the network operator has dialed a certain STS-1 signal to be managed on an STS basis, 1 :2 bridge 27 will provide connectivity between APS selector 26 and STS time slot interchanger 20. If the network operator has dialed the certain STS-1 signal to be managed on a VT or a cell basis, 1 :2 bridge 27 will provide connectivity between APS selector 26 and time slot interchanger 28.
• time slot interchanger 28 For the signals provided to time slot interchanger 28, time slot interchanger 28 outputs two sets of signals (preferably STS-1 signals) to Vx director 29.
• the first set of signals being those for which the network operator has dialed to be managed on a VT basis and the second set being those for which the network operator has dialed to be managed on a cell basis.
• Vx director 29 preferably multiplexes the incoming STS-1 signals to be managed on a VT basis into higher rate STS-n signals, such as STS-12 signals, and provides them to VT time slot interchanger 21.
• Vx director 29 preferably multiplexes the incoming STS-1 signals to be managed on a cell basis into higher rate STS-n signals and provides them to data switch 22. It should be noted that Vx director may pass the signals on without multiplexing them into higher rate signals or the signals may be passed directly from time slot interchanger 28 on to VT time slot interchanger 21 and/or data switch 22.
• Vx distributor may also make copies of the incoming signals and provide them to a spare VT time slot interchanger and data switch (not shown).
• VT time slot interchanger 21 manages the bandwidth of signals entering it on a VT basis and data switch 22 manages the bandwidth of signals entering it on a cell basis.
• Both data switch 22 and VT time slot interchanger 21 pass managed signals at STS-n rates such as STS-12s on to Vx selector 30. If an active/spare arrangement is utilized, Vx selector 30 will select the signals from the active data switch 22 and VT time slot interchanger 21 to pass on to time slot interchanger 31. Additionally, if Vx distributor 29 multiplexed the signals it
• Vx selector 30 will demultiplex them back into the STS-n rates equivalent to those that entered the Vx distributor 29, such as STS-1 s.
• Time slot interchanger 31 reassembles the signals received from
• Vx selector 30 back into the appropriate arrangement to match that of the signals received at the inputs to time slot interchanger 28.
• Time slot interchanger 31 undoes the arranging of the signals that was performed to route the signals to either VT time slot interchanger 21 or data switch 22. Time slot interchanger 31 then provides these signals to 2:1 selector 32.
• STS time slot interchanger 20 manages the
• 2:1 selector 32 selects the appropriate input line to be passed on to the APS distributor 33 based upon whether the bandwidth was to be managed at a STS level, a VT level or a data cell level.
• the 2:1 selector then provides connectivity between the appropriate input line and APS distributor 33.
• APS distributor 33 will provide the output signals to the active output interfaces. If any output interfaces are of a higher data rate than that of the signals received by APS distributor 33, APS distributor 33 may multiplex them up to the requisite rates.
• Fig. 3 an embodiment of the present invention as depicted in Fig. 2 is shown in Fig. 3.
• input signals 41 and 43 are to be managed on a data cell level
• input signals 42 and 45 are to be managed on a STS level
• input signals 44 in 46 are to be managed on a VT level.
• Input signals 41 and 43 are both routed to APS selector 26. As these are active signals, APS selector routes them on to 1 :2 bridge 27. Because a network operator has dialed these signals to be managed on a data cell level, incoming signals 41 and 43 are connected to time slot interchanger 28 by 1 :2 bridge 27. Time slot interchanger 28 then switches incoming signals 41 and 43 so as to route them to data switch 22 and provides incoming signals 41 and 43 to Vx distributor 29. Vx distributor 29 copies incoming signals 41 and 43 and provides the signals to both data switch 22 and a spare data switch (not shown). Data switch 22 then manages the bandwidth within the incoming signals 4 land 43 and passes managed signals out to Vx selector 30.
• Vx selector selects the managed signals 41' and 43' from active data switch 22 and provides them to time slot interchanger 31. Time slot interchanger 31 then routes the managed signals 41 ' and 43' to 2:1 selector 32. Because input signals 41 and 43 were to be managed on a data cell basis, 2:1 selector passes managed signals 41 ' and 43' on to APS distributor 33. APS distributor passes managed signals 41' and 43' out to the appropriate active output interfaces (not shown). The data flow for input signals 42 and 45 is somewhat different.
• input signals 42 and 45 are input to the APS selector 26.
• APS selector 26 passes them onto 1 :2 bridge 27.
• 1 :2 bridge 27 then provides connectivity for input signals 42 and 45 to time slot interchanger 20.
• Time slot interchanger 20 then manages the bandwidth on an STS level and passes the managed signals 42' and 45' onto 2:1 selector 32.
• 2:1 selector 32 provides connectivity between STS time slot interchanger 20 and APS distributor 33 for managed signals 42' and 45' because they were to be managed at an STS level
• APS distributor 33 outputs managed signals 42' and 45' to the appropriate active output interfaces.
• Input signals 44 and 46 are passed to APS selector 26. As these are active signals, APS selector routes them on to 1 : 2 bridge 27. Because they are to be managed on a VT level, 1 :2 bridge 27 provides connectivity for incoming signals 44 and 46 to time slot interchanger 28. Time slot interchanger 28 then switches incoming signals 44 and 46 so as to route them to VT time slot interchanger 21 and provides input signals 44 and 46 to Vx distributor 29. Vx distributor 29 copies input signals 44 and 46 and provides the signals to both VT time slot interfchanger 21 and a spare time slot interchanger (not shown).
• VT time slot interchanger 21 manages the bandwidth of incoming signals 44 and 46 on a VT level and outputs managed signals 44' and 46' to Vx selector 30.
• Vx selector selects the managed signals 44' and 46' from active VT time slot intetchanger 21 and provides them to time slot interchanger 31.
• Time slot interchanger 31 connects managed signals 44' and 46' to 2:1 selector 32. Because input signals 44 and 46 were to be managed on a VT basis, 2:1 selector 32 provides managed signals 44' and 46' to APS distributor 33. APS distributor 33 then provides managed signals 44' and 46' to the appropriate active output interfaces.
• Figure 4 depicts another embodiment of present invention. In that figure, input signals are accepted into network element 51 through input interfaces 52, 53 and 54.
• Network element 51 accepts different signal types and formats from the telecommunications network.
• input interface 52 may accept a DS 3 signal
• input interface 53 may accept a DS 1 signal
• input interface 54 may accept data traffic on an OC-3 line.
• the signals from input interfaces 52, 53 and 54 are then routed to the appropriate bandwidth management device through connectors 66a-66c, 67a-67c and 68a-68c, respectively.
• input interfaces 52, 53 and 54 reside on cards which slide into a card cage.
• Connectors 66a-66c, 67a-67c and 68a-68c would reside on the backplane of the card cage and make contact with input interfaces 52, 53 and 54, respectively, when the cards have been inserted into the cage.
• Each of the connectors a-c may reside on a single connector or multiple connectors.
• Connectors 66a, 67a and 68a would provide connectivity to STS time slot interchanger 55.
• Connectors 66b, 67b and 68b would provide connectivity to VT time slot interchanger 56.
• Connectors 66c, 67c and 68c would provide connectivity to data switch 57.
• Layer 3 switch 64 can communicate with data switch 57 to provide Layer 3 switching functionality.
• STS time slot interchanger 55, VT time slot interchanger 56, data switch 57 and Layer 3 switch 64 are connected to STS distributor 58.
• STS distributor 58 than distributes signals it receives from STS time slot interchanger 55, VT time slot interchanger 56, data switch 57 and Layer 3 switch 64 to the appropriate output interfaces 60 through 62.
• the signals output from interface cards 60 through 62 can be of an OC-n type.
• the STS selector 58 may be replaced by the use of connectors similar to 66a-66d, 67a-67d, 68a-68d and 69a-69d attached to output interfaces 60 through 62 providing connectivity to STS time slot interchanger 55, VT time slot interchanger 56, data switch 57 and Layer 3 switch 64.
• the selectability of which input interfaces 52 through 54 and 63 are mapped to which elements 55 through 57 and 64 is managed by a network operator through user interface 70.
• this can be done automatically by detecting the presence of a certain type of input interface card in a slot in the device upon power up, or by detecting the type of traffic being carried by the input interface cards 52 through 54 and 63.
• this could be done on the input interface card itself through the use of a switch or similar device.
• the selectability function would be implemented through the use of software, but may be implemented through hardware, such as switches or relays, or through firmware.
• FIG. 5 A sample of traffic flow through the embodiment depicted in Figure 4 is shown in Figure 5.
• the DS 3 signal received by input interface 52 is built into an STS-n signal and routed by connector 66a to STS time slot interchanger 55.
• STS time slot interchanger 55 manages the bandwidth of this signal on an STS level and outputs an STS-n signal to STS distributor 58.
• This signal is then routed to output interface 62 and output to the network.
• the DS 1 signal received by input interface 53 is built into an STS- n signal and passed to VT time slot interchanger 56 through connector 67b.
• VT time slot interchanger 56 manages the bandwidth of this signal on a VT level and outputs and STS-n signal to STS distributor 58.
• This signal is then routed to output interface 60 and output to the network.
• the data traffic received by input interface 54 is built into an STS-n signal and passed to data switch 57 through connector 68c.
• Data switch 57 manages the bandwidth of data signals sent into it on a cell level and outputs an STS-n signal.
• This signal is passed to Layer 3 switch, if Layer 3 switching is desired.
• a data connection from a LAN may be input into input interface 63 and that data may be passed on to Layer 3 switch 64 through connector 69d.
• Layer 3 switch 64 then manages the Layer 3 data and outputs managed data to STS distributor 58. This data is then routed to output interface 61 and output to the network.

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Data Exchanges In Wide-Area Networks (AREA)
• Time-Division Multiplex Systems (AREA)

Priority Applications (5)

Applications Claiming Priority (2)

Publications (1)

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ID=23264805

Family Applications (1)

Country Status (7)

Cited By (1)

Families Citing this family (13)

Citations (3)

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• 1999
  • 1999-06-03 US US09/324,721 patent/US6396847B1/en not_active Expired - Fee Related
• 2000
  • 2000-06-01 DE DE60042271T patent/DE60042271D1/de not_active Expired - Fee Related
  • 2000-06-01 EP EP00939515A patent/EP1181839B1/en not_active Expired - Lifetime
  • 2000-06-01 AU AU54592/00A patent/AU5459200A/en not_active Abandoned
  • 2000-06-01 WO PCT/US2000/015229 patent/WO2000076259A1/en not_active Ceased
  • 2000-06-01 CA CA002375553A patent/CA2375553A1/en not_active Abandoned
  • 2000-06-01 JP JP2001502401A patent/JP2003501977A/ja active Pending
• 2001
  • 2001-09-18 US US09/955,880 patent/US6584119B2/en not_active Expired - Fee Related

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