WO2000063962A1 - Dispositif et procede pour evaluer la fiabilite d'une interconnexion metallique, et support d'enregistrement dans lequel une evaluation de la fiabilite d'une interconnexion metallique est enregistre - Google Patents
Dispositif et procede pour evaluer la fiabilite d'une interconnexion metallique, et support d'enregistrement dans lequel une evaluation de la fiabilite d'une interconnexion metallique est enregistre Download PDFInfo
- Publication number
- WO2000063962A1 WO2000063962A1 PCT/JP1999/004084 JP9904084W WO0063962A1 WO 2000063962 A1 WO2000063962 A1 WO 2000063962A1 JP 9904084 W JP9904084 W JP 9904084W WO 0063962 A1 WO0063962 A1 WO 0063962A1
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- WO
- WIPO (PCT)
- Prior art keywords
- wiring
- thickness
- current density
- afd
- bamboo
- Prior art date
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Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
- G01R31/2858—Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
Definitions
- the present invention relates to a technique for predicting electromigration (EM) damage, which is a cause of metal wiring failure, and for evaluating reliability.
- EM electromigration
- EM electrical outlet
- the life expectancy of the wiring is performed by excluding the results of the disconnection test under the EM acceleration conditions under practical conditions. Although an empirical formula is currently used for this extrapolation, the development of a universal life prediction method has been awaited due to the problem that the prediction results differ depending on the choice of accelerated test conditions and wiring configuration. Disclosure of the invention
- An object of the present invention is to predict EM damage such as formation of a void or a hillock and disconnection failure of the wiring due to the damage by using atomic flux divergence (AFD ien ) which is a parameter controlling EM damage of each of the polycrystalline wiring and the bamboo wiring. It is.
- the present invention provides a method of calculating the current density and temperature distribution of metal wiring by a numerical analysis method, The flux divergence (AFD gen ) is calculated, the volume reduction of each element in each calculation step is calculated, the change in the thickness of each element is calculated, and each operation is repeated, so that the element penetrating the thickness reduces the wiring width. The process is performed until the element that penetrates the occupied state or thickness or the element whose temperature exceeds the melting point of the material occupies the wiring width.
- the above method is applied to both polycrystalline wiring and bamboo wiring.
- the present invention also includes an apparatus for executing the above method and a recording medium storing a program for causing a computer to execute the above method.
- FIG. 1 is a diagram showing an atomic flux and a current density at a crystal grain boundary.
- FIG. 2 is a diagram showing a model of a grain boundary structure of a rectangular element having a unit thickness including only one triple junction formed by three grain boundaries inside.
- FIG. 3 is a flowchart showing the processing of the numerical simulation.
- FIG. 4 is a diagram showing an example of element division used for numerical simulation of polycrystalline wiring.
- FIG. 5 is a flow chart showing a procedure for obtaining an effective width of a slit, which is a physical property constant of a wiring material.
- Figure 6 shows two samples for numerical simulation of polycrystalline wiring.
- Fig. 7 shows the results of numerical simulation of the AFD gen distribution in the polycrystalline wiring (sample 1).
- FIG. 8 is a diagram showing a numerical simulation result of a void distribution in the polycrystalline wiring (sample 1).
- FIG. 9 is a diagram showing a numerical simulation result of the AFDeen distribution in the polycrystalline wiring (sample 2).
- FIG. 10 is a diagram showing a numerical simulation result of a void distribution in a polycrystalline wiring (sample 2).
- FIG. 11 is a block diagram showing an apparatus for a verification experiment.
- FIG. 12 is a diagram showing an experimental result on a polycrystalline wiring (sample 1).
- FIG. 13 is a diagram showing the experimental results for a polycrystalline wiring (sample 2).
- FIG. 14 shows constants of material properties used for numerical simulation of polycrystalline wiring.
- Fig. 15 shows an example of element division used for numerical simulation of bamboo wiring.
- Fig. 16 shows three samples for performing a numerical simulation of bamboo wiring.
- Figure 17 shows the material properties used for the numerical simulation of the bamboo wiring (ASYM (+)).
- Fig. 18 shows the results of numerical simulation of the AFD gen distribution in bamboo wiring (ASYM (+)).
- FIG. 19 is a diagram showing a numerical simulation result of a void distribution in a bamboo wiring (ASYM (+)).
- Fig. 20 shows the results of numerical simulation of AFDien distribution in bamboo wiring (SYM).
- FIG. 21 is a diagram showing a result of a numerical simulation of a void distribution in a bamboo wiring (SYM).
- Fig. 22 shows the results of numerical simulation of the AFD gen distribution in the bamboo wiring (ASYM (-)).
- FIG. 23 is a diagram showing a numerical simulation result of a void distribution in a bamboo wiring (ASYM (-)).
- FIG. 24 is a diagram showing an experimental result in a bamboo wiring (ASYM (+)).
- FIG. 25 is a diagram showing the results of an experiment on bamboo wiring (SYM).
- FIG. 26 is a diagram showing an experimental result in a bamboo wiring (ASYM (—)). BEST MODE FOR CARRYING OUT THE INVENTION
- the total sum of atomic flux divergence A FD een in the wiring is expressed by the sum of atomic flux divergence (atomic flux divergence) in the crystal grain boundaries and in the crystal grains, and is defined by the following equation.
- AFD ien AFD gb + AFD l at (1)
- AFD ib and AFD l at are the divergence of the atomic flux in the grain boundary and in the grain, respectively. Equation (1) holds for both the polycrystalline interconnect and the bamboo interconnect.
- AFD ib and AFD lat are derived in consideration of the wiring structures of polycrystalline wiring and bamboo wiring. Here, the movement of atoms in the crystal grain boundary and in the crystal grain are both given by the following equations. ND
- J is the atomic flux vector
- N is the atomic density
- k is the Boltzmann constant
- T is the absolute temperature
- Z * is the number of effective charges
- e is the unit charge
- / 0 is the electrical resistivity
- D is Is the diffusion coefficient represented by
- D is the diffusion coefficient represented by
- I is the frequency term
- Q is the activation energy.
- J is equal to I j I in the crystal grain because the directions of J and j coincide. As shown in Fig. 1, if the angle between j and the grain boundary is ⁇ , (grain boundary) a )
- Q represents a value in a crystal grain boundary or a crystal grain, and is expressed as Q ib and Q lat , respectively.
- the X-direction component and the y-direction component of the current density vector j are j x and j y , respectively, and the angle between the grain boundary I and the X axis is 0, the current at the end of the grain boundaries I, ⁇ , and ⁇
- the density vector component and temperature are expressed as follows, respectively, as shown in Fig. 2.
- T T + — — -ee «& + — — * mff
- AFD ib 0 (Bamboo wiring) (7) (Diffusion of atomic flux in crystal grains)
- Lattice diffusion can be treated similarly in both polycrystalline and bamboo wiring.
- Vector analysis is possible for the atomic flux vector J in the crystal grain.
- the number of atoms reduced per unit time and unit volume AFD'lat can be obtained by the following equation. (8) Where Q lat is the activation energy of the dominant intragranular diffusion of lattice expansion.
- Equations (10) and (5) show that current flux, current density gradient, temperature, and temperature gradient affect the divergence of atomic flux in polycrystalline interconnects.
- the physical properties of the wiring materials are determined by an acceleration test using straight wiring.
- the constant; 0. And ⁇ can be obtained by measuring the electrical resistance of the linear metal wiring.
- the constant H is determined so that the electrical resistance of the metal wiring calculated based on the temperature distribution obtained from the numerical analysis becomes equal to the measured value.
- the activation energy Q ib for the polycrystalline wiring is given by the slope of the plot of In VT / (j ⁇ , n p) for one.
- j in is the input current density
- V is the volume of the void in the central region of the wiring after energizing for a certain time under the three acceleration conditions.
- the volume of the void is estimated by multiplying the total area of the void measured by a scanning electron microscope (SEM) by the thickness of the thin film.
- SEM scanning electron microscope
- the activation energy Q l at in the crystal grains in the bamboo interconnect is determined from the slope of the straight line obtained by plotting the I NVT 2 Z 0 against 1 ZT.
- V is the current input to the linear bamboo wire at three different substrate concentrations for a certain period of time.
- the vicinity of the cathode end of each wire is measured using an atomic force microscope (Atomic Force Microscope A FM). It is the void volume obtained by measurement.
- the constant ⁇ 0 is determined so that the calculated value of the ratio of the void volume in the central region of the wiring to the void volume near the end on the cathode side is equal to the ratio of the measured values.
- the constant C ib is obtained from the relationship between the void volume measured in the experiment and the calculated value.
- metal interconnects are divided into elements. Using a smaller element size can provide more realistic results.
- the thickness of the element is changed according to the procedure shown in the flow chart of Fig. 3.
- the distribution of current density and temperature can be obtained by numerical analysis techniques such as two-dimensional finite element analysis (FEM analysis) (S304).
- FEM analysis finite element analysis
- the divergence AFD gen of the atomic flux of each element is calculated by using these distributions and the physical property constants (S306) of the wiring material determined in advance by the acceleration test (S308).
- the volume reduction per calculation step in the simulation (S312) is given by multiplying the volume of each element, the time corresponding to one calculation step, and the atomic volume (S310). Here, one calculation time allocates real time.
- the reduction in volume is converted to the reduction in thickness in each element (S314).
- the element with reduced thickness it indicates that a void was formed, and the depth of the void corresponds to the decrease in the thickness of the element.
- Numerical analysis of the current density and temperature distribution in the metal wiring is performed again in consideration of the thickness of each element (S304). Thus, the calculation shown in FIG. 3 is repeatedly performed.
- Voids grown selectively along crystal grain boundaries and grown in slits are connected to each other in the direction of the wiring width. This is the growth morphology of voids in polycrystalline interconnects.
- the parameter AFD gen is derived based on the assumption that void formation occurs at grain boundaries, but is eventually extended to the expected void formation at any point in the metal interconnect.
- the form of the void formation is once again converted into the formation of slit-like voids along the crystal grain boundaries.
- FIG. 4A shows an example of a finite element model of wiring used later in FIG.
- FIGS. 4B, 4C, and 4D are enlarged views of each part.
- the thickness of the dedicated element for slit-like voids is reduced based on the calculation of AFD g , n for that element and its neighbors.
- the pitch of the slit is determined by the average crystal grain size.
- the width of the slit is one of the physical constants of the wiring material, and can be obtained according to the procedure shown in FIG.
- an accelerated test is performed until a disconnection failure occurs while performing SEM observation (S504).
- S504 From the SEM image of the metal wiring obtained just before the failure occurs, an area where slit-like voids are dense, that is, a place where a disconnection failure will soon occur is extracted (S502).
- the number of slits included in the dense area is obtained by dividing the length of the dense area (S506) along the longitudinal axis of the wiring by the pitch of the slit (S510).
- the total area of the slit-shaped voids in the dense area is measured (S508).
- the effective width of the slit in the simulation can be obtained (S512).
- the experiment for determining the slit width is a constant?. ,, H, ⁇ , and C gb are performed with the sample used to determine.
- the two aluminum polycrystalline interconnects shown in Figure 6 were used to predict lifetime and failure location.
- the bent metal wiring has a two-dimensional distribution of current density and temperature.
- the constants required for prediction are given by a simple accelerated test using straight wiring.
- the two wires are called sample 1 and sample 2. These are different not only in shape but also in test conditions as shown in Fig. 6A.
- the AFDien distribution changes with time due to changes in current density and temperature distribution due to void growth.
- the metal wiring failure occurs with a lifetime of 770 s, and the failure location is predicted to be the cathode end of the wiring.
- the failure for sample 2 occurs with a lifetime of 3400 s, and the failure location is on the cathode side of the corner. It is predicted that.
- Figures 12 and 13 show the experimental results of the frequency distribution of disconnection failures and the average time to failure.
- Fig. 12A in the case of sample 1, the average time to failure obtained from all 11 test pieces is 6731 s. The most frequent fault location is at the cathode end of the wiring. The predicted failure location, that is, the average open time of the six test pieces opened at the cathode end is 6820 s, which is close to the average time to failure obtained from 11 test pieces.
- sample 2 the average time to failure obtained from all 12 test pieces was 3655 s, and the cathode side of the corner was one of the most frequent failure points (See Figure 13A).
- the assumed wiring is divided into elements as shown in FIG. 15, and the thickness of each element is changed by the method shown in the flowchart of FIG.
- the distribution of current density and temperature in the wiring is obtained by numerical analysis methods such as two-dimensional finite element analysis (S304), and the The AFD gen of each element is calculated (S308) using the results and the physical property constants (S306) of the wiring determined in advance by experiments.
- S304 two-dimensional finite element analysis
- S306 The AFD gen of each element is calculated
- S306 the volume of each element that decreases during one time step is calculated (S312).
- the time of one time step corresponds to the actual time.
- the volume of each element is reduced, and the thickness of each element is changed accordingly (S314).
- the current density and temperature are again analyzed numerically, taking into account the change in electrical resistance and change in heat conduction corresponding to the change in thickness, and the subsequent calculations are repeated.
- an element whose thickness can be regarded as sufficiently zero compared to the initial thickness penetrates in the wiring width direction, or an element with zero thickness or an element whose temperature exceeds the melting point of the material reduces the wiring width.
- the calculation is defined as a break in the simulation at the time of the occupation, and the calculation is terminated.
- the three types of AI bamboo wiring shown in Fig. 16 were used as disconnection prediction targets.
- the current density distribution and the temperature distribution show a two-dimensional distribution.
- A 14.0 / m
- B 8.0 ⁇ m for AS YM (+)
- ⁇ 11.2m
- B 10.9m for SYM
- A 8.0 / m
- B 13.9 / im AS YM (—)
- the test conditions for the input current density and the substrate temperature were the same for each configuration.
- the wiring width is not constant as shown in Fig.
- the physical properties of the thin film required for the AFDeen calculation were obtained as shown in the table in Fig.17. This book In the measurement, the constants H and; l were measured for each of the straight-line wiring and the bent wiring by the wiring resistance value calculated based on the temperature distribution simulation by the two-dimensional finite element analysis and the experiment in each shape. The wiring resistance was determined so as to match. Generally the thermal conductivity of thin films are said to be lower than that of the bulk, the ⁇ obtained a 1.55X 1 0 one 4 WZ ( ⁇ ⁇ ⁇ ), lower than the bulk value. Numerical simulations were performed using the above physical properties, and the disconnection by EM was predicted for each of the three types of wiring, AS YM (+), S YM, and ASYM (—).
- AS YM (+) respectively which the time course of distribution of the distribution and the void of the AFD ie n in the case of 1 8 and 1 9.
- S YM is shown in FIGS. 20 and 21
- AS YM (1) is shown in FIGS. 22 and 23, respectively.
- the void distribution is indicated by an iso-line of the wiring thickness.
- the distribution of AFD een changes over time after the start of re-energization due to changes in current density and temperature distribution due to void growth.
- ASYM (+) a disconnection was predicted at 7100 s after the start of energization on the anode side of the wiring corner.
- SYM a break after 7000 s was predicted on the corner anode side.
- AS YM (-) a disconnection after 5200 s near the cathode end of the wiring was predicted.
- AS YM (+) for 9 specimens The average disconnection time was 9160 s, and the most broken part of the wiring was on the anode side of the corner of the wiring.
- the average disconnection time of the four specimens that were disconnected at the corner anode side which was the predicted location of the disconnection in the numerical simulation, was 7965 s, which was close to the average disconnection time of all nine specimens.
- the average disconnection time of the ten test pieces was 7836 s, and the most broken part of the wiring was on the anode side of the wiring corner.
- the average disconnection time of the five disconnected wires was 7344 s, which was close to the average disconnection time of all ten test pieces, similar to ASYM (+).
- the average disconnection time for 11 test pieces was 6996 s, and the most ruptured location was near the cathode end of the wiring.
- the average disconnection time of the six test pieces disconnected at the cathode end of the wiring which is the predicted location of the disconnection in the numerical simulation, was 6160 s, which was close to the average disconnection time of all 11 test pieces.
- voids induced by electrification is related to current density, temperature, these gradients, electrical resistivity, average grain size, activation energy, relative angle between grain boundaries, atomic density, and diffusion. It depends on material properties such as coefficient, effective charge, and effective width of grain boundaries.
- AFD ien a parameter determined as a function of these factors, supports poid formation. I have arranged. Disconnection failures in metal interconnects result from the formation and growth of voids. The location of a failure varies depending on the combination of these factors, which are determined by the operating conditions such as the wiring shape, substrate temperature, and input current density.
- the simulation of the present invention based on AFD ien accurately predicts the life of metal wiring and the location of disconnection failure.
- the present invention may be applied not only to a stand-alone computer system but also to a client-server system composed of a plurality of systems.
- the system according to the present invention can be realized by reading out and executing the program from the storage medium storing the program for making predictions according to the present invention.
- Such recording media include floppy disks, CD-ROMs, magnetic tapes, and ROM sets.
- the simulation of the present invention makes it possible to accurately predict the lifetime of a metal wiring and the location of a failure.
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Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP99933164A EP1195800A4 (en) | 1999-04-19 | 1999-07-28 | DEVICE AND METHOD FOR EVALUATING THE RELIABILITY OF A METAL INTERCONNECT, AND RECORDING MEDIUM IN WHICH AN ASSESSMENT OF THE RELIABILITY OF A METAL INTERCONNECT |
US09/959,073 US6879925B1 (en) | 1999-04-19 | 1999-07-28 | Metal interconnect reliability evaluation device, method thereof, and recording medium storing program for evaluating reliability of metal interconnect |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11147899A JP4298842B2 (ja) | 1999-04-19 | 1999-04-19 | 金属配線の信頼性評価装置及び方法、並びに金属配線の信頼性評価のためのプログラムを格納した記録媒体 |
JP11/111478 | 1999-04-19 |
Publications (1)
Publication Number | Publication Date |
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WO2000063962A1 true WO2000063962A1 (fr) | 2000-10-26 |
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PCT/JP1999/004084 WO2000063962A1 (fr) | 1999-04-19 | 1999-07-28 | Dispositif et procede pour evaluer la fiabilite d'une interconnexion metallique, et support d'enregistrement dans lequel une evaluation de la fiabilite d'une interconnexion metallique est enregistre |
Country Status (6)
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US (1) | US6879925B1 (ja) |
EP (1) | EP1195800A4 (ja) |
JP (1) | JP4298842B2 (ja) |
KR (1) | KR100753693B1 (ja) |
TW (1) | TW446897B (ja) |
WO (1) | WO2000063962A1 (ja) |
Families Citing this family (6)
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JP4515131B2 (ja) * | 2004-03-30 | 2010-07-28 | 独立行政法人科学技術振興機構 | 多層構造配線のem損傷による原子濃度分布評価システム |
US7146588B1 (en) * | 2004-08-02 | 2006-12-05 | Advanced Micro Devices, Inc. | Predicting EM reliability by decoupling extrinsic and intrinsic sigma |
JP6044926B2 (ja) * | 2012-09-06 | 2016-12-14 | 国立大学法人弘前大学 | ビア接続の多層配線の信頼性を評価する信頼性評価シミュレーションプログラム、ビア接続の多層配線の許容電流密度向上方法およびビア接続の多層配線 |
US10755000B2 (en) | 2015-11-06 | 2020-08-25 | Toyota Motor Engineering & Manufacturing North America, Inc. | Methods and apparatuses for assessing high temperature bonding systems and bonded substrates therefrom |
CN107784163B (zh) * | 2017-09-28 | 2021-04-27 | 东南大学 | 一种沥青混合料空隙结构离散元模拟方法 |
CN109872779B (zh) * | 2019-01-30 | 2022-10-11 | 郑州大学 | 一种微系统金属互连结构可靠性评估方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07283283A (ja) * | 1994-02-15 | 1995-10-27 | Ricoh Co Ltd | 配線故障解析方法 |
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US5434385A (en) * | 1992-11-02 | 1995-07-18 | International Business Machines Corporation | Dual channel D.C. low noise measurement system and test methodology |
US5382831A (en) * | 1992-12-14 | 1995-01-17 | Digital Equipment Corporation | Integrated circuit metal film interconnect having enhanced resistance to electromigration |
US5581475A (en) * | 1993-08-13 | 1996-12-03 | Harris Corporation | Method for interactively tailoring topography of integrated circuit layout in accordance with electromigration model-based minimum width metal and contact/via rules |
US5497076A (en) * | 1993-10-25 | 1996-03-05 | Lsi Logic Corporation | Determination of failure criteria based upon grain boundary electromigration in metal alloy films |
US5439731A (en) * | 1994-03-11 | 1995-08-08 | Cornell Research Goundation, Inc. | Interconnect structures containing blocked segments to minimize stress migration and electromigration damage |
US5822218A (en) * | 1996-08-27 | 1998-10-13 | Clemson University | Systems, methods and computer program products for prediction of defect-related failures in integrated circuits |
US5760595A (en) * | 1996-09-19 | 1998-06-02 | International Business Machines Corporation | High temperature electromigration stress test system, test socket, and use thereof |
US6038383A (en) * | 1997-10-13 | 2000-03-14 | Texas Instruments Incorporated | Method and apparatus for determining signal line interconnect widths to ensure electromigration reliability |
US6320391B1 (en) * | 1998-05-08 | 2001-11-20 | Advanced Micro Devices, Inc. | Interconnection device for low and high current stress electromigration and correlation study |
JP2001351919A (ja) * | 2000-06-05 | 2001-12-21 | Nec Corp | 配線故障解析方法 |
US6714037B1 (en) * | 2002-06-25 | 2004-03-30 | Advanced Micro Devices, Inc. | Methodology for an assessment of the degree of barrier permeability at via bottom during electromigration using dissimilar barrier thickness |
-
1999
- 1999-04-19 JP JP11147899A patent/JP4298842B2/ja not_active Expired - Fee Related
- 1999-07-28 WO PCT/JP1999/004084 patent/WO2000063962A1/ja active Application Filing
- 1999-07-28 US US09/959,073 patent/US6879925B1/en not_active Expired - Fee Related
- 1999-07-28 EP EP99933164A patent/EP1195800A4/en not_active Ceased
- 1999-07-28 KR KR1020017013233A patent/KR100753693B1/ko not_active IP Right Cessation
- 1999-09-04 TW TW088115289A patent/TW446897B/zh not_active IP Right Cessation
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07283283A (ja) * | 1994-02-15 | 1995-10-27 | Ricoh Co Ltd | 配線故障解析方法 |
Non-Patent Citations (2)
Title |
---|
KIRCHHEIM R. ET AL.: "Atomistic and Computer Modeling of Metallization Failure of Integrated Circuits by Electromigration", JOURNAL OF APPLIED PHYSICS, vol. 70, no. 1, 1 July 1991 (1991-07-01), pages 172 - 181, XP002925388 * |
See also references of EP1195800A4 * |
Also Published As
Publication number | Publication date |
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EP1195800A4 (en) | 2002-10-30 |
US6879925B1 (en) | 2005-04-12 |
KR20010112436A (ko) | 2001-12-20 |
KR100753693B1 (ko) | 2007-08-30 |
EP1195800A1 (en) | 2002-04-10 |
TW446897B (en) | 2001-07-21 |
JP2000306969A (ja) | 2000-11-02 |
JP4298842B2 (ja) | 2009-07-22 |
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