WO2000042644A1 - System and method for surface passivation - Google Patents

System and method for surface passivation Download PDF

Info

Publication number
WO2000042644A1
WO2000042644A1 PCT/US2000/000185 US0000185W WO0042644A1 WO 2000042644 A1 WO2000042644 A1 WO 2000042644A1 US 0000185 W US0000185 W US 0000185W WO 0042644 A1 WO0042644 A1 WO 0042644A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor substrate
oxidizing
substrate surface
ranges
annealing
Prior art date
Application number
PCT/US2000/000185
Other languages
French (fr)
Other versions
WO2000042644A9 (en
Original Assignee
Sumitomo Sitix Silicon Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Sitix Silicon Inc. filed Critical Sumitomo Sitix Silicon Inc.
Priority to EP00903112A priority Critical patent/EP1142007A1/en
Priority to JP2000594145A priority patent/JP2002535833A/en
Publication of WO2000042644A1 publication Critical patent/WO2000042644A1/en
Publication of WO2000042644A9 publication Critical patent/WO2000042644A9/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67115—Apparatus for thermal treatment mainly by radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
    • H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form

Definitions

  • the electrical characterization, e.g., resistivity being most common, of underlying layer 14 is an important specification desired by a purchaser or consumer of semiconductor wafers and/or chips because, among other factors, the electrical properties of underlying layer 14 significantly impact the electrical performance of the active devices formed in the underlying layer.
  • the wafer surface passivation process i.e. fabrication of oxide layer 12 of Figure 1, is currently accomplished either through wet chemistry or by thermal oxidation. According to the wet chemistry method , the wafer surface, which is typically includes silicon, is exposed at low temperatures, e.g., about 80 °C. to an aqueous oxidizing solution that oxidizes or passivates the wafer surface and forms silicon dioxide (SiO 2 ) thereon.
  • the wafers are exposed to a wet chemistry solution, they are dried using a drying apparatus, which requires added cost and space for additional equipment.
  • the wet chemical passivation and drying steps are also time consuming and, therefore, lower the throughput of the wafer surface passivation process.
  • the problems associated with limited cost and space are further aggravated when additional resources are expended for environmentally safe disposal of the wet chemistry solutions.
  • Thermal oxidation typically begins when a wafer is loaded into a tube furnace containing an oxidizing environment and the temperature inside the furnace is raised to relatively high temperatures, e.g., 900 °C and higher.
  • An oxidizing environment may contain oxygen or ozone in various concentrations. Any ozone gas used in the tube furnace is produced ex-situ, i.e. outside the tube furnace, and is transported inside the tube furnace through appropriate equipment, such as pipes, valves and the like, during thermal oxidation. In order to accomplish the required extent of passivation, the wafer is exposed to such high temperatures for about 2 hours or more. The heated wafer surface is cooled before the electrical properties of the underlying layer are determined.
  • Figure 2 shows a portion of a epitaxial silicon wafer 20 having a passivated surface and the layer stack of this wafer is discussed hereinafter as an example to facilitate discussion regarding the undesirable effects of high temperature treatments on a wafer during thermal oxidation.
  • the present invention provides a process for effectively reducing reactivity of a surface of a semiconductor substrate.
  • the process includes: (1) oxidizing in an oxidizing environment the surface of a semiconductor substrate, which has a dopant concentration profile that extends across a depth of the semiconductor substrate; and (2) annealing the semiconductor substrate surface in an inert gas environment, wherein oxidizing and annealing of the semiconductor substrate surface are performed at relatively low temperatures.
  • the temperatures of oxidizing and annealing which may be the same, are sufficiently low to substantially preserve the dopant concentration profile in the semiconductor substrate.
  • the temperatures are sufficiently low to substantially preserve the oxygen precipitation level of the semiconductor substrate.
  • the temperatures are sufficiently low to substantially preserve the mechanical properties of the substrate.
  • the present invention provides a surface passivation apparatus.
  • the apparatus includes: (1) a heating source for heating a substrate surface; (2) an ozone generator; and (3) a chamber for exposing a substrate surface to an oxidizing environment that includes a gas composition.
  • the ozone generator of the present invention is configured to produce ozone within said chamber using said gas composition.
  • An inert gas environment may be produced before the temperature inside lower chamber 104 is modified to promote annealing of the substrate surface.
  • IR lamps 124 drive up the temperature inside lower chamber to increase the temperature of the substrate surface.
  • the temperature inside lower chamber 104 is the same as the annealing temperature, then the temperature need not be modified.
  • Annealing of the substrate surface is carried out in an inert gas environment. In a preferred embodiment of the present invention, however, annealing is carried out in a noble gas environment.
  • the inert environment includes argon and/or nitrogen gas.
  • the oxidation step of the present invention may be carried out at atmospheric pressure, but the prior art designs of surface passivation require oxidation under vacuum conditions.
  • the present invention therefore, obviates the need for complicated vacuum generating systems and the like, which are necessary to implement the prior art designs of oxidation.
  • Total UV flux may generally be between about 0.1 Watts/m 2 and about 10 kilo Watts/m 2 and is preferably between about 500 Watts/m 2 and about 7000 Watts/m 2 and more preferably is between about 5000 Watts/m 2 and about 7000 Watts/m 2 . It should not be construed that UV generating is necessary to carry out the present invention. In fact, ozone generated ex-situ may be transported to lower chamber 104, which is maintained at low temperatures, to induce surface oxidation. In a preferred embodiment, however, the ozone may be generated using a UV source and in a more preferred embodiment, the ozone may be generated in-situ using the surface apparatus shown in Figure 4.
  • a semiconductor substrate processed according to the present invention is effectively passivated to include a high quality oxide surface layer that is at least of the same quality as or better than the oxide layer produced by thermal oxidation.
  • the oxide layer advantageously lends itself to the non-contact or non-destructive measurement of the electrical properties, e.g., resistivity of the substrate layer underlying the passivated surface.
  • the electrical properties of the underlying substrate layer are measured in a simple, fast, reproducible manner, which is totally independent of the period of time that passivated substrate surface is exposed to the environment. Consequently, a feed back loop, which provides new or modified input values of variables involved in epitaxial silicon production, are quickly provided to the process control of reactors associated with epitaxial layer deposition.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

A process for effectively reducing reactivity of a surface of a semiconductor substrate is described. The process includes: (1) oxidizing in an oxidizing environment the semiconductor substrate surface, the semiconductor substrate having a dopant concentration profile that extends across a depth of the semiconductor substrate; and (2) annealing the semiconductor substrate surface in an inert gas environment, wherein the oxidizing and the annealing of the semiconductor substrate surface are performed at a temperature that is sufficiently low to substantially preserve the dopant concentration profile in the semiconductor substrate. A surface passivation apparatus is also described. The apparatus includes: a heating source for heating a substrate surface; an ozone generator; and a chamber for exposing a substrate surface to an oxidizing environment that includes a gas composition, wherein the ozone generator is configured to produce ozone within the chamber using the gas composition.

Description

SYSTEM AND METHOD FOR SURFACE PASSIVATION
BACKGROUND OF THE INVENTION
The present invention relates to a system and process for surface passivation of a semiconductor substrate surface. More particularly the present invention relates to a system and process for surface passivation, which produces a passivated semiconductor substrate surface that allows for effective characterization of the electrical properties of the semiconductor substrate layer underlying the passivated substrate surface.
Regardless of the cleanliness of the semiconductor wafer processing environment, some electrically active contaminants end up in or on the semiconductor wafer surface. In order to protect the wafer or its surface from such contaminants, the top layer of the wafer surface, which typically includes silicon, is oxidized to serve as a protective coating. During the wafer surface oxidation or passivation process, as it is commonly known, the top layer of silicon is converted to silicon oxide or some other semiconductor oxide.
Figure 1 shows a portion of a semiconductor wafer 10 having a bulk silicon layer 14, above which is disposed a silicon dioxide (SiO2) layer 12 (hereinafter interchangeably referred to as the "oxide layer" or "passivated surface") that may be fabricated by surface passivation techniques described below. In the presence of such a passivated surface, contaminants landing on the wafer surface end up on the new oxide layer 12 away from the electrically active semiconductor layer or the bulk silicon layer 14. However, contaminants disposed above the oxide layer impede the electrical characterization of bulk silicon layer 14 underlying the passivated wafer surface (hereinafter referred to as the "underlying layer 14" to facilitate discussion). The electrical characterization, e.g., resistivity being most common, of underlying layer 14 is an important specification desired by a purchaser or consumer of semiconductor wafers and/or chips because, among other factors, the electrical properties of underlying layer 14 significantly impact the electrical performance of the active devices formed in the underlying layer. The wafer surface passivation process, i.e. fabrication of oxide layer 12 of Figure 1, is currently accomplished either through wet chemistry or by thermal oxidation. According to the wet chemistry method , the wafer surface, which is typically includes silicon, is exposed at low temperatures, e.g., about 80 °C. to an aqueous oxidizing solution that oxidizes or passivates the wafer surface and forms silicon dioxide (SiO2) thereon. There are oxidizing solutions of different compositions that are commercially available to accomplish wafer surface oxidation. Some compositions of the commercially available oxidizing solution are propreitary. Other compositions of the oxidizing solution, however, are well known. A representative aqueous oxidizing solution composition includes hydrogen peroxide, hydrogen fluoride, ammonium fluoride, etc. Another representative aqueous oxidizing solution composition includes ozone and hydrogen fluoride. After the wafer surface is oxidized using wet chemistry, it undergoes drying which requires a drying apparatus and additional equipment associated with such an apparatus.
Although the wet chemistry method passivates the wafer surface at the desired relatively low temperatures, it suffers from several drawbacks. By way of example, the wet chemistry surface method produces an oxide layer of poor quality that does not allow for simple and reproducible measurements of the electrical properties of the underlying layer. Consequently, it is difficult to ensure a purchaser or consumer of semiconductor wafer and/or chips that the electrical properties of the underlying layer meets their specifications, without utilizing destructive measurement techniques.
As another example, after the wafers are exposed to a wet chemistry solution, they are dried using a drying apparatus, which requires added cost and space for additional equipment. The wet chemical passivation and drying steps are also time consuming and, therefore, lower the throughput of the wafer surface passivation process. The problems associated with limited cost and space are further aggravated when additional resources are expended for environmentally safe disposal of the wet chemistry solutions.
As yet another example, the wet chemistry approach described above may also introduce contaminants from the oxidizing solution on the wafer surface. These contaminants include dissolved metals or particles and may also exacerbate the problem of measuring the electrical properties of the underlying layer.
Thermal oxidation is another method that is traditionally employed to accomplish surface passivation. Those skilled in the art recognize that thermal oxidation offers many advantages associated with dry processing, i.e. processing in the absence of an aqueous oxidizing solution, that are not realized by the wet chemistry method. A few advantages of dry processing by thermal oxidation include eliminating contamination caused by the aqueous oxidizing solution and the need for a drying apparatus and other equipment used in conjunction with the drying apparatus.
Thermal oxidation typically begins when a wafer is loaded into a tube furnace containing an oxidizing environment and the temperature inside the furnace is raised to relatively high temperatures, e.g., 900 °C and higher. An oxidizing environment may contain oxygen or ozone in various concentrations. Any ozone gas used in the tube furnace is produced ex-situ, i.e. outside the tube furnace, and is transported inside the tube furnace through appropriate equipment, such as pipes, valves and the like, during thermal oxidation. In order to accomplish the required extent of passivation, the wafer is exposed to such high temperatures for about 2 hours or more. The heated wafer surface is cooled before the electrical properties of the underlying layer are determined.
Another thermal oxidation technique involves oxidizing the wafer at temperatures of about 1000 °C and higher in a Rapid Thermal Oxidation (RTO) apparatus for a short period of time, e.g., 30 seconds. In order to make the electrical properties of the underlying layer measurable, the oxidized wafer surface is subjected to Rapid Thermal Annealing (RTA) in a nitrogen and/or argon gas environment maintained at the same relatively high temperatures as the oxidation process.
Unfortunately, the thermal oxidation techniques discussed above also suffer from several drawbacks. By way of example, the dopant concentration profile, the oxygen precipitation level and mechanical properties of the wafer are not preserved due to the high thermal budget of the thermal oxidation process. Figure 2 shows a portion of a epitaxial silicon wafer 20 having a passivated surface and the layer stack of this wafer is discussed hereinafter as an example to facilitate discussion regarding the undesirable effects of high temperature treatments on a wafer during thermal oxidation.
Epitaxial silicon wafer 20 includes an epitaxial silicon layer 24 fabricated above a bulk silicon layer 26. Those skilled in the art will recognize that epitaxial silicon layer has a greater degree of silicon purity than bulk silicon layer 26, which may be more conductive due to a higher dopant concentration than epitaxial layer 24. Furthermore, the high purity of the epitaxial layer makes it suitable for many applications and is generally a desired feature by purchasers or consumers of semiconductor wafers and/or chips. An oxide layer 22, as shown in Figure 2, is fabricated above epitaxial layer 24 to reduce the reactivity of the surface of epitaxial silicon wafer 20.
Figure 3 shows a graph of resistivity, which is shown on vertical axis 32, versus the depth of the epitaxial silicon wafer from the top of the epitaxial layer, which depth is shown on horizontal axis 34. It is well known to those skilled in the art that the resistivity of a layer is inversely proportional to the dopant concentration in that layer and, therefore, the resistivity of epitaxial silicon layer 24 is higher than that of silicon bulk layer 26 of Figure 2. For these reasons, the terms "resistivity profile" and "dopant concentration profile" convey the same idea in the discussion set forth below and the term "dopant concentration profile" is used instead of the term "resistivity profile" hereinafter. Thus, also shown in Figure 3 are dopant concentration profiles 36 and 38 that extend across the epitaxial silicon layer, a transition width region 40 and bulk silicon layer of an epitaxial silicon wafer. Dopant concentration profile 38 represents the dopant concentration profile in an epitaxial silicon wafer after the epitaxial silicon wafer is fabricated, but before the wafer is subjected to thermal oxidation. Dopant concentration profile 36 represents the resulting dopant concentration profile of an epitaxial silicon wafer after its surface has been subjected to thermal oxidation. Transition width 40 represents a region of transition between the epitaxial silicon layer and bulk silicon layer.
The shape of the dopant concentration profile in the transition width, such as the shape of dopant concentration profile 38 of Figure 3, is usually specified by the purchaser or consumer of semiconductor wafers and/or chips. In transition width region 40, dopant concentration profile 38 shows a steep drop in resistivity and delineates between a silicon layer of high purity and relatively low dopant concentration and a bulk silicon layer with high dopant concetration in the transition width region. During surface passivation, however, there is a need to preserve dopant concentration profile 38 and thereby ensure that high silicon purity of the epitaxial layer will be maintained and the epitaxial layer will serve as intended.
In this context, however, dopant concentration profile 36 is undesired because it indicates excessive diffusion of the dopant atoms from the bulk silicon layer to the epitaxial silicon layer and across the transition width. The excessive diffusion of dopant atoms alters the characteristics, electrical properties in particular, of the epitaxial silicon layer. High temperature treatment encountered by the wafer during thermal oxidation cause such excessive diffusion of the dopant atoms. Consequently, there is no clear delineation between the epitaxial silicon layer and the bulk silicon layer. Dopant concentration profile 36 illustrates that high temperature treatments performed during thermal oxidation defeat the purpose of expending significant time and resources to fabricate a silicon layer of high purity and render thermal oxidation an unattractive method for surface passivation.
With regards to oxygen precipitation level, it should be borne in mind that a certain amount of oxygen precipitation is desired because it facilitates in gettering metallic impurities, for example. A purchaser or consumer of semiconductor wafers and/or chips typically specifies the desired amount of oxygen precipitation and the epitaxial silicon wafer is fabricated to have this specified or appropriate oxygen precipitation level. High temperature treatments during thermal oxidation, however, undesirably alter the oxygen precipitation level. Specifically, high temperatures induce excessive oxygen precipitation causing sufficient amounts of oxygen atoms to diffuse and precipitate out as crystal silicon dioxide.
Those skilled in the art will recognize that exposure of the wafer surface to high temperatures during thermal oxidation undesirably alters the mechanical properties of the wafer. In particular, wafer mechanical properties such as wafer flatness, warping and bowing, which are typically specified by purchasers or consumers of semiconductor wafers and/or chips, are altered due to high temperature treatments. It is well know that changes in such mechanical properties can detrimentally impact the wafer resulting after subsequent wafer fabrication steps, such as photolithography, and thereby lower die yield.
What is, therefore, needed is a system and method for surface passivation that allows for fast and reproducible measurements of the electrical properties of the underlying layer by employing non-destructive techniques, without suffering from the drawbacks associated with wet chemistry and thermal oxidation.
SUMMARY OF THE INVENTION
The present invention provides a system and method for surface passivation that allows for fast and reproducible measurements of the electrical properties of the underlying layer. The present invention enjoys the advantages offered by wet chemistry (e.g., of low temperature processing) and thermal oxidation (e.g., of producing a high quality oxide layer by employing a simple design for dry processing), without suffering from the drawbacks associated with wet chemistry and thermal oxidation.
It is should be borne in mind that after a semiconductor substrate, e.g., a silicon wafer, a silicon germanium wafer or these wafers having an epitaxial surface layer, is fabricated and before the substrate surface is oxidized, the electrical properties of the substrate layer underlying the passivated surface (hereinafter referred to as "underlying substrate layer" to facilitate discussion) are not always measurable. Whether the electrical properties of the underlying are measurable or not may depend on how long the substrate has been out the reactor and exposed to the environment after the substrate was fabricated. In those instances when the electrical properties of the underlying substrate layer are measurable, it has been found that such measurements are not reproducible over time. Consequently, it is difficult for the semiconductor fabrication facility to know without any degree of certainty whether the properties of the semiconductor substrate meet the customer specifications. To this end, the present invention provides a surface passivation process that guarantees reproducible measurement of the underlying substrate layer, which measurements are independent of time. i.e. the period of time that substrate surface is exposed to the environment after fabrication and before passivation.
The present invention, in accordance with one embodiment, provides a process for effectively reducing reactivity of a surface of a semiconductor substrate. The process includes: (1) oxidizing in an oxidizing environment the surface of a semiconductor substrate, which has a dopant concentration profile that extends across a depth of the semiconductor substrate; and (2) annealing the semiconductor substrate surface in an inert gas environment, wherein oxidizing and annealing of the semiconductor substrate surface are performed at relatively low temperatures. In one embodiment of the present invention, the temperatures of oxidizing and annealing, which may be the same, are sufficiently low to substantially preserve the dopant concentration profile in the semiconductor substrate. In another embodiment of the present invention, the temperatures are sufficiently low to substantially preserve the oxygen precipitation level of the semiconductor substrate. In yet another embodiment, the temperatures are sufficiently low to substantially preserve the mechanical properties of the substrate.
It is noteworthy that due to the drawbacks of wet chemistry and thermal oxidation, 1 or 2 semiconductor substrates serve as test substrates for a substrate production lot and the electrical properties of the underlying substrate layers of the test substrates are considered to be representative of the substrate production lot. A substrate production lot refers to a collection of about 25 semiconductor substrates that are processed together under substantially similar processing conditions. If substrate surface passivation is performed using thermal oxidation, then generally only the test substrates undergo the high thermal cycling described above and the remaining substrates of the production lot may be passivated without being subjected to the same high temperatures. Thus, alterations in the dopant concentration profile, oxygen precipitation level and mechanical properties of the test substrate, as described above, make the properties of the test substrate no longer representative of the entire substrate production lot. Although, the measurement of electrical properties may be carried out via non-contact and non-destructive techniques, the test substrates are discarded because their altered properties fail to ensure compliance with the customer's specifications. This translates into a lower product yield and lost profits.
Equipped with, among others, the advantages of low temperature treatment associated with wet chemistry and dry processing associated with thermal oxidation, the present invention allows all substrates of a substrate production lot to undergo passivation under substantially similar processing conditions. The present invention provides a high quality oxide layer on all the substrate surfaces, which lend themselves to non-contact and reproducible measurement of the electrical properties of the underlying substrate layer. As a result, any one of the substrates of a substrate production lot may serve as the test substrate for measurement of the electrical properties of the underlying substrate layers. Furthermore, the substrates processed according to the present invention need not be discarded after the conclusion of non-contact or non-destructive measurements of the electrical properties because none of the substrates are subjected to high temperatures during surface passsivation according to the present invention. As a result, the need to use test substrates for monitoring production quality is totally eliminated.
In another aspect, the present invention provides a surface passivation apparatus. The apparatus includes: (1) a heating source for heating a substrate surface; (2) an ozone generator; and (3) a chamber for exposing a substrate surface to an oxidizing environment that includes a gas composition. The ozone generator of the present invention is configured to produce ozone within said chamber using said gas composition. Thus, the need for equipment necessary to transport ozone gas from a location off-site to the chamber where ozone gas is created to the chamber is obviated. It is important to keep in mind that all prior art designs that require ozone gas during surface passivation, have their ozone generator located outside the substrate processing chamber. The heating source may include a single or plurality of infrared heating lamps such that each lamp operates at a power of and less than about 1000 watts, for example. Alternatively, in other embodiments, the lamp may operate at a power of about 1000 watts or higher. The ozone generator may be an ultraviolet (UV) frequency generating lamp, which is maintained ozone free when said UV frequency generating lamp produces ozone inside said chamber. A preferred embodiment of the surface passivation apparatus includes a UV transmitting layer that is disposed between the chamber and the ozone generator. The UV transmitting layer is at least substantially transparent to UV radiation and transmits at least a substantial portion of the UV radiation produced by the UV lamps. The chamber may be equipped with a gas inlet and a gas exhaust port such that substantially uniform flow of said gas composition is maintained inside said chamber.
These and other features of the present invention will be described in more detail below in the detailed description of the invention and in conjunction with the following figures.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which:
Figure 1 shows a cross-sectional view of a silicon wafer having a passivated surface or a silicon dioxide surface layer.
Figure 2 shows a cross-sectional view of an epitaxial silicon wafer having a passivated surface or a silicon dioxide surface layer.
Figure 3 shows a graph of resistance versus depth of the epitaxial silicon wafer from the top of the epitaxial layer.
Figure 4 shows a surface passivation, apparatus according to one embodiment of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
The present invention will now be described in detail with reference to a few preferred embodiments thereof as illustrated in accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps and/or structures have not been described in detail in order to not unnecessarily obscure the present invention.
Figure 4 shows a surface passivation apparatus 100, according to one embodiment of the present invention. Surface passivation apparatus 100 includes an upper chamber 102 and a lower chamber 104. Upper chamber 102 houses ultraviolet frequency radiation generating lamps 106 (hereinafter referred to as "UV lamps" to facilitate discussion) and comes equipped with a gas inlet port 108 and a gas outlet port 110. In one embodiment, UV lamp 106 generate UV radiation that includes frequencies which range from about 100 to about 300 nanometers (nm). A substrate holder 1 1 for securing a substrate 116 is provided in lower chamber 104, which includes a process gas inlet 122, a purge gas inlet 118 and an exhaust gas outlet 120. In a preferred embodiment of the present invention, process gas inlet 122 in conjunction with exhaust gas outlet 120 are appropriately sized and configured to ensure steady state flow of process gases inside lower chamber 104. Similarly, the placement of purge gas inlet 118 and exhaust gas outlet 120 of the present invention preferably enables a steady state flow of the purge gas underneath substrate 116.
Those skilled in the art will recognize that although the embodiment of Figure 4 shows two separate inlets, i.e. process gas inlet 122 and purge gas inlet 118, other embodiments of the present invention include a single gas inlet for introducing both purge and process gases inside lower chamber 104. In these embodiments, single gas inlet along with exhaust gas outlet 120 are preferably sized to ensure steady state flow of purge and process gases inside lower chamber 104.
Lower chamber 104 includes a temperature control mechanism, e.g. an infrared radiation (IR) lamp 124, as shown in Figure 4. and resistive heating, for controlling the substrate surface temperature. The IR lamp 124 may have a power rating of about 1000 Watts. As mentioned above, the power rating of IR lamp 124 may be lower or higher than about 1000 Watts. The placement of IR lamp 124 below substrate holder 114 should not be construed as limiting and such heating mechanisms may be placed inside lower chamber 104 in any configuration so long as substrate 116 reaches the desired temperature.
There is disposed between upper chamber 102 and lower chamber 104 a UV transmitting material 112 that is configured to transmit the UV radiation generated in upper chamber 102 to lower chamber 104. UV transmitting material 112, therefore, may be made from any material that is sufficiently transparent to or transmits UV radiation generated by UV bulbs 106, for example. In one preferred embodiment of the present invention, UV transmitting material 112 transmits about 90% or greater of the UV radiation that is incident upon it. In a preferred embodiment, however, UV transmitting material 1 12 is a high purity silica.
A surface passivation process, according to one embodiment of the present invention, begins when semiconductor substrate 116, for example, is secured on substrate holder 114. Gas inlet 108 and gas outlet 110 may be used in conjunction with valves to produce a steady state uniform flow of an inert gas in and out of the upper chamber 102 to produce an ozone free environment inside upper chamber 102 generally and in particular, around UV lamps 106. The flow of inert gas as described above may continue throughout substrate processing in lower chamber as described below.
In lower chamber 102, purge gas inlet 118 and exhaust gas outlet 120, similarly facilitate steady state uniform flow of purge gas, e.g., argon gas admixed with nitrogen gas, and ensure that an oxygen free, inert environment is maintained in lower chamber 104. Of course process gas inlet 122, which is responsible for introducing gas compositions to create an oxidizing environment in lower chamber 104, is at this point blocked off. After the appropriate inert environment is created inside lower chamber 104, substrate 116 is preheated to and maintained at the desired temperature using the selected heating mechanism.
The oxidant mixture or process gas composition is then introduced inside lower chamber 104 through process gas inlet 122 to create a steady state uniform flow of process gases inside chamber and the exhaust gases of lower chamber 104 are removed using exhaust gas port 120. In one embodiment of the present invention, the process gas composition continuously flows through lower chamber 104 from this point until before annealing of the substrate surface commences. The flow of inert gas from purge gas inlet 1 18 may continue during the oxidation step to maintain an appropriate concentration of oxygen inside lower chamber 104. Alternatively, in another embodiment of the present invention, oxidation is carried out in a stagnant oxidizing environment that is not maintained by continuous flow of the process gas composition.
Next, in accordance with one embodiment of the present invention, UV lamps 106 are activated to generate UV radiation, which is transmitted through UV transmitting material
112 to lower chamber 104. The UV radiation using the process gas composition inside lower chamber 104 produces ozone gas or the appropriate oxidizing environment within lower chamber 104. The substrate surface, while exposed to this oxidizing environment, undergoes passivation. After sufficient time elapses so that the substrate surface is passivated to the desired extent or an oxide layer of the desired thickness is fabricated over the substrate surface, the process gas supply and UV lamps 106 are turned off.
An inert gas environment may be produced before the temperature inside lower chamber 104 is modified to promote annealing of the substrate surface. By way of example, IR lamps 124 drive up the temperature inside lower chamber to increase the temperature of the substrate surface. Of course, if after the conclusion of the oxidation step, the temperature inside lower chamber 104 is the same as the annealing temperature, then the temperature need not be modified. Annealing of the substrate surface is carried out in an inert gas environment. In a preferred embodiment of the present invention, however, annealing is carried out in a noble gas environment. By way of example, the inert environment includes argon and/or nitrogen gas. Effective temperature and environment for annealing may be maintained inside lower chamber 104 for sufficient period of time to ensure that the oxidized surface is stabilized. After annealing of the substrate surface has concluded, the substrate surface undergoes cooling and the temperature inside the lower chamber may be adjusted for the processing of the next substrate surface. Table 1 shows approximate values of the various parameters in the surface passivation process, according to one embodiment of the present invention. The parameters of Table 1 include temperature, total flowrate of gases, concentration of oxygen gas, time, UV flux at wavelengths that are between about 100 - 300 nm. total UV flux. It should be borne in mind that the ranges for temperature, total gas flowrate and time in Table 1 apply to both oxidation and annealing of the substrate surface. The values of these parameters may be the same or different and it should not be construed that the values of these parameters are necessarily the same during oxidation and annealing.
Figure imgf000016_0001
Table 1
Temperature refers to the processing temperature of the substrate surface during the oxidation and annealing steps in lower chamber 104, for example. The desired temperature during oxidation and annealing of the substrate surface is generally sufficiently low to preserve at least one of: dopant concentration profile: oxygen precipitation level: and substrate mechanical properties. By way of example, substrate mechanical properties include flatness, warping and bowing of the substrate surface. In the case of an epitaxial silicon wafer, after substrate surface passivation, the dopant concentration profile, oxygen precipitation level, and substrate mechanical properties are substantially the same as before passivation or after the epitaxial layer is fabricated on the epitaxial silicon wafer. In a preferred embodiment, however, the temperature range is less than or equal to about 900 °C. in a more preferred embodiment the temperature range is less than or equal to about 600 °C and in a still more preferred embodiment, the temperature range is less than or equal to 200 °C.
Total flowrate of gases accounts for flowrate of all process gases or the oxidant gas mixture introduced into lower chamber 104 during the oxidation step. The total flowrate of annealing gases into lower chamber 104, during annealing, may be within the same range as the flowrate of the oxidant mixture. The total flowrate of gases generally ranges from about 0 to about 500 standard liters per minute, preferably ranges from about 0 to about 100 standard liters per minute and more preferably ranges from about 0 to about 50 standard liters per minute. The flowrate mentioned above is carried out in standard temperature and pressure, i.e. 25 °C and 1 atmosphere. It is worthwhile to note that the oxidation step of the present invention may be carried out at atmospheric pressure, but the prior art designs of surface passivation require oxidation under vacuum conditions. The present invention, therefore, obviates the need for complicated vacuum generating systems and the like, which are necessary to implement the prior art designs of oxidation.
Concentration of oxygen gas refers to the concentration of oxygen in the oxidant gas mixture flowrate, which is introduced into lower chamber 104 during the oxidation step. It is important to note that during preheating and annealing of the substrate surface, oxygen is not required in lower chamber 104. In accordance with one embodiment of the present invention, the concentration of oxygen gas in the total gas flowrate is a value that ranges from between about 10"4 (1 ppm) to about 100%, in a preferred embodiment, the concentration of oxygen gas ranges from between about 1 and about 25 % and in a more preferred embodiment, the concentration of oxygen gas ranges from between about 2 and about 5 %.
Time refers to the duration that the substrate surface is exposed to the oxidizing environment and to the duration that the substrate surface is exposed to the inert gas environment for annealing. Time generally ranges from between about 30 to about 900 seconds, preferably ranges from between about 45 to about 240 seconds and more preferably ranges from between about 60 to about 120 seconds.
UV flux at a frequency that is between about 100 - 300 nm is generally between about 0.1 Watts/m2 and about 1 kilo Watts/m2 and is preferably between about 50 Watts/m2 and about 700 Watts/m2 and more preferably is between about 500 Watts/m2 and about 700 Watts/m2.
Total UV flux may generally be between about 0.1 Watts/m2 and about 10 kilo Watts/m2 and is preferably between about 500 Watts/m2 and about 7000 Watts/m2 and more preferably is between about 5000 Watts/m2 and about 7000 Watts/m2. It should not be construed that UV generating is necessary to carry out the present invention. In fact, ozone generated ex-situ may be transported to lower chamber 104, which is maintained at low temperatures, to induce surface oxidation. In a preferred embodiment, however, the ozone may be generated using a UV source and in a more preferred embodiment, the ozone may be generated in-situ using the surface apparatus shown in Figure 4.
The surface passivation process of the present invention is generally performed at a pressure that is between about 0.100 and about 1500 Torr, preferably performed at a pressure that is between about 100 and about 800 Torr and more preferably performed at a pressure that is between about 100 and about 760 Torr.
After the substrate is cooled, the stability or loss of reactivity of the substrate surface may be confirmed through the reduction of the contact angle. According to the well known technique of contact angle measurement, a low contact angle, i.e. less than or equal to about 30°, is observed on the passivated surface. Such a low contact angle indicates that the passivated surface of the present invention is hydrophillic and stable. The passivated surface according to the present invention is more stable than passivated surfaces produced by the prior art surface passivation processes of thermal oxidation and wet chemistry. Thus, it is relatively easier to measure the electrical properties of the substrate layer underlying the passivated surface of the present invention compared to substrate layer underlying the passivated surface according to wet chemistry or thermal oxidation. The stability of the passivated substrate surface of the present invention is further confirmed using X-ray Photoelectron Spectroscopy
(XPS), Atomic Force Microscopy (AFM), Scanning Force Microscopy (SFM) or ellipsometery.
Regardless of the surface reactivity measuring technique employed, it is established that a semiconductor substrate processed according to the present invention is effectively passivated to include a high quality oxide surface layer that is at least of the same quality as or better than the oxide layer produced by thermal oxidation. The oxide layer advantageously lends itself to the non-contact or non-destructive measurement of the electrical properties, e.g., resistivity of the substrate layer underlying the passivated surface. The electrical properties of the underlying substrate layer are measured in a simple, fast, reproducible manner, which is totally independent of the period of time that passivated substrate surface is exposed to the environment. Consequently, a feed back loop, which provides new or modified input values of variables involved in epitaxial silicon production, are quickly provided to the process control of reactors associated with epitaxial layer deposition.
Furthermore, a substrate, which is selected to serve as the test substrate in a substrate production lot, does not undergo the high temperature treatments as it would have under thermal oxidation. Thus, the dopant concentration profile, oxygen precipitation level and mechanical properties of the substrate are substantially preserved. In the case of the epitaxial silicon wafer, in particular, processing at relatively low temperatures of the present invention ensures that the properties of the epitaxial silicon layer underlying the passivated surface are substantially preserved.
Further still, substrate processing according to the present invention provides the flexibility of surface passivation one substrate at a time or multiple substrates almost contemporaneously or simultaneously. In this context, it is noteworthy that thermal oxidation using a tube furnace, as described above, does not lend itself to single substrate processing, rather multiple substrates or batch processing is typically carried out and the Rapid Thermal Oxidation (RTO) apparatus is designed for processing one substrate at a time and not batch processing.
It can therefore be appreciated that new and novel surface passivation processes and apparatuses have been described. It will be appreciated by those skilled in the art that, given the teaching herein, numerous alternatives and equivalents will be seen to exist which incorporate the invention disclosed hereby. As a result, the invention is not to be limited by the foregoing exemplary embodiments, but only by the following claims.
What is claimed is:

Claims

1. A process for effectively reducing reactivity of a surface of a semiconductor substrate, comprising: oxidizing in an oxidizing environment said semiconductor substrate surface, said semiconductor substrate having a dopant concentration profile that extends into a depth of said semiconductor substrate; and annealing said semiconductor substrate surface in an inert gas environment, wherein said oxidizing and said annealing of said semiconductor substrate surface are performed at a temperature that is sufficiently low to substantially preserve said dopant concentration profile in said semiconductor substrate.
2. The process of claim 1, wherein the temperature in said oxidizing or annealing of said semiconductor substrate surface is below about 900 °C.
3. The process of claim 2, wherein the temperature in said oxidizing or annealing of said semiconductor substrate surface is below about 600 °C.
4. The process of claim 3, wherein the temperature in said oxidizing or C surface is below about 200 °C.
5. The process of claim 1, wherein before said oxidizing of said semiconductor substrate surface, introducing oxygen gas at a concentration that ranges from about 10'4 % to about
100% (by volume) of a total gas composition to produce said oxidizing environment.
6. The process of claim 5, wherein said introducing oxygen gas at a concentration that ranges from about 1% to about 25% (by volume) of a total gas composition to produce said oxidizing environment.
7. The process of claim 6, wherein said introducing oxygen gas at a concentration that ranges from about 2% to about 5% (by volume) of a total gas composition to produce said oxidizing environment.
8. The process of claim 1. wherein said oxidizing or annealing of semiconductor substrate surface is carried out for a period of time that ranges from between about 30 seconds to about 900 seconds.
9. The process of claim 8, wherein said a period of time ranges from between about 45 seconds to about 240 seconds.
10. The process of claim 9, wherein said a period of time ranges from between about 60 seconds to about 120 seconds.
11. The process of claim 1, wherein said oxidizing environment is produced by introducing a gas at a flowrate that ranges from between about 0 to about 500 standard liters per minute.
12. The process of claim 11, wherein said flowrate ranges from between about 0 to about 100 standard liters per minute.
13. The process of claim 12, wherein said flowrate ranges from between about 0 to about 50 standard liters per minute.
14 The process of claim 1, wherein said annealing of said semiconductor substrate surface is carried out in a noble gas environment.
15. The process of claim 1, wherein said oxidizing semiconductor substrate surface includes producing ozone in said oxidizing environment by directing UV radiation having a flux that ranges from between about 0.1 Watts/m2 to about 10 kilo Watts/m2.
16. The process of claim 15, wherein said UV flux ranges from between about 500 Watts to about 7 kilo Watts/m2.
17. The process of claim 16, wherein said UV flux ranges from between about 5 kilo Watts/m2 to about 7 kilo Watts/m2.
18. The process of claim 1, wherein said oxidizing semiconductor substrate surface includes producing ozone in said oxidizing environment by directing UV radiation that includes UV radiation having a frequency that ranges from between about 100 nanometers to about 300 nanometers.
19. The process of claim 18, wherein said UV radiation has a flux that ranges from between about 0.1 Watts/m2 to about 1 kilo Watts/m2.
20. The process of claim 1, wherein said oxidizing includes producing ozone outside said oxidizing environment and then transporting said ozone into said oxidizing environment.
21. The process of claim 1 , wherein said oxidizing is conducted at atmospheric pressure.
22. The process of claim 1, wherein said semiconductor substrate is an epitaxial silicon wafer having said dopant concentration profile that extends into a epitaxial silicon layer and a bulk silicon layer disposed below said epitaxial silicon layer, wherein said dopant concentration profile is substantially preserved after said oxidizing and said annealing of said epitaxial silicon wafer.
23. A process for effectively reducing reactivity of a surface of a semiconductor substrate, comprising: oxidizing in an oxidizing environment said semiconductor substrate surface, said semiconductor substrate having an oxygen precipitation level; and annealing said semiconductor substrate surface in an inert gas environment, wherein said oxidizing and said annealing of said semiconductor substrate surface are performed at a temperature that is sufficiently low to substantially preserve said oxygen precipitation level of said semiconductor substrate.
24. The process of claim 23, wherein the temperature in said oxidizing or annealing of said semiconductor substrate surface is below about 900 °C.
25. The process of claim 23, wherein before said oxidizing of said semiconductor substrate surface, introducing oxygen gas at a concentration that ranges from about 10"4 % to about 100%) (by volume) of a total gas composition to produce said oxidizing environment.
26. The process of claim 23, wherein said oxidizing or annealing of semiconductor substrate surface is carried out for a period of time that ranges from between about 30 seconds to about 900 seconds.
27. The process of claim 23, wherein said oxidizing environment is produced by introducing a gas at a flowrate that ranges from between about 1 to about 20 standard liters per minute.
28. The process of claim 1, wherein said annealing of said semiconductor substrate surface is carried out in a noble gas environment.
29. A process for effectively reducing reactivity of a surface of a semiconductor substrate, comprising: oxidizing in an oxidizing environment said semiconductor substrate surface, said semiconductor substrate having certain mechanical properties; and annealing said semiconductor substrate surface in an inert gas environment, wherein said oxidizing and said annealing of said semiconductor substrate surface are performed at a temperature that is sufficiently low to substantially preserve said mechanical properties of said semiconductor substrate.
30. The process of claim 29, wherein said mechanical properties include at least one property selected from the group consisting of flatness of said semiconductor substrate surface, degree of warping and bowing of said semiconductor substrate surface.
31. The process of claim 29, wherein the temperature in said oxidizing or annealing of said semiconductor substrate surface is below about 900 °C.
32. The process of claim 29, wherein before said oxidizing of said semiconductor substrate surface, introducing oxygen gas at a concentration that ranges from about 10"4 % to about 100%) (by volume) of a total gas composition to produce said oxidizing environment.
33. The process of claim 29, wherein said oxidizing or annealing of semiconductor substrate surface is carried out for a period of time that ranges from between about 30 seconds to about 900 seconds.
34. The process of claim 29, wherein said oxidizing environment is produced by introducing a gas at a flowrate that ranges from between about 1 to about 20 standard liters per minute.
35. The process of claim 29, wherein said annealing of said semiconductor substrate surface is carried out in a noble gas environment.
36. A surface passivation apparatus, comprising: a heating source for heating a substrate surface; an ozone generator; and a chamber for exposing a substrate surface to an oxidizing environment that includes a gas composition, wherein said ozone generator is configured to produce ozone within said chamber using said gas composition.
37. The apparatus of claim 36, wherein said heating source includes a infrared heating lamp.
38. The apparatus of claim 37, wherein said infrared heating lamp operates at a power of and less than about 1000 watts.
39. The apparatus of claim 36, wherein said infrared heating lamp operates at a power of and more than about 1000 watts.
40. The apparatus of claim 36, wherein said ozone generator is an ultraviolet (UV) frequency generating lamp.
41. The apparatus of claim 36. wherein said ultraviolet (UV) frequency generating lamp is maintained ozone free when said UV frequency generating lamp produces ozone inside said chamber.
42. The apparatus of claim 41, wherein a UV transmitting layer is disposed between said chamber and said ozone generator, said UV transmitting layer is at least substantially transparent to UV radiation and transmits at least a substantial portion of the UV radiation produced by the UV lamps.
43. The apparatus of claim 41 , wherein the UV transmitting layer transmits at least 90% of the UV radiation produced by the UV lamps.
44. The apparatus of claim 36, wherein said chamber is equipped with a gas inlet and a gas exhaust port such that substantially uniform flow of said gas composition is maintained inside said chamber.
45. A surface passivation apparatus, comprising: means for heating a substrate surface;
means for generating ozone; and means for exposing a substrate surface to an oxidizing environment that includes a gas composition, wherein said means for generating ozone is configured to produce ozone within said means for exposing using said gas composition.
46. The apparatus of claim 45, wherein said means for heating includes a infrared heating lamp.
47. The apparatus of claim 46, wherein said infrared heating lamp operates at a power of and less than about 1000 watts.
48. The apparatus of claim 45, wherein said means for generating ozone is an ultraviolet (UV) frequency generating lamp.
49. The apparatus of claim 48, wherein said ultraviolet (UV) frequency generating lamp is maintained ozone free when said UV frequency generating lamp produces ozone inside said chamber.
50. The apparatus of claim 45, wherein a UV transmitting layer is disposed between said means for exposing and the UV frequency generating lamps, said UV transmitting layer is at least substantially transparent to UV radiation and transmits a substantial portion of the UV radiation produced by the UV frequency generating lamps.
51. The apparatus of claim 45, wherein the UV transmitting layer transmits at least 90% of the UV radiation produced by the UV lamps.
52. The apparatus of claim 45, wherein said means for exposing is equipped with a gas inlet and a gas exhaust port such that substantially uniform flow of said gas composition is maintained inside said means for exposing.
PCT/US2000/000185 1999-01-12 2000-01-05 System and method for surface passivation WO2000042644A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP00903112A EP1142007A1 (en) 1999-01-12 2000-01-05 System and method for surface passivation
JP2000594145A JP2002535833A (en) 1999-01-12 2000-01-05 Surface passivation system and method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/229,137 1999-01-12
US09/229,137 US6511921B1 (en) 1999-01-12 1999-01-12 Methods for reducing the reactivity of a semiconductor substrate surface and for evaluating electrical properties of a semiconductor substrate

Publications (2)

Publication Number Publication Date
WO2000042644A1 true WO2000042644A1 (en) 2000-07-20
WO2000042644A9 WO2000042644A9 (en) 2001-08-23

Family

ID=22859971

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/000185 WO2000042644A1 (en) 1999-01-12 2000-01-05 System and method for surface passivation

Country Status (4)

Country Link
US (1) US6511921B1 (en)
EP (1) EP1142007A1 (en)
JP (1) JP2002535833A (en)
WO (1) WO2000042644A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101728239B (en) * 2009-11-10 2013-01-30 上海宏力半导体制造有限公司 Removal method of water vapor on crystal wafer surface

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6408535B1 (en) * 1999-08-26 2002-06-25 Semitool, Inc. Ozone conversion in semiconductor manufacturing
JP4914536B2 (en) * 2001-02-28 2012-04-11 東京エレクトロン株式会社 Oxide film formation method
EP1593145A2 (en) * 2002-10-30 2005-11-09 Amberwave Systems Corporation Methods for preserving strained semiconductor layers during oxide layer formation
JP4973133B2 (en) * 2005-11-10 2012-07-11 株式会社Ｓｕｍｃｏ Epitaxial layer pretreatment method, epitaxial layer evaluation method, and epitaxial layer evaluation apparatus
JP4940737B2 (en) * 2006-04-11 2012-05-30 株式会社Ｓｕｍｃｏ Minority carrier diffusion length measuring method and silicon wafer manufacturing method
JP2010087475A (en) * 2008-09-03 2010-04-15 Hitachi Kokusai Electric Inc Method and device for manufacturing semiconductor device
KR101235419B1 (en) * 2011-05-26 2013-02-20 주식회사 엘지실트론 Surface treatment method of silicon epitaxial wafer
CN109643638B (en) * 2016-09-16 2023-09-05 应用材料公司 Ultraviolet radiation system and method for controlling arsenic outgassing in sub-7 nanometer CMOS fabrication

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61234532A (en) * 1985-04-11 1986-10-18 Nec Corp Device for photochemical gas phase growth of silicon oxide film
JPS63129633A (en) * 1986-11-20 1988-06-02 Fujitsu Ltd Surface treatment for semiconductor
US5294571A (en) * 1992-07-22 1994-03-15 Vlsi Technology, Inc. Rapid thermal oxidation of silicon in an ozone ambient
US5738909A (en) * 1996-01-10 1998-04-14 Micron Technology, Inc. Method of forming high-integrity ultrathin oxides
EP0889514A1 (en) * 1993-07-16 1999-01-07 Shin-Etsu Handotai Company Limited Method for determination of resistivity of N-type silicon epitaxial layer
WO1999060615A2 (en) * 1998-05-21 1999-11-25 Memc Electronic Materials, Inc. Process for the preparation of epitaxial wafers for resistivity measurements

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4409260A (en) * 1979-08-15 1983-10-11 Hughes Aircraft Company Process for low-temperature surface layer oxidation of a semiconductor substrate
EP0306069A3 (en) * 1987-08-31 1990-12-27 Koninklijke Philips Electronics N.V. A method of forming an oxide layer on a substrate
JPH031322A (en) * 1989-05-30 1991-01-08 Nippon Sheet Glass Co Ltd Magnetic recording medium and its production
JPH07118522B2 (en) * 1990-10-24 1995-12-18 インターナショナル・ビジネス・マシーンズ・コーポレイション Method and semiconductor structure for oxidizing a substrate surface
KR930009549B1 (en) * 1990-11-28 1993-10-06 현대전자산업 주식회사 High resistivity attaining method of poly-silicon
US6146135A (en) * 1991-08-19 2000-11-14 Tadahiro Ohmi Oxide film forming method
JPH05306455A (en) * 1992-04-30 1993-11-19 Shimadzu Corp Film forming device
CN1244891C (en) * 1992-08-27 2006-03-08 株式会社半导体能源研究所 Active matrix display
US5264396A (en) * 1993-01-14 1993-11-23 Micron Semiconductor, Inc. Method for enhancing nitridation and oxidation growth by introducing pulsed NF3
US5946588A (en) * 1994-12-07 1999-08-31 Micron Technology, Inc. Low temperature sub-atmospheric ozone oxidation process for making thin gate oxides
JP2937817B2 (en) * 1995-08-01 1999-08-23 松下電子工業株式会社 Method of forming oxide film on semiconductor substrate surface and method of manufacturing MOS semiconductor device
US5709754A (en) * 1995-12-29 1998-01-20 Micron Technology, Inc. Method and apparatus for removing photoresist using UV and ozone/oxygen mixture

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61234532A (en) * 1985-04-11 1986-10-18 Nec Corp Device for photochemical gas phase growth of silicon oxide film
JPS63129633A (en) * 1986-11-20 1988-06-02 Fujitsu Ltd Surface treatment for semiconductor
US5294571A (en) * 1992-07-22 1994-03-15 Vlsi Technology, Inc. Rapid thermal oxidation of silicon in an ozone ambient
EP0889514A1 (en) * 1993-07-16 1999-01-07 Shin-Etsu Handotai Company Limited Method for determination of resistivity of N-type silicon epitaxial layer
US5738909A (en) * 1996-01-10 1998-04-14 Micron Technology, Inc. Method of forming high-integrity ultrathin oxides
WO1999060615A2 (en) * 1998-05-21 1999-11-25 Memc Electronic Materials, Inc. Process for the preparation of epitaxial wafers for resistivity measurements

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
NAYAR V ET AL: "ATMOSPHERIC PRESSURE, LOW TEMPERATURE (<500 DEG C) UV/OZONE OXIDATION OF SILICON", ELECTRONICS LETTERS,GB,IEE STEVENAGE, vol. 26, no. 3, 1 February 1990 (1990-02-01), pages 205 - 206, XP000106040, ISSN: 0013-5194 *
PATENT ABSTRACTS OF JAPAN vol. 011, no. 081 (E - 488) 12 March 1987 (1987-03-12) *
PATENT ABSTRACTS OF JAPAN vol. 012, no. 385 (E - 668) 14 October 1988 (1988-10-14) *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101728239B (en) * 2009-11-10 2013-01-30 上海宏力半导体制造有限公司 Removal method of water vapor on crystal wafer surface

Also Published As

Publication number Publication date
JP2002535833A (en) 2002-10-22
EP1142007A1 (en) 2001-10-10
US6511921B1 (en) 2003-01-28

Similar Documents

Publication Publication Date Title
US5620559A (en) Hydrogen radical processing
EP1340247B1 (en) Method of forming dielectric films
US6107197A (en) Method of removing a carbon-contaminated layer from a silicon substrate surface for subsequent selective silicon epitaxial growth thereon and apparatus for selective silicon epitaxial growth
US5259883A (en) Method of thermally processing semiconductor wafers and an apparatus therefor
TW577129B (en) Method for fabricating semiconductor integrated circuit device
JP2007142442A (en) Method for rapid thermal processing (rtp) of silicon substrate
GB2136258A (en) Method and apparatus for the heat-treatment of a plate-like member
US20070065593A1 (en) Multi-source method and system for forming an oxide layer
KR102227883B1 (en) Atomic layer etching process using plasma with rapid thermal activation process
CN100338744C (en) Method and device for forming oxide film
JP4582608B2 (en) Method for producing a silicon oxynitride film
US6511921B1 (en) Methods for reducing the reactivity of a semiconductor substrate surface and for evaluating electrical properties of a semiconductor substrate
WO2000042644A9 (en) System and method for surface passivation
US7501352B2 (en) Method and system for forming an oxynitride layer
WO1999021219A1 (en) Method of oxidation of semiconductor wafers in a rapid thermal processing (rtp) system
JP3233281B2 (en) Method of forming gate oxide film
JP2006093218A (en) Lamp heating device and manufacturing method of semiconductor device
US7517814B2 (en) Method and system for forming an oxynitride layer by performing oxidation and nitridation concurrently
JPH08148552A (en) Semiconductor thermal treatment jig and its surface treatment method
JP2003347241A (en) Carbon thin film removing method, surface modifying method, and treatment device therefor
JPH0697157A (en) Use of oxyalkyl chloride for manufacture of silicon dioxide film doped with chloride on silicon substrate
JPH0897206A (en) Forming method of thermal oxidation film
JP2005347654A (en) Forming method of copper surface protection film and processing method of copper surface where protection film is formed
Nishiguchi et al. Rapid and uniform SiO2 film growth on 4 inch si wafer using 100%-O3 gas
JPH07268627A (en) Heat treating method

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
ENP Entry into the national phase

Ref country code: JP

Ref document number: 2000 594145

Kind code of ref document: A

Format of ref document f/p: F

WWE Wipo information: entry into national phase

Ref document number: 2000903112

Country of ref document: EP

COP Corrected version of pamphlet

Free format text: PAGES 1/3-3/3, DRAWINGS, REPLACED BY NEW PAGES 1/2-2/2; DUE TO LATE TRANSMITTAL BY THE RECEIVING OFFICE

WWP Wipo information: published in national office

Ref document number: 2000903112

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 2000903112

Country of ref document: EP