WO2000041136A1 - Method and apparatus for synchronizing graphics pipelines - Google Patents

Method and apparatus for synchronizing graphics pipelines Download PDF

Info

Publication number
WO2000041136A1
WO2000041136A1 PCT/US2000/000549 US0000549W WO0041136A1 WO 2000041136 A1 WO2000041136 A1 WO 2000041136A1 US 0000549 W US0000549 W US 0000549W WO 0041136 A1 WO0041136 A1 WO 0041136A1
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WO
WIPO (PCT)
Prior art keywords
pipelines
pipeline
graphics
ready
local
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2000/000549
Other languages
English (en)
French (fr)
Inventor
Andrew D. Bowen
Gregory C. Buchner
Remi Simon Vincent Arnaud
Daniel T. Chian
James Bowman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Graphics Properties Holdings Inc
Original Assignee
Silicon Graphics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Graphics Inc filed Critical Silicon Graphics Inc
Priority to JP2000592791A priority Critical patent/JP4249397B2/ja
Priority to AU24987/00A priority patent/AU2498700A/en
Priority to EP00903207.9A priority patent/EP1147489B1/en
Publication of WO2000041136A1 publication Critical patent/WO2000041136A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—Three-dimensional [3D] image rendering
    • G06T15/005—General purpose rendering architectures

Definitions

  • the present invention relates generally to systems for computer graphics.
  • the present invention includes a method and apparatus for
  • Computer systems typically create three-dimensional
  • Each primitive is defined in terms of its
  • the graphics pipeline maps each primitive into a memory storage device
  • Each storage location within the frame buffer defines one
  • the graphics pipeline performs the mapping
  • Each pixel is then initializes to reflect the attributes of
  • the graphics processing unit or primitives in which it is included.
  • the graphics processing unit or primitives in which it is included.
  • the graphics processing unit or primitives in which it is included.
  • One method for improving the speed of the rendering process is to use
  • subdividing the rendering task is to assign a fixed portion of each image to a
  • the synchronization problem may be overcome through
  • SILICON GRAPHICS INC. provides a signal of this
  • SWAP_READY type, known as SWAP_READY, for use with certain types of SGI computers.
  • SWAP_READY signal is physically connected to each graphics pipelines that is to
  • SWAP_READY functions as a logical AND of these local ready signal.
  • SWAP_READY becomes asserted when all systems are ready to output
  • the graphics pipelines sample the state of the SWAP_READY signal on a periodic, synchronized basis.
  • the pipelines output their image portions
  • a second way to combine multiple graphics pipelines is to subdivide the
  • each pipeline contributes a succeeding image to a sequence of images.
  • a synchronization method such as a
  • one or more graphics pipelines are connected as a daisy-chain
  • Each pipeline may be configured to operate in two different modes: local and
  • Pipelines operating in local mode output their own digital video data
  • pass-through mode output the video data that they receive from preceding pipelines.
  • an application program configures the sequence of pipelines so
  • program selects the next pipeline for operation in local mode. Shortly after the
  • the timing of swap events is based on the state of a global ready signal.
  • global ready signal represents a logical AND of a set of local ready signals.
  • the sequence of pipelines also operates in a mode that is compatible
  • Figure 1 is a block diagram showing three graphics pipelines configured to
  • FIG. 2 is a block diagram showing the internal details of the pipeline
  • Figure 3 is a block diagram showing the pipeline sequence of Figure 1
  • Figure 4 is a block diagram showing a single image divided into three image
  • rendering system 100 is intended to represent a sequential grouping of a series of
  • graphics pipelines 102a through 102c are shown. Each of these graphics pipelines
  • Graphics pipelines 102 are connected as a daisy chain sequence. This
  • Each pipeline 102 is connected to a host processor 106.
  • Host processor 106 Host processor 106
  • connection between host processor 106 and graphics pipelines 102 is also intended
  • bus interconnects and
  • Host processor 106 controls the execution of pipelines 102. Under the control of host processor 106, graphics pipelines 102 produce
  • pipelines 102 is synchronized. This means that graphics pipelines 102 produce
  • pipeline 102 includes a multiplexer 200.
  • Multiplexer 200 has two inputs. The first of
  • each multiplexer except the first is connected to the output of
  • multiplexer 200 is connected to a null device.
  • Each pipeline 102 includes three state bits: a current bit 202, a next bit 204
  • multiplexer 200 selects its first input. In this
  • multiplexer 200 outputs the digital video output of the pipeline 102 in
  • multiplexer 200 selects its second input. In this
  • multiplexer 200 outputs the digital video data it receives from
  • Next bit 204 contains the next value for current bit 202. As will be described in
  • pipelines 102 transfer the value included in next bit 204 to current bit 202 as part of each swap event. In this way, each next bit 204 controls the next state
  • next bit 204 is set or cleared using a command sent
  • host processor 106 This allows a host application to dynamically select the next
  • pipeline 102 to output video data.
  • pipelines 102 are each connected to produce a
  • Host processor 106 uses ready disable bits 206 to
  • ready disable bits 206 are set or cleared
  • Graphics pipelines 102 are connected to monitor the state of global ready
  • Global ready signal 210 is configured to act as a logical AND of its
  • global ready signal 210 enters an asserted state whenever one
  • ready signal 210 become asserted whenever a pipeline 102 having a set next bit
  • the synchronization subsystems sample global ready signal 210 at the beginning of each pulse of the vertical synchronization signal.
  • pipeline 102 moves the value stored in its next bit 204 into its current bit 202.
  • graphics pipeline 102 also clears its next bit 204. If the movement of next bit 204
  • multiplexer 200 enters local mode operation. In all other cases,
  • multiplexer 200 either enters or stays in pass-through mode.
  • an application process executing on host processor 106,
  • the host corresponds to a series of images that are to be generated by pipelines 102.
  • the host corresponds to a series of images that are to be generated by pipelines 102.
  • the host application then sends commands to graphics pipelines 102 to set the next
  • graphics pipelines 102 and all other graphics pipelines 102 sample global ready
  • each graphics pipeline moves its next bit 204 to its
  • next bit 204 is set. This
  • pipelines 102 to either enter or remain in pass-through mode operation.
  • Host processor 106 continues the rendering process by repeatedly setting
  • the present invention provides a flexible
  • the present invention also provides for synchronized execution between
  • sequences of graphics pipelines (such as the sequence of graphics pipelines 102
  • Figure 3 includes the three sequential pipelines 102a - 102c of Figure 2. In this
  • sequential pipelines 102a - 102c produce a series of images for a portion of display
  • the remaining pipelines 102d and 102e each provide images for additional
  • sample image 400 is shown.
  • Sample image 200 is subdivided into three portions
  • pipelines 102d and 102e is achieved by configuring pipelines 102d and 102e to
  • Pipelines 102d and 102e are

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Graphics (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Image Processing (AREA)
  • Image Generation (AREA)
  • Processing Or Creating Images (AREA)
  • Multi Processors (AREA)
PCT/US2000/000549 1999-01-08 2000-01-07 Method and apparatus for synchronizing graphics pipelines Ceased WO2000041136A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2000592791A JP4249397B2 (ja) 1999-01-08 2000-01-07 グラフィックス・パイプラインを同期化する方法および装置
AU24987/00A AU2498700A (en) 1999-01-08 2000-01-07 Method and apparatus for synchronizing graphics pipelines
EP00903207.9A EP1147489B1 (en) 1999-01-08 2000-01-07 Method and apparatus for synchronizing graphics pipelines

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/227,227 US6329996B1 (en) 1999-01-08 1999-01-08 Method and apparatus for synchronizing graphics pipelines
US09/227,227 1999-01-08

Publications (1)

Publication Number Publication Date
WO2000041136A1 true WO2000041136A1 (en) 2000-07-13

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Family Applications (1)

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PCT/US2000/000549 Ceased WO2000041136A1 (en) 1999-01-08 2000-01-07 Method and apparatus for synchronizing graphics pipelines

Country Status (5)

Country Link
US (1) US6329996B1 (https=)
EP (1) EP1147489B1 (https=)
JP (1) JP4249397B2 (https=)
AU (1) AU2498700A (https=)
WO (1) WO2000041136A1 (https=)

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US8326819B2 (en) 2006-11-13 2012-12-04 Exegy Incorporated Method and system for high performance data metatagging and data indexing using coprocessors
US8374986B2 (en) 2008-05-15 2013-02-12 Exegy Incorporated Method and system for accelerated stream processing
US8379841B2 (en) 2006-03-23 2013-02-19 Exegy Incorporated Method and system for high throughput blockwise independent encryption/decryption
US8620881B2 (en) 2003-05-23 2013-12-31 Ip Reservoir, Llc Intelligent data storage and processing using FPGA devices
US8762249B2 (en) 2008-12-15 2014-06-24 Ip Reservoir, Llc Method and apparatus for high-speed processing of financial market depth data
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EP1147489A1 (en) 2001-10-24
US6329996B1 (en) 2001-12-11
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JP2002534750A (ja) 2002-10-15
AU2498700A (en) 2000-07-24
JP4249397B2 (ja) 2009-04-02

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