GB2223335A - Improved data processing - Google Patents

Abstract

A data bus processing system has a host processor 10 interfaced with a bus controller 12 which arranges for rapid data transfer from a host memory 14 to the memories of any one of a number of devices such as 24', 26', on GBUS 16. To speed up operation, each device 24', 26' has a buffer memory with direct memory access in parallel with the GBUS. One of said devices includes a system controller 28 controlled by the processor 10 and, in each device which includes a processor (e.g. 30), the function control input of the processor is instructed by the host processor 10 via the bus controller 12. The system may be used for image processing. <IMAGE>

Description

Title: Improved Data Processing Field of the Invention This invention concerns data processing methods and apparatus. It is particularly concerned with systems for processing large quantities of data at very hlgh speed as in the case of digitised image processing.

Background to the Invention In a typical image data processing system digitised image data relating to a raster scanned original image is stored in a frame store memory associated with a work station and is displayable on a monitor associated with the work station often as a part of an overall display either as raw data (ie a reproduction of the original image) or as processed data representing some function (for example inversion or rotation) of the original image data.Thus for example a typical screen display on the monitor may comprise down one edge region of the screen a menu of processing functions selectable for example by means of a screen mouse or light pen or the like, and in a rectangular area located in the remainder of the screen, a display of a selected region of the original image either as directly read out from the frame store or after processing (such as inversion, rotation etc).

One of the problems associated with such data display systems is the considerable time required to perform any particular processing of the image data. Merely transferring data out of a frame store, through a processor and into a screen memory, for display on a monitor, can sometimes take many seconds or even minutes depending on the size of the image and the number of pixels in the image and the speed and power of the processor. Where high definition colour pictures are involved, the time for processing and display of a processed image can be very considerable and the lack of immediacy is not only disconcerting to the user, but when wanting to compare for example image data processed in one way with the same image data after processing in another way, the time delay can interfere with the comparison.

The problem is further aggravated if the processing is complex and itself introduces a significant processing delay.

It is an object of the present invention to speed up the processing of data, particularly image data, to enable virtually instantaneous transitions between one field and another field, which may for example comprise the same array of data which made up the first field, after one or more signal processing steps such as inversion of the data.

Summary of the Invention According to the present invention in a data processing system which includes a parallel data BUS along which data is to be transmitted between one device and another, inter alia for processing and for storage, an improvement in the overall speed of operation is achieved if, 1. Each device includes a buffer memory with a direct memory access (DMA) interface into and out of which data can be read in parallel format to and from the BUS, and wnere the device is to perform processing on the data in the buffer memory a programmable microprocessor (which may be a Transputer) is associated therewith; 2.One of the devices linked to the BUS via a DMA interface comprises a system controller to which operating commands are sent from a master controller, for the purpose of sending address data and intercepts via the BUS to one or more other devices connected thereto, for sending and receiving data; and 3. In each processing device linked to the BUS, the function control input of the Transputer is supplied with control signals from the system controller to perform particular functions (such as inversion) on data stored in the buffer memory associated therewith, by reading the data out of the buffer memory, processing data and returning the processed data to the buffer memory.

The term Transputer is believed to be a registered Trade Mark.

An increase in operating speed is achieved in two ways.

In the first place data to be processed does not occupy the BUS during processing, thereby leaving the BUS free for other data transfers.

In the second place the data which is being processed only has to be transferred into and out' of the local buffer memory associated with the corresponding Transputer, and before and after processing, the data is delivered to the local buffer memory and back either to the main memory or into a screen memory or to another buffer memory using the direct memory access interfaces and the high speed data transfer capacity of the full parallel data highway of the BUS, thereby allowing the very rapid transfer of large blocks of data, before and after processing, from one device to another.

A further increase in operating speed is achieved by providing N parallel subsystems in each device each including its own buffer memory (and if required a processor), and when transferring data from a master memory into the device, the system controller sequentially identifies memory addresses in the N buffer memories of the N subsystems so that the block of data removed from the master memory is distributed between the N buffer memories within the device.

Where the device is simply a memory, the N subsystems each comprise a buffer memory. A single DMA interface may be provided for all of the buffer memories or an individual DMA interface may be provided for each buffer memory.

Where processing is required in the device, each subsystem additionally includes a Transputer controlled by data from the system controller, for reading, processing and restoring data from its associated buffer memory. Where the system includes two or more Transputers these are conveniently linked so that instructional data can be pipelined to the Transputers from the master controller N host computer. By simultaneously instructing the N transputers to process the data in each of the N associated buffer memories, so the time taken to process the original block of data removed from the master memory is reduced to 1/N th of the time required if only one transputer and larger buffer memory were employed, (assuming that the time taken to load and read the larger buffer memory is no longer than the time taken to load and read the smaller buffer memories).

As a consequence of these refinements it has proved possible to process digital data representative of a complete screen of 625 lines of a high definition colour television picture in a typical frame scan period, thereby enabling apparently instantaneous changes to occur in a displayed picture following an instruction from the master controller to process image data in a particular way.

Experiments to date have indicated that a data transfer rate of the order of 640 Megabits per second, between one device and another on the BUS, is achievable.

Preferably a BUS controller is provided which is supplied with a list of parameters from the master controller (typically a host computer) which define the transfers to be performed.

Typically the BUS includes 64 parallel data paths, 8 byte write lines and 5 memory control lines, which operate to move data from one device to another in a pipelined fashion, 2 control lines to set up the memory start, addresses for the source and each destination device, using the 64 data lines during the quiescent period just before each line transfer; 4 lines to detect the rate of the slowest addressed device to thereby ensure that the rate of addressing does not exceed that limit; 6 lines to deal with interrupts which may be required either by the addressed devices or the BUS controller; and 1 reset line.

Conveniently control registers are provided in the devices and an auxiliary data highway is provided in addition, comprising 16 data lines, 12 address lines and 3 handshake control lines, to write to or read from the control registers. The auxiliary highway may operate independently of and simultaneously with the main 64 line data highway.

By adjusting the clock rate of the synchronous transfers at the begining of any data transfer, and setting the clock rate to a value that matches the devices involved, enables BUS transfer rates to be higher where the devices are capable of it, thus optimising overall system performance. Typically up to 16 destinations can be specified for simultaneous receipt of data during a single block transfer of data and this feature is of considerable importance in obtaining high speed of execution for certain algorithms and functions where parallel processing is required.

In operation the host computer or other master controller which is controlling the sequence of transfers on the BUS, is interfaced to a system controller and under commands of the system controller, the transputer link pipelines and the BUS microcontroller pass commands and data between image processing devices in order to perform a desired algorithm.

The transputer link facility of the system controller allows these links to be used in addition to the BUS, where transputer devices are on the BUS. The transputer link pipelines are then primarily used to set up parallel processing operations in transputer based devices on the BUS. Data for these processes is sent in parallel via the BUS, as there is generally a larger volume and the greater BUS band width is of benefit.

As previously mentioned the BUS has two transfer paths.

Thus a 64 bit wide path may be used for the high bandwidth block transfers of data. Conveniently this uses a format suited to the DRAM and VRAM devices of any volumetric image store linked to the BUS, the buffer working memories associated with transputers linked to the BUS and any display generator frame stores. This data transfer path would typically operate at rates of and aDove 640 Megabits per second and addresses, set up as a base address, may be multiplexed onto the path during the set up phase of a block transfer. Typically devices on the BUS auto increment their addresses internally during the data block transfer.

The second path is conveniently 28 bits wide and may be used for command, status, short data set, and supervisory transfers. This second supervisory path typically uses a handshake protocol at rates of the order of 2 megawords per second. Typically word length may be at 8 or 16 bits.

Double word transfers permit up to 32 bits of data to be transferred to a given address. 16 datalines may for example work in parallel with 12 address lines. Again devices typically auto increment internal addresses when accepting short data sets.

Preferably the supervisory path can conduct transfers at the same time as and asynchronously with the data transfer path. This will allow real time monitoring of data transfer processes by the supervisory function.

Typically the BUS micro controller is mapped into the memory space of the system controller. Address blocks may be defined for the various control and data functions to be performed and the BUS micro controller conveniently has two parts, one for driving the data transfer BUS, and the other for driving the supervisory BUS.

In an address setting mode, addresses for the block transfers may be issued on the 64 bit path during the initial phase of a block transfer of data.

In the block transfer mode, data blocks of an arbitrary number of bytes may be transferred synchronously from a device linked to the BUS to any one or a number of destinations across the 64 bit path. Typically the block address counter is arranged to provide addresses for up to 64 Megabytes.

In the supervisory transfer mode, the 28 bit data path may be employed to transfer command and status information concerning data block transfers which are in progress on the 64 bit data path. This gives the system controller the ability to monitor the large block transfers in real time.

The BUS may be operated in a data set transfer mode and in this context data sets are small blocks of data which are written to ancillary memories in devices on the BUS. In general the format of such data blocks is not suited to 64 bit DRAM organised data format. Such data sets are typified by blocks of data for look up tables. Here the transfers are preferably made on the 28 bit data path and such devices are provided with address counters and the latter are initially loaded with a base address and then auto incremented as each BUS word is sent.

In the multiple destination mode the BUS can operate in the same way as in the block transfer mode, except that during the initialising phase of the block transfer, more than one destination device is instructed to receive the data from the source device as it is clocked onto the BUS In this mode, equivalent transfer speeds of the order of 10 Gbits per second can be envisaged.

Typically the system controller employs a single transputer-type T800 running at a clock rate of 20 MHz with 2 Mbyte of dedicated random access memory (RAM).

Nominal performance of this particular transputer is 1.5 Megaflops (or 4000 K Whetstones) per second.

Tne master controller conveniently comprises a host computer such as an Apollo work station as produced by Apollo Computers or a SUN work station as produced by Sun Microsystems Inc.

The invention will now be described by way of example with reference to the accompanying drawings in which: Figure 1 is a general schematic view of BUS system architecture embodying the invention, Figure 2 shows a typical transfer operation using the BUS of Figure 1, Figure 3 is a block schematic diagram showing the elements making up the BUS micro control unit, Figure 4 illustrates typical parameters to be stored in the parameter store of the BUS micro control unit, Figure 5 shows how a control word can be separated into fields of significance, Figure 6 illustrates the hardware architecture of a complete data processing system using a host computer as the master controller.

In order to distinguish the high speed parallel path data BUS of the invention from other BUS architecture, the 64 bit wide data highway will be referred to as a GBUS.

In the general view of a GBUS system shown in Figure 1, a host processor such as an Apollo or SUN work station computer 10 is shown interfaced with a GBUS controller 12.

The latter organises the addressing of different devices attached to the GBUS and also allows data to be transferred from a disc memory or the like 14 associated with the host computer 10 via the GBUS into one or more of the memories of the devices linked to the GBUS.

The GBUS is designated by reference numeral 16 and in order to obtain maximum advantage from the system, a bulk RAM memory 18 is shown linked to the GBUS for storing large quantities of digital data from the memory 14 for subsequent processing.

Alternatively, if desired, a direct link may be provided from the host computer memory 14 to the GBUS provided an appropriate DMA interface is available to obtain maximum data transfer rates into and out of the host computer memory 14.

The memory 18 includes a port which includes a DMA interface to allow rapid transfer of data into and out of the memory.

Other devices may be linked to the GBUS such as disc memories, tape streamers, satellite links and the like and an appropriate interface such as 20 gathers the inputs and distributes the outputs from the GBUS to and from the devices linked thereto and in common with all of the other devices, the interface 20 is itself interfaced to the GBUS lb via a local buffer memory 22 provided with DMA so as to maximise data transfer rates.

Processing of data stored in the master memory device 18 is pertormed by general or special purpose programmable processors such as Transputers and two devices are shown linked to the GBUS at 24 and 26 one containing a general purpose programmable processor or Transputer 28 the other containing a processor 30 chosen for a particular range of applications requiring higher speed. The latter are linked via appropriate DMA access to their own local butter memories 32 and 34 respectively and the local buffer memories 32 and 34 are likewise interfaced to the GBUS via DMA ports, again to maximise data transfer to and from the local buffer memories.

In the event that data from the memory 18 is to be processed, the host computer 10 instructs the GBUS controller 12 to transfer data from the memory 18 to one or both of the memories 32 and 34 and control data from the host computer via controller 12 at 36 and 38 serves to program the processors 28 and 30 to perform the desired processing junction on the data in the associated memories 32 and 34.

On a subsequent command data is streamed from the memories 32 and 34 into the processors 28 and 30 and after processing is typically restored in the memories 32 and 34.

After processing, the GBUS controller can access the data stored in the memories 32 and 34 and download the processed data via the GBUS 16 either back to the main memory 18, (for example to replace the data previously stored in the memory 18) or more typically into one or more other buffer memories such as 22, 24' or 26'.

It routed to memory 22, a subsequent command from the GBUS controller along instruction path 40 will cause the information stored in the memory 22 to be transmitted for storage for example on a disc or a tape or transmitted via satellite link.

In the case of memory 24', control data along path 42 from the host computer via the GBUS controller 12 will initiate an image display engine 44 to access data in the memory 24' and display it on the monitor screen 46.

Although no active processing memory or storage device is shown linked to the memory 26', it will be appreciated that whatever is connected to the memory 26', can also be instructed by the GBUS controller 12 to access the data transferred to memory 26' and either process it, display it or store it.

In all cases except the image display engine 44, the data highway between the local buffer memory and the processor distributor or other subsystem, is a two way highway and for example in the case of a processor such as 28, information can pass from the memory into the processor and from the processor back to the memory.

The GBUS is therefore a device whereby a number of independently operating devices can transfer data between themselves at a high data rate. A sustained data rate of 640 Megabits per second has been achieved and although the number of devices which can be linked to the GBUS is apparently unlimited, practical considerations indicate that typically 15 or 16 such devices is probably a sensible maximum number.

Figure 1 is merely intended to illustrate some of the device types and subsystems which can be connected to a GBUS in a data processing system particularly one adapted to handle image data.

The invention solves the problem of moving data from sources of information to processors of that information and then moving the processed information to output destinations at rates compatible with "real time" moving colour pictures of raster scan CRT type. This problem is particularly acute for image processing applications where several processors may have to operate in parallel.

Figure 2 shows a typical transfer operation. In this mode, the memory 18 is shown as the source of data and two destinations are shown at 48 and 50 each of which under the action of the controller 12 are arranged to receive data from the memory 18 via the GBUS data highway 16. The same data may be transferred to local buffer memories 52 and 54 of the devices 48 and 50 or by appropriate addressing, a first block of data removed from the memory 18 may be stored in the local buffer memory 52 and a second block of data similarly removed from the memory 18 may be stored in the local buffer memory 54.

It will be seen that where the same data is to be acted on in a number of different paths in parallel, the parallel transfer of data en bloc from one memory to all of the other memories simultaneously, and the local processing of each separately stored block of data, represents a considerable enhancement over the time which would otherwise be required where the data is read out from the master memory into the processors and is returned from the processors to the master memory.

In the situation where a large amount of data is to be processed using a single algorithm, two or more processors may be organised so as to perform the same processing algorithm on any data presented to them, and the large quantity of data can be divided into two (or more) blocks (depending on the number of parallel processors available) and the different blocks of information are stored in the local buffer memories and are available for processing in parallel by the processors associated with the buffer memories. Since each processor can begin processing the data stored in its own buffer memory as soon as data from the master memory has been entered, it is quite possible for the first processor to have processed all of the data stored in its own local buffer memory by the time that the last block of data has been stored in the Nth buffer memory.The processed data now stored in the local buffer memory associated with the first device 48, can now be returned to the master memory 18 or to a screen memory of an image engine, for display purposes, and that from the other buffer memories in sequence.

By writing to several destinations simultaneously, greatly enhanced performance can be obtained when distributing original data among several processing devices. For example if a two dimensional n X n filter is arranged to be executed by several processors, each processor will use some data in common with other processors, and such data need only be transmitted once.

Another use of such a system mey be in the viewing of an original changing image through two or more display engines, each of which applies a different display function to the same data stream.

The basic transfer block through the GBUS is a consecutively addressed sequence of of an arbitrary number of bytes. In practice the practical realisation is between 1 and 64 Megabytes. Such a block of data will be referred to as a line of data.

Although the start address in each selected device may be arbitrary, it is subject to the restriction that each such start address must differ from any other by a multiple of 8.

A complete transfer consists of an arbitrary number of lines (typically from 1 to 4096) each being of the same length but whose line start to line start address difference, or pitch, is the same per device, but may be different between selected devices. This allows rectangular sub-images from a larger rectangular image to be moved in one transfer to a processor or to a window of a display engine.

The GBUS consists of: 1. The main data highway comprising 64 data lines, 8 byte write lines and 5 memory control lines which operate to move data from the source to one or more destinations in a pipelined fashion.

2. Two control lines to set up the memory start addresses for the source and each destination, using the 64 data lines, just before each line transfer is to occur.

Four lines to detect the rate of the slowest addressed device to thereby determine the rate of any particular transfer.

4. Six lines to deal with interrupts which may be required either by the addressed device or the GBUS controller, and b. One reset line.

An auxiliary data highway is also incorporated to write to or read from control registers (not shown) in the devices linked to the GBUS and this auxiliary data highway comprises 16 data lines, 12 address lines and 3 handshake control lines. The auxiliary highway operates independently of, but simultaneously with, the main data highway.

The GBUS controller shown in Figure 3 is made up of the following elements: (I) A parameter store 56 which is the means whereby the master controller or host computer (not shown) instructs the control unit what transfers to perform; (2) An unit 58 by which the next start address for each new line can be computed for each device being accessed; A A ROM or similar memory 60 containing a list of transfer control command words. (This list is the collection of micro programmes by which transfers can be steered through their various phases of operation and included are micro programmes which deal with the refresh ot the dynamic memories and microprogrammes which respond to requests from devices attached to the GBUS to hold up a transfer if a higher priority memory access is required within that device.Where it is desirable to be able to change the list and the menu of functions available, the memory 60 may be in the form of a random access memory into which data is loaded from the master controller or host computer at system initialisation. In this way for example only those transfer commands required may be stored so as to limit the amount of information stored within the memory 60, or selected-transfer function instructions from a library of such instructions may be stored within the memory 60); (4) A command sequence execution unit 62. (The selected control word from the memory 60 is applied to the unit 62 to generate BUS signals depending on the device control bits for durations depending on the timing control bits, and to provide an address to find the next micro command word, which may be conditional upon a test of a particular state of the system.The unit 62 also executes an instruction if the "instruction bit" is set, and allows or not this microstep to be interrupted); (5) An address generator 64, which determines the address ot the next control word to be used in response to the address required by the sequence execution unit 62 and to interrupts from the devices connected to the GBUS, from the host, and from internal timers (not shown), according to a priority system.

An auxiliary highway interface is provided at 66. This is arranged to respond to a given range of addresses accessed by the master controller or host computer. This accesses a corresponding range of control or status registers (not shown) in the devices connected to the GBUS. Each device control element has two auxiliary addresses, one where a base address is set and one where auxiliary data is written to or read from. Using this system, the base address is automatically incremented upon a read or write command to its corresponding data register, and the auto increment range is set over 16 bits which gives efficient access to large look up tables, for example.

As shown in Figure 3, the GBUS Control Unit sits between a host interface 68 and the GBUS 16 and the sections of the GBUS to which the various parts of the control unit are connected are labelled on the right hand side of Figure 3.

Thus the command sequence execution unit 62 is linked to the main highway of the GBUS, address generator 64 receives information from the interrupt lines of the GBUS, whilst the auxiliary interface 66 transmits and receives data from the auxiliary highway previously referred to.

Typical information stored in the parameter store 56 is shown in Figure 4.

Upon command from the host computer or master controller, the sequencer 62 uses the parameter list to set the transfer addresses in the selected devices for the first line to be transferred, triggers the adder unit 58 which works out the start addresses for the next line and operates the memory controls to move the data. After the line has been transferred, the sequencer decrements a counter which holds the number of lines to be transferred.

If the result is not zero then a new line is transferred using updated values in the parameter store 56. If the end has been reached, an interrupt is given to the host or master controller.

Figure 5 shows how the control word is divided into fields ot significance. Thus 10 bits are dedicated to device control signals or instructions. The next 5 bits provide the time period for the first part of the control step, the next 5 bits provide the time period for the second part of a control step, 4 bits are provided for any conditional tests, 5 further bits provide the sequence address or the address if a test succeeds whilst the next bits provide the address if a test fails, 2 more bits provide for interrupt control and the last bit is an interpretation bit, to indicate whether or not the word is an instruction.

The two sheets making up Figure 6 illustrate a complete data processing system incorporating the GBUS and associated hardware previously referred to.

The system is linked to a master controller such as a host computer 70 which includes a hard disc bulk memory device and keyboard 72. Essentially the data processing system (shown as a single item 74) is supplied with data from the host computer along instruction data path 76 and receives the video signal from the work station along a video path 78. A second video data path 80 is connected to the monitor 82 and within the system 74 is provided a video switch (84) by which either the work station video can be transmitted to the monitor 82 or video from processed data, reconstituted into a video signal, can be transmitted to the monitor instead.

The disc storage device 72 includes the digitised data of a raster scanned picture or image, and the data processing system 74 operates to process some or all of the image data from the hard disc store 72. After processing the data may be returned to the disc store 72 to be stored either in addition to, or instead of some or all of the previous data read from the disc. Alternatively data which has been processed may simply be displayed and never stored.

Betore the processing system 74 can operate on image data, the latter must be transmitted and stored in the bulk RAM store 86 within the processing system 74. To this end a data highway is set up by means of instruction signals whereby blocks of data are read from the disc store 72 and loaded into a 2 MBYTE DRAM 88 which forms a buffer memory within a system controller 90 which itself forms part of the overall data processing system 74. The DRAM 88 includes a DMA interface 92 and is connected to the GBUS highway 94 (data and auxiliary), such as has previously been described with reference to the earlier figures. The GBUS is controlled by a micro GBUS controller 96, which receives instruction signals from the host computer 70 and/or obtains information stored in the DRAM 88.

Interpretation of incoming and outgoing data and overall control is achieved by a Transputer 98 also forming part of the system controller.

Since the DRAM 88 is required for storing control information and parameter information for programmable devices attached to the GBUS, only part of the capacity is available for storing incoming data from the disc drive z, but typically in excess of 1 Megabyte will be available and after each Megabyte of data has been stored in the DRAM 88, the GBUS microcrntroller generates an address of the bulk RAM store 86 and downloads the 1 Megabyte of data from DRAM 88 via the GBUS data highway and the DMA interfaces 92 and 100.

As soon as the data transfer is completed, a further Megabyte of data can be downloaded from the store 72 into the DRAM 88 and the sequence is continued until the whole of the data which is to be transferred from the store 72 into the bulk RAM 86, has been transferred.

At this stage processing of the data can begin and again the host computer 70 is used to instruct the system to perform the desired processing. For example the instruction may be given to invert the data stored in the bulk RAM 86 and display the inverted data on the monitor 82.

Initial instructions are sent to the system controller and arrive at Transputer 98. This identifies the instructions and microprograms required for data inversion as stored in the utilities section of the DRAM 88 and transmits the appropriate data information to the Transputers TP2 to TP5 contained within the image engine device 102 which is that part of the data processing system 74 which is to perform the inversion processing.

From system information stored in the DRAM 88, TP1 will have been told that there are 4 transputers (TP2 to TP5) which are available for processing the data stored in the bulk RAM 86. The system controller therefore searches for and/or sets up a sequence of commands which will result in a splitting up of the data downloaded from the bulk RAM Bb, into 4 blocks.

In order to process the data, TP1 issues instructions to the micro controller 96 to generate addresses for bulk RAM 8b and a 2 Megabit DRAM 104, and during the next following synchronous clock pulses, a block of data from the series of addresses in the bulk RAM 86 are transferred at high speed, in parallel format via the DMA interfaces 100 and 106 into the DRAM 104.

Subsequent addresses allow similar transfers of blocks of data from RAM 86 to DRAMS 108, 110 and 112.

Instructional data is simultaneously transmitted to the Transputers TP2, TP3, TP4 and TP5 via the instruction data highway 114 by mean of Transputer 98. The control instructions are read by the Transputers TP2 to TP5 and stored in a buffer memory within the Transputer for future reference. As soon as its associated DRAM is full, such as DRAM 104 in the case of TP2, data is read from the DRAM and processed by the Transputer TP2 and restored in the DRAM 104.

In a similar way but quite independently of one another, Transputers TP3, TP4 and TP5 read data from their respective DRAMS 108, 110 and 112, processing the data and restoring it.

End of processing control signals are returned along the data highway 114 so that the system controller is advised that the data in each of the DRAMS 104 etc., is ready for down loading. This is achieved by setting appropriate addresses on the GBUS 94 so as to access the DRAM 104 via the DMA interface 106. If the processed data is simply to.

be restored in the bulk RAM 86 in place of the earlier data, a second set of addresses is provided relating to the appropriate addresses in the bulk RAM 86 to which the processed data is to be down loaded. Subsequent clock pulses on the GBUS cause high speed return transfer of the data from 104 to 86.

If on the other hand there is a desire to see the processed data, the second set of addresses define addresses within three Image Plane memories denoted by reference numeral 116 and the subsequent clock pulses cause data from the DRAM 104 to be transferred via the DMA interface 106 and DMA interface 118 into the appropriate Image Plane memories of memory assembly 116.

Data from each of the DRAMS 108, 110 and 112 can similarly be downloaded into the Image Plane memories of 116 and where the quantity of data needed to build up the complete image for display is greater than that of the capacity of the DRAMS 104, 108 etc, the process must be repeated two or more times until sufficient data has been processed by TP2 to TP5 and stored in the Image Plane memories of 116, for a complete picture to be available for display on the monitor 82. In practice however the size of the DRAMS 1U4, 108 etc., is selected to be compatible with the quantity of data normally required for display of a picture on the monitor and consequently there will be no need for successive processing to build up the data in the Image Plane memories of unit 116.

Presentation of a picture on the screen of the monitor 82 is achieved under the action of the Image Contol system 120 which controls the Image Plane selector 122 which interprets the data stored in the three Image Plane stores 116 and loads the red, green and blue signals into the appropriate buffer amplifiers 124, 126 and 128.

With the video switch 84 in the appropriate position, video data from the buffers 124, 126 and 128 can be transferred via the monitor video path 130, for display on the monitor 82.

If a graphics display is required then data from the processors can be routed via the DMA 118 and a graphics generator 132 for storage either in a 1 Megabit DRAM 134 or directly into a Graphics Plane memory device 136.

Again under the action of the Image Control system 120, the data stored in the Graphics Plane memory 136 can be downloaded through the red, green and blue signal generators 124 to 128, to provide an appropriate colour video signal for routeing to the monitor 82.

As previously noted, the quantity of data which is actually processed by the image engine 102 in any given period of time is four times the quantity that could be processed by an image engine incorporating only one processor, even though the buffer memory associated with that processor were four times the size of the 2 Megabit DRAM shown associated with each Transputer.

The Image Plane selector 122 may be utilised not only to select the appropriate data from the Image Plane memories to produce the R, G and B signals, but also can be used to select some of the lines and only some of the stored data along each line of each Image Plane memory, so that only a selected region of the overall image is displayed by the monitor 82. This is of particular importance where for example it is required that the monitor screen is to display more than one item, such as a menu of possible image processing functions as well as part of the processed image in another region on the screen. The area which can be displayed on the screen is selectable through controls associated with the host computer 70.

Claims (16)

1. A data processing system which includes a parallel data BUS along which data is to be transmitted between one device and another, inter alia for processing and for storage, wherein in order to achieve improvement in the overall speed of operation: (1) Each device includes a buffer memory with a direct memory access (DMA) interface into and out of which data can be read in parallel format to and from the BUS, and, where the device is to perform processing on the data in the buffer memory, a programmable microprocessor is associated therewith.

(2) One of the devices linked to the BUS via a DMA interface comprises a system controller to which operating commands are sent from a master controller, for the purpose of sending address data and intercepts via the BUS to one or more other devices connected thereto, for sending and receiving data; and (3) In each processing device linked to the BUS, the function control input of the programmable microprocessor is supplied with control signals from the system controller to perform particular functions (such as inversion) on data stored in the buffer memory associated therewith, by reading the data out of the buffer memory, processing data and returning the processed data to the buffer memory.

2. A processing system according to claim 1, wherein the programmable microprocessor is a Transputer.

3. A processing system according to claim 1 or claim 2, wherein a further increase in operating speed is achieved by providing N parallel subsystems in each device, each including its own buffer memory (and if required a processor), and by providing that, when transferring data from a master memory into the device, the system controller sequentially identifies memory addresses in the N buffer memories of the N subsystems so that the block of data removed from the master memory is distributed between the N buffer memories within the device.

4. A processing system according to claim 3, wherein where the device is simply a memory, the N subsystems each comprises a buffer memory, either a single DMA interface being provided for all of the buffer memories or an individual DMA interface being provided for each buffer memory.

5. A processing system according to claim 3 or claim 4, wherein, where processing is required in the device, each subsystem additionally includes a programmable microprocessor such as a Transputer controlled by data from the system controller, for reading, processing and restoring data from its associated buffer memory, and where the system includes two or more such microprocessors (Transputers), these are so linked that instructional data can be pipelined to the Transputers from the master controller N host computer.

6. A processing system according to any of claims 1 to 5, wherein a BUS controller is provided which is supplied with a list of parameters from the master controller, such as a host computer, which define the transfers to be performed.

7. A processing system according to claim 6, wherein the BUS includes 64 parallel data paths, 8 byte write lines and 5 memory control lines, which operate to move data from one device to another in a pipelined manner, 2 control lines to set up the memory start, addresses for the source and each destination device, using the 64 data lines during the quiescent period just before each line transfer; 4 lines to detect the rate of the slowest addressed device, thereto ensure that the rate of addressing does not exceed that limit; 6 lines to deal with interrupts which may be required either by the addresed devices or the BUS controller; and 1 reset line.

8. A processing system according to claim 7, wherein control registers are provided in the devices and an auxiliary data highway is provided comprising 16 data lines, 12 address lines and 3 handshake control lines, to write to or read from the control registers, the auxiliary highway operating independently of and simultaneously with the main 64 line data highway.

9. A processing system according to any of claims 1 to 8, wherein, in operation, the host computer or other master controller, which is controlling the sequence of transfers on the BUS, is interfaced to a system controller and under commands emanating from the system controller, the transputer link pipelines and the BUS microcontroller pass commands and data between image processing devices in order to perform a desired algorithm.

10. A processing system according to claim 7 or any claim appendent thereto, wherein, in operation, the 64 bit wide path is used for the high bandwidth block transfers of data, employing a format suited to the DRAM and VRAM devices of any volumetric image store linked to the BUS, the buffer working memories associated with transputers linked to the BUS and any display generator frame stores.

11. A processing system according to claim 10, wherein devices on the BUS auto increment their addresses internally during the data block transfer.

12. A processing system according to claim 11, wherein the supervisory second path is 28 bits wide and is used for command, status, short data set, and supervisory transfers, and in operation, devices on the path auto increment internal addresses when accepting short data sets.

13. A processing system according to claim 12, wherein the supervisory path can conduct transfers at the same time as and asynchronously with the data transfer path.

14. A processing system according to claim 12 or claim 13, wherein the BUS micro controller is mapped into the memory space of the system controller, address blocks being defined for the various control and data functions to be performed and the BUS micro controller having two parts, one for driving the data transfer BUS, and the other for driving the supervisory BUS.

15. A processing system according to claim 14, wherein, in an address setting mode, addresses for the block transfers are issued on the 64 bit path during the initial phase of a block transfer of data; in the block transfer mode, data blocks of an arbitrary number of bytes are transferred synchronously from a device linked to the BUS to any one or a number of destinations across the 64 bit path, and in the supervisory transfer mode, the 28 bit data path is employed to transfer command and status information concerning data block transfers which are in progress on the 64 bit data path.

16. A data processing system substantially as hereinbefore described with reference to the accompanying drawings.