Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
  • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
  • G06F1/3228—Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode

Definitions

• the present invention relates in general to processor-based systems, and more particularly to an apparatus and method for providing intelligent power management in processor-based systems.
• Power management is implemented in processor-based systems to conserve power or to reduce the power consumption of the system. Power management is typically implemented by powering down one or more circuits in the system upon detection of a period of non-use or inactivity. The period of non-use or inactivity, typically termed the "time-out" period, is generally fixed. The user typically has to enter a setup mode for a particular application and select or enter a time-out value for the application. Selection of the time-out value is also based on the user's perception of system performance versus battery life expectancy, and thus may not be optimized.
• the present invention is an apparatus and method for providing power management apparatus for a circuit in a processor-based system.
• the apparatus comprises a memory to store instruction sequences by which the processor-based system is processed and a processor coupled to the memory.
• the stored instruction sequences cause the processor to: (a) determine a system access time of the circuit; (b) determine if the system access time is less than a first predetermined value, if so, increasing an accessibility period of the circuit, during which the circuit is active.
• Figure 1 illustrates one embodiment of a power state profile of a device.
• Figure 2 is a system block diagram of an exemplary processor system in which the apparatus and method of the present invention is used.
• Figure 3 is an overall functional block diagram illustrating the architecture of an operating system which utilizes the apparatus and method of the present invention.
• FIG 4 is a top-level flow chart of one embodiment of a general process that implements the Intelligent Power Management (IPM) technique of the present invention.
• IPM Intelligent Power Management
• FIG. 5 is a flow chart that illustrates one embodiment of the IPM process of the present invention.
• Figure 6 is a flow chart that illustrates a second embodiment of the IPM process of the present invention.
• Figure 7 is a flow chart that illustrates a third embodiment of the IPM process of the present invention.
• Figure 8 is a flow chart that illustrates a fourth embodiment of the IPM process of the present invention.
• the present invention is an apparatus and method for altering the time period prior to turning off a device based on system-level demands for that device.
• Figure 1 illustrates one embodiment of a power state profile of a device. As shown, the device transitions from an in-use period, to an inactive period, an off period and then back to an in-use period.
• T represents a period of time beginning from the time a device is turned off until it is again accessed;
• T[to] represents an inactivity time-out period prior to turning off the device; this value changes as a result of the intelligent power management scheme of the present invention
• T [delta] represents the total time during which a device is turned off, and occurs after the device inactivity period and prior to the time when the device is accessed by the system;
• T[delta_inc] represents a stored time interval corresponding to each power- managed device, that is used to determine if the device's time-out period T[to] should be increased.
• T[delta_inc] is approximately equal to l/3 ⁇ T[delta] ⁇ ;
• T[delta_dec ⁇ represents a stored time interval corresponding to each power- managed device, that is used to determine if the device's time-out period T[to] should be decreased. In one embodiment, T[delta_dec] is approximately equal to
• T[ito] represents an initial inactivity time-out value
• DIR represents a flag that indicates the current mode of the "time-out" change
• INDEX represents an integer that is used to control the amount of increase or decrease to the time-out value T[to].
• the intelligent power management technique of the present invention determines if the system accesses of a power-managed device are occurring too quickly, too slowly, or if the system accesses are just about right relative to a predetermined time-out inactivity value.
• the time-out inactivity value corresponds to a predetermined period of time during which a power-managed device is inactive. Upon reaching the end of the time-out inactivity period, the power-managed device is turned off.
• T[to] the device time-out inactivity period T[to] is increased. If system accesses are occurring slower than a second predetermined time-out value, T[to] is decreased. If the accesses are occurring within a range that is acceptable relative to the time-out inactivity value, i.e., T[to] occurs between the first and second predetermined value, no changes are implemented. In one embodiment, T[to] may be increased or decreased at a predetermined rate to accelerate or decelerate the increase or decrease of T[to] by a predetermined number.
• T[to] is imposed to ensure that T[to] would not be subject to increasing without limitation.
• K 16.
• K may be any user selected number. Implementation The present embodiment is described in reference to a processor system 10.
• FIG. 2 illustrates an exemplary processor system 10 which implements the processes of the present invention.
• the processor system 10 comprises a CPU 12 and a memory module 14.
• the memory module 14 includes random access memory (RAM) 14a and read-only memory (ROM) 14b.
• the memory module 14 also includes a main memory or a dynamic random access memory (DRAM).
• the CPU 12 and memory module 14 are coupled to a system bus 16.
• the processor system 10 may also include various I/O and peripheral modules (MISC I/O #1, #2, ... #N) which are coupled along an I/O bus 20 that is in turn coupled to the system bus 20 via a bus bridge 22. Examples of the peripheral modules include a console, a printer and a mouse.
• FIG. 3 is an overall functional block diagram illustrating the architecture of a processing system 10 that utilizes the apparatus and method of the present invention.
• the processing system 10 comprises an operating system 30 which supports user applications 40, Basic
• BIOS 50 Input/ Output System
• the user applications 40 include an intelligent power management (IPM) application 42 and client application(s) 44.
• IPM intelligent power management
• the BIOS 50 is a collection of drivers, or software interfaces for hardware devices such as the console (keyboard and display), a generic printer, the auxiliary device (serial port), the computer's clock and the boot disk device.
• BIOS 50 is typically embedded in programmable, read only memory (PROM).
• PROM programmable, read only memory
• An operating system typically makes no use of the BIOS 50 after the operating system has been booted and is running.
• the kernel level drivers in the operating system 30 may interface directly with the system hardware 60.
• the operating system 30 includes an Application Program Interface (API) 70 which interfaces with the IPM Application 42, and a Configuration Manager 74 which allocates resources installed on the operating system 30 based on requests from the IPM Application 42.
• the operating system 30 further includes a class driver 74 which interfaces with the user applications 40 (either directly, as in the case of the client applications 44, or via the API 70 and Configuration Manager 72), and an I/O Manager 76.
• the I/O Manager 76 converts I/O requests (made via the class driver 74) into properly sequenced calls to various driver routines located in the kernel 78.
• the I/O Manager 42 uses the function codes of the request to call one of several dispatch routines in a driver located in the kernel 78.
• the kernel 78 provides hardware-independent functions, called system functions, that are accessed by means of a software interrupt.
• the functions provided by the kernel 78 include file and directory management, memory management, character device input/ output and time and date support, among others.
• the operating system is the Windows NT operating system.
• the operating system 30 includes the Solaris or the AIX operating systems or other operating systems based on demand-paged virtual memory subsystems.
• the present invention provides the IPM Application 42 which monitors the I/O activities of I/O devices such as MISC I/O #1, ..., MISC I/O #N ( Figure 2) through the use of one or more Filter Device drivers 80, located within the kernel 74. Based on information provided by the filter device drivers 80, the IPM
• the IPM Application 42 identifies the most suitable power state for power-managed devices installed on the system 10 and/ or for the system 10 using the knowledge-based technique of the present invention.
• the power state of the system hardware 60 can then be efficiently controlled and managed.
• the IPM Application 42 controls the power state of system hardware through the use of the
• the physical device drivers 82 can either directly control system hardware 60 or interface with the system hardware 60 through the BIOS interface 52 and Physical Memory and I/O circuit 54 of BIOS 50.
• Drivers 78 comprise source code written in the C language. It is understood that other assembly languages may be utilized in implementing the functions of the IPM Application 42 and Filter Device drivers 78.
• the BIOS data and addresses are typically located in physical memory 50 (typically in RAM 14a; see Figure 1) and are accessed by the physical device drivers 82.
• Figure 4 is a top-level flow chart of one embodiment of a general process that implements the IPM technique of the present invention.
• the system process is configured to run at a predetermined interval, e.g., every 10 seconds. This interval was established as a trade-off between the granularity of monitoring and controlling power-managed devices and the minimization of the IPM process's consumption of power.
• the predetermined interval may be increased or decreased depending on system requirements and user preference.
• the system process 100 of the present invention which implements the IPM process (generally represented by process blocks 106-108) proceeds from a start state to process block 102, where the IPM environment is initialized. In particular, various circuits such as timers or variables required for the use of the system process 100 are initialized.
• the process 100 then advances to process block 104, where I/O accesses from the Filter Device Drivers 80 (see Figure 3) are read.
• the I/O accesses are then applied by the process 100 to identify and control the power states of one or more power-managed device(s), as shown in process block 106.
• the process 100 subsequently outputs one or more power state requests for controlling the power-managed device(s) and/ or the system 10, as shown in process block 108.
• such requests are serviced by the Configuration Manager 72 ( Figure 3).
• the process 100 then proceeds to decision block 110, where it determines if the system is still active. If not, the process 100 is terminated (process block 112). Otherwise, the IPM process 100 is suspended for a predetermined period of time. In one embodiment, the IPM process 100 is suspended for 10 seconds. In particular, a timer is set to a predetermined period of time. The process 100 determines if the predetermined period has lapsed, as shown in decision block 118. If not, the process 100 continues to monitor the timer event. Otherwise, it proceeds to process block 120, where the operating system places the IPM process into the run state and returns to process block 104.
• FIG. 5 is a flow chart that illustrates one embodiment of the IPM process of the present invention.
• the IPM process of Figure 5 may be implemented for device management of I/O devices such as hard disk drives, CD ROMs, and Modems.
• the IPM process 200 begins from a start state and proceeds to process block 202, where it determines if T, the system access time of a managed device, is less than a first predetermined value, T(Inc). If so, the process 200 proceeds to decision block 204, where it determines if the flag, DIR FLAG, which indicates the current mode of the time-out inactivity change, has been set to indicate that T[to] should be increased.
• T the system access time of a managed device
• process block 206 the DIR FLAG is set to INC, indicating that T[to], the time-out inactivity period for the managed device, should be increased.
• INDEX the rate of change of T[to] is set to 1. The process 200 then terminates.
• the process 200 then returns to the main process 100 flow.
• the process 200 proceeds to process block 214, where it determines if the system access time is greater than a second predetermined period, T(Dec). If so, the process proceeds to decision block 216, where it determines if the DIR FLAG has been set to indicate that T[to] should be decreased. If so, the process proceeds to process block 218, where it sets the DIR FLAG to indicate that T[to] should be decreased. In one embodiment, DIRFLAG is set to a value of "2", indicating that T[to] should be decreased. The process 200 then returns to the main process 100 flow.
• the process 200 determines that T is not greater than a second predetermined value, T(Dec)
• the process 200 proceeds to decision block 228, where it queries if T is within an acceptable range. In one embodiment, the process queries if T(Inc) ⁇ T ⁇ T(Dec). If so, the process proceeds to process block 230, where it determines if the DIR FLAG has been set to indicate that T[to] should not be changed. If not, the process 200 proceeds to process block 232, where it sets the DIR FLAG to indicate that T[to] should not be changed. In one embodiment, DIRFLAG is set to a value of "0", indicating that T[to] should not be changed. The process 200 then returns to the main process 100 flow.
• the process 200 determines that the DIR FLAG has been set to indicate that T[to ⁇ should be decreased, it returns to the main process 100 flow. In addition, if at decision block 228, the process determines that T is not within the predetermined acceptable range, i.e., T is not greater than T(Inc) and not less than T(Dec), the process returns to the main process 100 flow.
• FIG. 6 is a flow chart that illustrates a second embodiment of the IPM process of the present invention.
• the IPM process 300 may be implemented for the management of display devices such as video circuits.
• IPM process 300 begins from a start state and proceeds to decision block 302, where the process 300 determines if T[to], the time out inactivity period of a device is greater than T[inactive_time] a predetermined inactivity period.
• T[inactive_time] is the inactivity period of an I/O device such as a keyboard or a pointing device such as a mouse.
• I/O device such as a keyboard or a pointing device such as a mouse.
• T[inactive_time] is 10 seconds. If so, the process 300 proceeds to process block 304, where it turns off the device. The process 300 then proceeds to process bloc, 306, where it starts a device interaction timer, which runs for a predetermined period of time, such as 15 seconds. The process 300 then queries if the managed device was accessed during the device interaction timer period, as shown in decision block 310.
• the process 300 proceeds to process block 312, where it activates the managed device.
• the process 300 then returns to the main process 100 flow. If, at decision block 310, the process determines that the device was not accessed during the device interaction timer period, the process 300 advances to process block 316, where the interaction timer is reset. The process then returns to decision block 302. If at decision block 302, the process 300 determines that T[to] is not greater than T[inactive_time], the process 300 returns to the main process 100 flow.
• Figure 7 is a flow chart that illustrates a third embodiment of the IPM process of the present invention.
• ID profile identification
• the process 400 determines that the profile ID of the managed device is neither word processing nor presentation services, it proceeds to decision block 408, where it determines if the profile ID of the device indicates that it is involved in providing spreadsheet services. If so, the process 400 sets the device clock to max, as shown in process block 41, which is a predetermined percentage of the full operational speed of the managed device. In one embodiment, "max" is 100% of the full operational speed of the managed device. The process 400 then returns to the main process 100 flow.
• FIG. 8 is a flow chart that illustrates a fourth embodiment of the IPM process of the present invention.
• the IPM process 500 may be implemented for the management of I/O devices such as floppy disks. Beginning from a start state, the process 500 proceeds to process block 502, where it determines if T[to] is greater than a predetermined amount, such as 4 seconds. If so, the device is turned off. The process 500 then returns to the main process 100 flow. If T[to] is less than the predetermined amount, the process 500 directly returns to the main process 100 flow.
• the present invention provides an apparatus and method for providing power management for a number of applications in a processor-based system, which facilitates conservation of power in the system, while optimizing system performance.

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• 1998
  • 1998-11-04 US US09/185,674 patent/US6347377B2/en not_active Expired - Lifetime
• 1999
  • 1999-11-04 JP JP2000580071A patent/JP2002529807A/ja active Pending
  • 1999-11-04 WO PCT/US1999/026187 patent/WO2000026756A1/en not_active Ceased
  • 1999-11-04 TW TW088119223A patent/TW525052B/zh not_active IP Right Cessation
• 2001
  • 2001-07-27 US US09/916,996 patent/US6523123B2/en not_active Expired - Lifetime
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