WO2000025353A1

WO2000025353A1 - Substrate comprising multilayered group iii-nitride semiconductor buffer

Info

Publication number: WO2000025353A1
Application number: PCT/US1999/025334
Authority: WO
Inventors: Motoaki Iwaya; Tetsuya Takeuchi; Hiroshi Amano; Isamu Akasaki
Original assignee: Agilent Technologies, Inc.
Priority date: 1998-10-28
Filing date: 1999-10-28
Publication date: 2000-05-04
Also published as: JP4298023B2; JP2000133601A

Abstract

A substrate (200) for group III-nitride devices comprises an initial substrate (102) and a buffer structure (204) of a stack of layer pairs (206, 207, 208, 210) located on the substrate. The material of the substrate is different from the materials of the layer pairs. Each layer pair includes a buffer layer of low-temperature-deposited nitride semiconductor material (212, 216, 220) preferably GaN or AlGan and a single-crystal layer of single-crystal GaN (214, 218, 222) grown directly on the buffer layer. At least one of the layer pairs (210) is structured to exhibit in-plane strain that is no more tensile that the in-plane strain in the single-crystal layer of another of the layer pairs on which the at least one of the layers is located.

Description

SUBSTRATE COMPRISING MULTILAYERED GROUP III-NITRIDE

SEMICONDUCTOR BUFFER

Field of the Invention

The invention relates to a semiconductor deposition substrate and a method for making a semiconductor deposition substrate, and more particularly relates to a multi-layer Group Ill- nitride semiconductor deposition substrate having a growth layer with a low defect density that makes the deposition substrate useful as the substrate for making Group Ill-nitride semiconductor devices. The invention also relates to a method for making such a deposition substrate.

Background of the Invention

Short-wavelength lasers fabricated from Group Ill-nitride semiconductor materials, whose general formula is A\_xGa _x._y\n_YN, where Al is aluminum, Ga is gallium, In is indium, N is nitrogen, and x and / are compositional ratios, have been widely reported. The substrates on which such lasers are fabricated must have a low defect density, but the size of currently- available wafers of Group Ill-nitride semiconductor materials is too small for such wafers to be used in mass-production. Consequently, deposition substrates are widely used as substrates in the manufacture of Group Ill-nitride semiconductor devices. Such deposition substrates are made by depositing one or more layers of a Group Ill-nitride semiconductor material on a substrate of a different material, such as sapphire, SiC, spinel, MgO, GaAs, or silicon. The top-most layer of the deposition substrate, which is the layer on or in which semiconductor devices would be fabricated, will be called the growth layer of the deposition substrate throughout this disclosure.

However, deposition substrates suffer from problems caused by the considerable lattice mismatch and difference in coefficients of thermal expansion between the material of the substrate and the Group Ill-nitride semiconductor material deposited on the substrate. For instance, sapphire and the Group Ill-nitride semiconductor materials have a lattice mismatch between 1 1 % and 23 %, and a coefficient of thermal expansion difference of approximately 2 x 10^"6 K^'1. Consequently, the layer of a Group Ill-nitride semiconductor that constitutes the growth layer of the deposition substrate has poor crystal quality, poor electrical characteristics and poor optical properties. These shortcomings of conventional deposition substrates impair the quality of semiconductor devices fabricated on or in the growth layer of such deposition substrates.

Some attempts have been made to solve the problem of the poor crystal quality of the growth layer of deposition substrates. One of the most effective solutions is the multi-layer deposition substrate. A multi-layer deposition substrate is composed of a substrate on which is formed a stack of layer pairs. Each layer pair is composed of a buffer layer of a low- temperature-deposited Group Ill-nitride semiconductor material and a single-crystal layer of a single-crystal Group Ill-nitride semiconductor material grown on the buffer layer. The material of the substrate, e.g., sapphire, differs from the materials of the layer pairs. Low-temperature- deposited Group Ill-nitride semiconductor material is Group Ill-nitride semiconductor material deposited at a temperature below that at which single-crystal growth occurs.

In published Japanese Patent Application No. H 4-297023, Nakamura stated that the quality of a layer of single-crystal gallium nitride-based semiconductor material grown on a buffer layer of AI^Ga^N (0 < x ≤ 1 ) that was deposited on a substrate at a temperature below that at which single-crystal growth occurs is higher than when such layer of single- crystal gallium nitride-based semiconductor material is grown on a buffer layer of low- temperature-deposited AIN.

Nakamura went on to say that, when a layer of GaN is grown on a substrate, the advantages of using a buffer layer of GaN, rather than of AIN, include: "(1 ) Because of the lower melting point of GaN, single crystal formation occurs more readily when the temperature rises. Therefore, the benefits of the buffer layer can be expected even if the buffer layer is made thicker.

"(2) Because the buffer layer is GaN, an epitaxial growth layer of GaN grown over the buffer layer has an increased crystal quality since the material being grown is the same as the material on which it is grown."

In published Japanese Patent Application No. H 9-1 99759, Akasaki et al. disclosed a technique in which a deposition substrate is made by forming a stack of layer pairs on a substrate of a different material. Each layer pair is composed of a buffer layer of low- temperature-deposited material grown at a temperature below that at which single crystals grow, and a single-crystal layer grown on the buffer layer at a temperature above that at which single crystals grow. A Group Ill-nitride semiconductor material is then grown on the deposition substrate at a temperature above that at which single crystals grow.

Akasaki et al. disclosed a working example in which the deposition substrate is made by forming a stack of three layer pairs on a sapphire substrate. Each layer pair is composed of a 50 nm-thick buffer layer of low-temperature-deposited AIN grown at a temperature of 400°C and a single-crystal layer of single-crystal GaN grown at a temperature of 1 1 50°C . The thickness of the lower two single-crystal layers was 300 nm and that of the top-most single- crystal layer was 1 .5 μm. During formation of the stack, the top-most single-crystal layer was etched with KOH and a scanning electron micrograph was taken. The etch pit density was measured from the photomicrograph and was found to be 4 x 10⁷ cm^"2 after one layer pair was grown, and was 8 x 10⁵ cm^"2 after three layer pairs were grown.

In published International Application no. WO 99/25030, which is assigned to the assignee of this disclosure, Amano et al. disclosed an improvement to the above-mentioned method disclosed by Akasaki et al. in which the buffer layer grown at a temperature below that at which single crystals grow was subject to crystallization at an elevated temperature before the single-crystal layer was grown.

However, notwithstanding the advances described above, the need remains for an improvement in the crystal quality of the growth layer of deposition substrates. In particular, the need remains to ascertain any limit on the number of layer pairs in multi-layer substrates, to better control the quality of the growth layer of multi-layer substrates, and to lower the cost of multi-layer substrates.

Moreover, in the deposition substrates disclosed by Akasaki and Amano, the material of the buffer layers is low-temperature-deposited AIN, which has a relatively low electrical conductivity. The low-conductivity buffer layers reduce electrical conduction between the single-crystal layers and, hence, the overall electrical conductivity of the deposition substrate. It would be advantageous to be able to use a material with a higher electrical conductivity as the material of the buffer layers to increase the electrical conductivity of the deposition substrate.

Improvements such as those described above would enable multi-layer deposition substrates to be used in a broader range of applications.

What is needed, therefore, is to improve the crystal quality of the growth layer of a multilayer deposition substrate that includes a Group Ill-nitride semiconductor. What is also needed is a multi-layer deposition substrate having a higher electrical conductivity than one that employs buffer layers of low-temperature-deposited AIN.

Finally, what is also needed is to provide more effective control over the quality of multilayer deposition substrates, to provide a method for fabricating a deposition substrate with a high-quality growth layer, and to solve or ameliorate the problems of the prior art.

Summary of the Invention

The invention provides a multi-layer nitride semiconductor deposition substrate that comprises a substrate and a stack of layer pairs located on the substrate. The material of the substrate is different from the materials of the layer pairs. Each layer pair includes a buffer layer of low-temperature-deposited nitride semiconductor material and a single-crystal layer of single-crystal GaN grown directly on the buffer layer. At least one of the layer pairs is structured to exhibit in-plane strain that is no more tensile than the in-plane strain in the single- crystal layer of another of the layer pairs on which the at least one of the layers is located. The buffer layer of the at least one layer pair may consist essentially of AIGaN with an

AIN molar fraction of between 5 % and 100% . In this case, the buffer layer of the others of the layer pairs may consist essentially of GaN. However, to prevent cracks in the growth layer, the number of contiguous layer pairs having a buffer layer consisting essentially of GaN may not be more than six.

Alternatively, the buffer layer of a majority of the layer pairs may consist essentially of AIGaN with an AIN molar fraction of between 1 0% and 90% .

The invention enables a deposition substrate to be made with a greater number of layer pairs, and, hence, with a lower crystal defect density, than prior art deposition substrate by overcoming the limit on the number of layer pairs imposed by using low-temperature-deposited GaN as the material of the buffer layers. In one embodiment, GaN is used as the material of the buffer layer of most of the layer pairs, but the stack includes a layer pair having a buffer layer of low-temperature-deposited AIN or AIGaN which prevents the accumulation of tensile strain in the growth layer. Alternatively, low-temperature-deposited AIGaN with an AIN molar fraction of between 10% and 90% may be used as the material of the buffer layer of a majority of the layer pairs.

The invention also provides a method of making a multi-layer nitride semiconductor deposition substrate. In the method, a substrate of a first material is provided. A stack of layer pairs is formed on the substrate. Each of the layer pairs is formed by processes that include depositing a buffer layer of low-temperature-deposited nitride semiconductor at a temperature below that at which single-crystal growth occurs, and growing a single-crystal layer of single-crystal GaN directly on the buffer layer at a temperature above that at which single-crystal growth occurs. In forming the stack of layer pairs, at least one of the layer pairs is formed have in-plane strain in its single-crystal layer that is no more tensile than the in-plane strain of the single-crystal layer of another of the layer pairs on which the at least one of the layers is formed.

During formation of the stack, the strain in the single-crystal layer can be determined at room temperature or at an elevated temperature by measuring the lattice constant.

Brief Description of the Drawings Figure 1 is a schematic diagram of a first embodiment of a multi-layer deposition substrate according to the invention in which the material of the buffer layer of a majority of the layer pairs is low-temperature-deposited AIGaN.

Figure 2 is a schematic diagram of a second embodiment of a multi-layer deposition substrate according to the invention in which the material of the buffer layer of one of the layer pairs is low-temperature-deposited AIN or AIGaN and that of the buffer layer of the remaining layer pairs is low-temperature deposited GaN.

Figure 3 is a schematic diagram of a first experimental multi-layer deposition substrate fabricated for test purposes in which all of the layer pairs are GaN/GaN layer pairs.

Figure 4 is a graph in which the lattice constant of the growth layer is plotted against the number of layer pairs constituting the stack formed on the substrate in the experimental deposition substrates shown in Figures 3 and 6. Figure 5 is a graph in which the dislocation density of the growth layer is plotted against the number of layer pairs constituting the stack formed on the substrate in the experimental deposition substrates shown in Figures 3 and 6.

Figure 6 is a schematic diagram of second experimental multi-layer deposition substrate fabricated for test purposes in which all of the layer pairs are AIN/GaN layer pairs.

Detailed Description of the Invention

Figure 1 shows a first embodiment of a multi-layer deposition substrate 100 according to the invention. The deposition substrate 1 00 is composed of the substrate 102 and the stack 104 of layer pairs formed on the substrate. In the example shown, the stack is composed of the three layer pairs 1 06, 107 and 1 1 0. The exemplary layer pair 1 1 0 is composed of the buffer layer 1 1 2 of low-temperature- deposited AIGaN with the single-crystal layer 1 1 4 of single-crystal GaN grown on the buffer layer. Since the layer pair 1 10 is the top-most layer pair in the stack 104, the single-crystal layer 1 14 constitutes the growth layer of the deposition substrate 100. The surface 1 1 9 of the growth layer constitutes the growth surface of the deposition substrate. When the deposition substrate 100 is used for manufacturing semiconductor devices, such semiconductor devices would be fabricated on the growth surface, in the growth layer, or both on the growth surface and in the growth layer, of the deposition substrate. The structure and materials of the layer pairs 106 and 107 are similar to those of the layer pair 1 10, and will therefore not be described. In the example shown in Figure 1 , the stack 104 is composed of three layer pairs.

However, the stack may be composed of more or fewer layer pairs: increasing the number of layer pairs reduces the dislocation density in the growth layer, i.e., the single-crystal layer 1 14, while decreasing the number of layer pairs increases the dislocation density in the growth layer. Using low-temperature-deposited AIGaN as the material of the buffer layer of each of the layer pairs 106, 107 and 1 10 provides each buffer layer with a higher electrical conductivity than using the low-temperature-deposited AIN taught by Akasaki et al. in the above-mentioned published Japanese Patent Application No. H 9-1 99759. However, a trade-off is involved in selecting the molar fraction of AIN in the AIGaN material. As will be described in more detail below, it is preferable that the growth layer 1 14 be subject to in-plane strain in a range that extends from tensile strain less than a threshold strain to compressive strain. Tensile strain greater than the threshold strain causes the top-most single-crystal layer to crack. Such cracks negate the usefulness of this layer as a growth layer.

A buffer layer composed of AIGaN with a high molar fraction of AIN imposes compressive in-plane strain on the single-crystal layer grown on it, but has a low electrical conductivity. Decreasing the molar fraction of the AIN in the AIGaN increases the electrical conductivity of the buffer layer, but makes the in-plane strain in the single-crystal layer less compressive. Decreasing the AIN molar fraction further changes the in-plane strain in the single-crystal layer to tensile strain. Moreover, when the single-crystal layers of the layer pairs are each subject to in-plane tensile strain, the tensile strain in the growth layer increases as the number of layer pairs in the stack 104 increases. The tensile strain in the growth layer can accumulate to a level that exceeds the threshold at which the tensile strain causes the growth layer to crack. The accumulation of tensile strain imposes a maximum on the number of layer pairs in the stack, and, hence, imposes a minimum on the dislocation density that can be achieved in the growth layer 1 14.

Accordingly, to prevent in-plane tensile strain from accumulating in the stack, the AIN molar fraction in the material of the buffer layers should be no less than 5% and should preferably be no less than 10%. On the other hand, in applications in which the deposition substrate is required to have a high electrical conductivity, the AIN molar fraction in the material of the buffer layers should be not exceed 50%. When the conductivity of the deposition substrate is particularly important, the optimum AIN molar fraction is approximately 10%.

The method according to the invention for making the deposition substrate 100 will be described below.

Figure 2 shows a second embodiment 200 of a multi-layer deposition substrate according to the invention. Elements of the embodiment 200 that correspond to elements of the embodiment 100 shown in Figure 1 are indicated using the same reference numerals and will not be described further. The deposition substrate 200 is composed of the substrate 102 and the stack 204 of layer pairs located on the substrate. In the example shown, the stack is composed of the four layer pairs 206, 207, 208 and 210.

The layer pair 208 is composed of the buffer layer 216 of low-temperature-deposited GaN with the single-crystal layer 218 of single-crystal GaN grown on the buffer layer. The structure and materials of the layer pairs 206 and 207 are similar to those of the layer pair 208, and will therefore not be described. A layer pair, such as the layer pairs 206-208, in which the material of the single-crystal layer is single-crystal GaN and that of the buffer layer low-temperature GaN will be called a GaN/GaN layer pair. The layer pair 210 differs from the layer pairs 206, 207 and 208 in that the material of the buffer layer 21 2 is low-temperature-deposited AIN or AIGaN. The single-crystal layer 214 of single-crystal GaN is grown on the buffer layer 212. A layer pair, such as the layer pair 210, in which the material of the single-crystal layer is single-crystal GaN and that of the buffer layer low-temperature AIGaN or AIN will be called a AIN/GaN layer pair. Since the layer pair 210 is the top-most layer pair in the stack 204, the single-crystal layer 214 constitutes the growth layer of the deposition substrate 200. The surface 219 of the growth layer constitutes the growth surface of the deposition substrate 200. When the deposition substrate 200 is used for manufacturing semiconductor devices, such semiconductor devices would be fabricated on the growth surface, in the growth layer, or both on the growth surface and in the growth layer, of the deposition substrate.

In the example shown in Figure 2, the stack 204 is composed of four layer pairs, with the AIN/GaN layer pair 210 as the top-most layer pair. The number of GaN/GaN layer pairs in the stack may differ from that shown. A smaller number of GaN/GaN layer pairs increases the dislocation density in the growth layer i.e., the single-crystal layer 214. A larger number of GaN/GaN layer pairs reduces the dislocation density in the growth layer. However, the number of contiguous GaN/GaN layer pairs is limited, as will be described next.

Using low-temperature-deposited GaN as the material of the buffer layer of all but one of the layer pairs in the deposition substrate 200 provides the deposition substrate 200 with a higher conductivity than that of the deposition substrate 100, in which the material of the buffer layer of all the layer pairs is low-temperature-deposited AIGaN, and a substantially higher conductivity than that of a deposition substrate in which the material of the buffer layer of all the layer pairs is low-temperature-deposited AIN. However, the inventors have discovered, as will be described below, that the accumulation of in-plane tensile strain in the single-crystal layers of the GaN/GaN layer pairs, such as the layer pairs 206-208, limits the contiguous number of GaN/GaN layer pairs to about six. Increasing the number of contiguous GaN/GaN layer pairs beyond six incurs the risk that the accumulated in-plane tensile strain will cause cracks to form in the single-crystal layer of the top-most of the contiguous GaN/GaN layer pairs.

However, regardless of the in-plane tensile strain that accumulates in the single-crystal layers of the contiguous GaN/GaN layer pairs, such as the layer pairs 206-208, using low- temperature-deposited AIN or AIGaN as the material of the buffer layer 21 2 of the AIN/GaN layer pair 210 results in the in-plane strain in the single-crystal layer 214 of the layer pair 210 being substantially less tensile than that in the single-crystal layer 218 of the layer pair 208 on which the layer pair 210 is grown. When the material of the buffer layer 212 is AIN, the in-plane strain in the single-crystal layer 214 is compressive strain. When the material of the buffer layer 212 is AIGaN with an AIN molar fraction of less than about 95 %, the in-plane strain in the single-crystal layer 214 may be compressive strain or may be a lower level of tensile strain than that in the single-crystal layer 21 8 of the layer pair 208 on which the layer pair 210 is grown. Whether the in-plane strain in the single-crystal layer 214 is compressive strain or merely a lower level of tensile strain depends inversely on the AIN molar fraction of the low-temperature deposited AIGaN of the buffer layer 212. Thus, using AIN or AIGaN as the material of the buffer layer 21 2 of the AIN/GaN layer pair 21 0 effects a transfer in the in-plane strain towards compressive strain between the single- crystal layer 21 8 of the layer pair 208 on which the layer pair 21 0 is grown and the single- crystal layer 214 of the layer pair 210. The transfer of in-plane strain towards compressive strain allows additional GaN/GaN layer pairs to be grown on the single-crystal layer 214 of the AIN/GaN layer pair 21 0. As a result, embodiments of the deposition substrate 200 can be fabricated in which the total number of GaN/GaN layer pairs in the stack 204 exceeds the number of GaN/GaN layer pairs in which cracks would occur if the GaN/GaN layer pairs were contiguous. Such embodiments will have a growth surface with a lower crystal defect density than embodiments with stacks composed of fewer layer pairs.

The method according to the invention for making the deposition substrate 200 will be described below.

In the embodiments 100 and 200 described above, the conductivity of the deposition substrates is preferably increased by doping the materials of the single-crystal layers, e.g., 1 14, 214 and the buffer layers, e.g., 1 12, 21 2 and 216 using suitable dopants. Fabricating the deposition substrates is easier if the buffer layers and the single-crystal layers are doped with same dopant. Silicon and germanium, for example, can be used as n-type dopants for doping the layer pairs, while magnesium, zinc, and beryllium, for example, can be used as p- type dopants. Silicon and magnesium are particularly effective in reducing resistivity and enable technologically-mature manufacturing methods to be used. A high concentration of silicon reduces the specific resistivity of n-type layers, but degrades the crystal quality of the layers.

The silicon dopant concentration may be in the range from about 5 x 1 0¹⁷ cm ³ to 1 x 10¹⁹ cm^"3. In one example, the silicon dopant concentration was 5 x 1 0¹⁸ cm^"3. As with silicon, a high concentration of magnesium reduces the specific resistivity of p-type layers, but degrades the crystal quality of the layers. The magnesium dopant concentration should be in the range from about 1 x 10¹⁸ cm^"3 to 5 x 1 0²⁰ cm^"3. In one example, the magnesium dopant concentration was 1 x 10²⁰ cm^"3. The trade-off between crystal quality and conductivity means that care must be taken when selecting the doping concentrations. Although not exemplified above, the buffer layers may need to be doped at a higher level than the single-crystal layers to provide the buffer layers with an acceptably-high conductivity.

In the layer pairs described above, each buffer layer, e.g., the buffer layers 1 1 2, 21 2 and

21 6 of low-temperature-deposited Group Ill-nitride semiconductor material should have a thickness equal to or greater than that at which the buffer layer will provide a stable buffering effect, but less than that at which the buffer layer and the single-crystal layer grown on the buffer layer cease to have good crystal quality. In practice, therefore, each buffer layer should have a thickness in the range from 2 nm to 1 00 nm, with the range from 10 nm to 50 nm being preferred. The deposition temperature of the buffer layers should be below the temperature at which single-crystal growth occurs. In practice, a deposition temperature in the range from 300 °C to 700 °C is used.

In the layer pairs described above, each single-crystal layer, e.g., the single-crystal layers 1 1 4 and 214, preferably has a thickness in the range from 0.1 μm and 3 μm. Thinner single- crystal layers have a shorter growth time, but single-crystal layers that are too thin have poor crystal quality. The deposition temperature of the single-crystal layers should be above the temperature at which single-crystal growth occurs. The preferred growth temperature of the single-crystal layers is in the range from 1 000 °C to 1 200 °C.

The material of the substrate 102 may be sapphire. Alternative materials for the substrate include SiC, silicon, spinel (MgAI₂0₄) and AIGaN.

The method according to the invention that may be used to fabricate the multi-layer deposition substrate 1 00 according to the invention will now be described. This method is also the basis of the method according to the invention for making the deposition substrate 200.

A two-inch sapphire substrate 1 02 with a (0001 ) C plane was etched by dipping it for 5 minutes into each of hydrofluoric acid and aqua regia, and was then rinsed for 5 minutes in pure water. Organic washing was then performed with methanol and acetone for 5 minutes each, after which the substrate was again rinsed in pure water. This processing was performed at room temperature.

The substrate 102 was then transferred to the reactor of a metal-organic vapor phase epitaxy (MOVPE) apparatus. The atmosphere of the reactor was thoroughly replaced with nitrogen to remove oxygen and water. Hydrogen was then introduced into the reactor and the sapphire substrate was subject to hot cleaning for 10 minutes at 1 100°C.

The stack 104 of layer pairs was then formed on the substrate 102, with the layer pair 1 06, composed of the buffer layer 1 20 and the single-crystal layer 1 22, being formed first. To form the layer pair 106, the temperature of the substrate 102 was reduced to 500°C, and trimethylgallium (TMGa), trimethylaluminum (TMAI) and ammonia were supplied to the reactor. The volumetric ratio between the flows of TMGa and TMAI was set to generate the material of the buffer layer 1 20 with the desired AIN molar fraction. The substrate temperature was below that at which the TMGa, TMAI and ammonia would form single-crystal AIGaN on the surface of the substrate. A dopant, such as silane, biscyclopentadienylmagnesium (Cp2Mg) or some other suitable dopant, was additionally supplied to the reactor to dope the buffer layer to increase its conductivity.

The supplies of TMGa, TMAI and the dopant were continued for approximately three minutes to grow the buffer layer 1 20 of low-temperature-deposited AIGaN on the substrate 102 to a thickness of 30 nm, and were halted when the buffer layer reached its design thickness.

The temperature of the substrate 102 was then raised to 1050°C over approximately three minutes. Approximately five minutes later, TMGa and a dopant were supplied to the reactor together with the ammonia. The substrate temperature was above that at which TMGa and ammonia form single-crystal GaN on the surface of the buffer layer 1 20. The supplies of TMGa, ammonia and the dopant were continued to grow the single-crystal layer 122 of single- crystal GaN to a thickness of 1 μm at a growth rate of 2.5 μm per hour. The supplies of TMGa and the dopant were halted after the single-crystal layer 1 22 reached its design thickness, but the supply of ammonia was continued.

Fabrication of the stack 104 was completed by growing the layer pairs 107 and 1 10 on the single-crystal layer of the just-deposited layer pair by repeating the above-described process. Each layer pair was composed of a buffer layer of low-temperature-deposited AIGaN and a single-crystal layer of single-crystal GaN grown on the buffer layer.

After the required number of layer pairs had been grown, the multi-layer deposition substrate 100 was cooled to room temperature and taken out of the reactor.

A method similar to that just described was used to fabricate the multi-layer deposition substrate 200. However, during deposition of the buffer layers of the layer pairs 206-208, no TMAI was supplied to the reactor, i.e., TMAI was supplied to the reactor only during deposition of the buffer layer 212 of the layer pair 210. Moreover, in fabricating embodiments in which the material of the buffer layer 212 is low-temperature-deposited AIN, no TMGa is supplied to the reactor during deposition of this layer.

In the methods described above, the various layers were deposited or grown using metal- organic vapor phase epitaxy (MOVPE) exclusively. Other epitaxial growth techniques may be used, but when maturity of technology, ease of operation, and cost are factored in, MOVPE is preferred.

During fabrication of the deposition substrates 100 and 200 according to the invention, the in-plane strain in the top-most single-crystal layer can be determined by measuring of the lattice constant of this layer at a room temperature or an elevated temperature. Such measurements can be performed as the layer pairs are grown on the stacks 104 and 204. By including measurements of the lattice constant in sample tests performed during mass production, the stability of the manufacturing process to be easily and quickly monitored. This ability helps reduce manufacturing costs. In the deposition substrates 100 and 200, the buffer layers, e.g., the buffer layers 1 1 2,

21 2 and 216, are fabricated from low-temperature-deposited nitride semiconductor material that is deposited at a temperature below that at which single-crystal growth occurs. Consequently, after it is deposited, the material of each buffer layer is a mixture of amorphous and polycrystalline material. Raising temperature of the substrate and the buffer layer to a temperature above that at which single-crystal growth occurs to grow the single-crystal layer, e.g., the single-crystal layers 1 14, 214 and 218, on the buffer layer anneals the low- temperature deposited material of the buffer layer, and causes single-crystal regions to develop in the buffer layer. As a result, the single-crystal layer grows epitaxially on the buffer layer. However, regions of residual polycrystalline and amorphous material distinguish the buffer layers of low-temperature-deposited nitride semiconductor material from the layers of single- crystalline GaN between which each buffer layer is sandwiched in the finished multi-layer deposition substrates according to the invention and in the finished semiconductor devices incorporating such multi-layer deposition substrates.

Next, three experiments that, together with the inventors' analysis of the above- mentioned teachings of Amano et al., form the basis of the invention disclosed herein will be described.

The experiments to be described below involve fabricating and testing test samples of various examples of multi-layer Group Ill-nitride deposition substrates.

In the first experiment, test samples of an experimental deposition substrate in which all the layer pairs were GaN/GaN layer pairs were fabricated and tested for comparison purposes, i.e., the material of the buffer layer of all the layer pairs was low-temperature-deposited GaN.

An example of such a deposition substrate is shown in Figure 3. Test samples with stacks composed of 2, 3, 6, 9 and 1 2 layer pairs were fabricated and tested.

Figure 3 shows the deposition substrate 1 0 that includes the sapphire substrate 1 2 on which is located the stack 1 1 of GaN/GaN layer pairs. In the test sample shown, the stack is composed of two layer pairs, namely, the layer pair 1 3 and the layer pair 1 5. The layer pair 13 located on the substrate 1 2 is composed of the buffer layer 1 5 of low-temperature- deposited GaN and the single-crystal layer 1 6 of single-crystal GaN located on the buffer layer 1 5. The layer pair 1 5 located on the single-crystal layer 1 6 of the layer pair 1 3 is composed of the buffer layer 1 8 of low-temperature-deposited GaN, and the single-crystal layer 20 of GaN located on the buffer layer 1 8.

The top-most single-crystal layer 20 of the deposition substrate 10 constitutes the growth layer of the deposition substrate, and the surface 1 9 of the growth layer constitutes the growth surface of the deposition substrate. The growth layer has a lattice constant, to be discussed in more detail below, which is the lattice constant measured along the c axis of the growth surface.

In the other test samples of the deposition substrate 1 0, the stack is composed of more than two layer pairs. In such test samples, additional layer pairs are interposed between the layer pair 1 3 and the layer pair 1 5.

The test samples were fabricated using a method similar to that just described, except that during deposition of the GaN buffer layers, e.g., the buffer layers 14 and 1 8, no TMAI was supplied to the reactor. After fabrication, measurements of the growth layer 20 of the test samples of the deposition substrate 10 were performed. The measurements included taking photomicrographs of the growth surface using a differential interferometric microscope, and using X-ray diffraction to measure the lattice constant of the growth layer. The photomicrographs showed that the growth layer 20 was crack-free in the test samples of the deposition substrate 10 in which the stack 1 1 was composed of 2, 3 and 6 layer pairs. However, the photomicrographs of the growth layer of the test samples of the deposition substrate in which the stack was composed of 9 and 1 2 layer pairs showed a large number of cracks.

Figure 4 is a graph in which the lattice constant of the growth layer 20 is plotted along the -axis and the number of layer pairs is plotted along the x-axis. The lattice constant measurements taken on the test samples of the deposition substrate 1 0 are plotted as curve 1 . A horizontal broken line indicates the bulk lattice constant of GaN, which is about 0.5185 nm. The growth layers whose lattice constants lie below the broken line, and are therefore less than the bulk lattice constant, are subject to in-plane tensile strain, whereas the growth layers whose lattice constants lie above the broken line, and are therefore greater than the bulk lattice constant, are subject to in-plane compressive strain.

Figure 4 shows that, in the deposition substrate 10, when the stack 1 1 is composed of one layer pair, the lattice constant of the growth layer 20 is greater than the bulk lattice constant of GaN. The growth layer of such a deposition substrate is therefore subject to compressive strain. However, when the stack is composed of two or more layer pairs, the lattice constant of the growth layer is less than the bulk lattice constant of GaN, and the growth layer is subject to tensile strain. Moreover, the lattice constant of the growth layer decreases, and the tensile strain in the growth layer therefore increases, as the number of layer pairs increases up to six. Figure 4 shows that the growth layer is subject to in-plane tensile strain when the deposition substrate is composed of between two and nine layer pairs. When the deposition substrate is composed of nine or more layer pairs, cracks form in the growth layer. The cracks relieve the tensile strain in the growth layer, and the lattice constant of the growth layer becomes equal to the bulk lattice constant.

An increase in the lattice constant along the c-axis relative to the bulk lattice constant results in a decrease in the in-plane lattice constant relative to the bulk lattice constant. The strain applied to a layer can be tensile strain or compressive strain depending on the relative magnitudes of the lattice constant of the layer and the bulk lattice constant of the material of the layer. A change in the lattice constant of the layer relative to the bulk lattice constant can change a given strain from compressive strain to tensile strain, or vice versa.

The tests also show that in-plane tensile strain greater than a threshold level applied to a layer can cause the layer to crack. The threshold level of tensile strain at which cracking occurs can be estimated by determining a corresponding critical lattice constant. A thin slice was cut from the growth layer 20, and threading dislocations in this slice were counted by transmission electron microscopy. Additionally, the crystal dislocation density, which is the density of the threading dislocations, was measured.

Figure 5 is a graph in which the crystal dislocation density in the growth layer 20 is plotted along the -axis and the number of layer pairs in the stack 1 1 is plotted along the x- axis. The dislocation density measurements taken on the deposition substrate 1 0 are plotted as curve 1 . It can be seen that the crystal dislocation density steadily decreases as the number of layer pairs increases. It should be noted that the crystal dislocation density referred to here is different from the etch pit density measured and reported by Akasaki et al. in published Japanese Patent Application No. H 9-1 99759.

In a second experiment, test samples of an experimental multi-layer deposition substrate in which all the layer pairs were AIN/GaN layer pairs were fabricated and tested. In these test samples, the material of the buffer layer of all the layer pairs was low-temperature-deposited AIN. An example of such a deposition substrate 30 is shown in Figure 6. The test samples with stacks composed of 2, 3, 6, 9 and 1 2 layer pairs were fabricated and tested.

Figure 6 shows the experimental deposition substrate 30. Elements of the experimental multi-layer deposition substrate 30 that correspond to elements of the experimental multi-layer deposition substrate 10 are indicated using the same reference numerals and will not be described further. In the deposition substrate 30, the stack 31 of layer pairs is located on the sapphire substrate 1 2. In the example shown, the stack is composed of two layer pairs, namely, the layer pair 33 and the layer pair 35. The layer pair 1 3 located on the sapphire substrate is composed of the buffer layer 34 of low-temperature-deposited AIN, and the single- crystal layer 36 of single-crystal GaN located on the buffer layer. The layer pair 35 located on the single-crystal layer 36 of the layer pair 1 3 is composed of the buffer layer 38 of low- temperature-deposited AIN, and the single-crystal layer 40 of GaN located on the buffer layer 38. The top-most single-crystal layer 40 of the deposition substrate 30 constitutes the growth layer of the deposition substrate, and the surface 39 of the growth layer constitutes the growth surface of the deposition substrate 30. The experimental deposition substrate 30 was fabricated using a process similar to that described above for making the deposition substrate 100, except that during deposition of the buffer layers, e.g., the buffer layers 34 and 38, no trimethylgallium was supplied to the reactor. After fabrication, the test samples were tested as described above.

Photomicrographs showed that the growth layers 40 of the all of the test samples of the experimental deposition substrate 30 were crack-free, regardless of the number of layer pairs in the stack 31 . The lattice constant measurements taken as described above on the growth layers of the test samples of the deposition substrate 30 are plotted as curve 2 in Figure 4, described above. The graph shows that the lattice constants of the growth layers of the test samples of the deposition substrate 30 were approximately 0.51 88 nm, and were substantially independent of the number of layer pairs in the stack. However, the lattice constant of the growth layer was significantly greater than the bulk lattice constant of GaN of approximately 0.51 85 nm. Consequently, the growth layer of the deposition substrate 30 is subject to a substantial in-plane compressive strain. The crystal dislocation density measurements taken on the growth layers of the test samples of the deposition substrate 30 are plotted as curve 2 in Figure 5, described above. The crystal dislocation density decreases as the number of layer pairs increases.

In a third experiment, a test sample of the multi-layer deposition substrate 200 according to the invention, and shown in Figure 2, was fabricated and was tested as described above. The test sample was fabricated using the method described above.

Tests similar to those performed on the test samples of the deposition substrate 10 were carried out on the test sample of the deposition substrate 200. Photomicrographs showed that the growth layer 214 of the deposition substrate 200 was crack-free. The lattice constant of the growth layer 214 measured 0.51 88 nm. This shows that the layer pair 210, composed of the buffer layer 21 2 of low-temperature-deposited AIN and the single-crystal layer 21 and located on top of a stack of three GaN layer pairs, returns the lattice constant of the growth layer 214 to 0.5188 nm. This is the same as that measured in the second experiment in which the buffer layers of all the layer pairs were layers of low-temperature-deposited AIN. Since the lattice constant of the growth layer 214 is greater than the bulk lattice constant of GaN, the growth layer 21 4 is subject to in-plane compressive strain. Measurements were also taken of the crystal dislocation density of the single-crystal layer 21 8 of the layer pair 208 on which the layer pair 210 was grown and showed that the growth layer 214 had a crystal dislocation density lower than that of the single-crystal layer 21 8. As noted above, several additional GaN/GaN layer pairs can be grown sequentially on the growth layer 214 of the multi-layer deposition substrate 200 using the above-described process to fabricate a multi-layer deposition substrate having a crack-free growth layer that has a lower crystal dislocation density than the growth layer 214 of the multi-layer deposition substrate 200. The first experiment shows that a transfer of strain towards tensile strain in the single- crystal layer of successive GaN/GaN layer pairs increases the in-plane strain in the growth layer up to a level at which the tensile strain causes cracks to form in the growth layer. This imposes an upper limit on the number of contiguous GaN/GaN layer pairs in usable examples of the all-GaN deposition substrate 10. Thus, the accumulation of in-plane tensile strain in the single-crystal layers limits the benefits that can be obtained by growing a layer of single-crystal GaN on a buffer layer of low-temperature-deposited GaN.

The results of the first experiment also show that the number of GaN/GaN layer pairs in an all-GaN deposition substrate can be increased beyond four without cracks forming in the growth layer provided that the limit on the number of layer pairs is not exceeded. This point was not clear in the examples given in prior art. Also, the results of the first and second experiments indicate that Nakamura's statement does not apply in the case of a single GaN/GaN layer pair located on a substrate. Figure 5 shows that, in this case, the dislocation density of a single-crystal layer of single-crystal GaN is greater when the single-crystal layer is grown on a buffer layer of low-temperature-deposited GaN than when the single-crystal layer is grown on a buffer layer of low-temperature-deposited AIN.

Furthermore, the second experiment shows that, contrary to Nakamura's teaching, the crystal dislocation density can be reduced by increasing the number of layer pairs when the semiconductor material of the buffer layers differs from that of the single-crystal layers, as when, for example, the semiconductor material of the buffer layers is AIN and that of the single-crystal layers is GaN. Figure 5 shows that the average proportional reduction in the crystal dislocation density as the number of layer pairs is increased beyond two is about the same with a buffer layer of low-temperature-deposited GaN as with a buffer layer of low- temperature-deposited AIN. However, as noted above, when the conductivity of the deposition substrate is important, the preferred material of the buffer layers is low-temperature-deposited GaN because the conductivity of the layer pairs is greater when the material of the buffer layers GaN than when the material of the buffer layers is AIN.

The first experiment shows that a multi-layer deposition substrate in which the material of the buffer layer of all the layer pairs is GaN suffers from the above-described limit on the number of layer pairs. This is because the initial lattice mismatch between the substrate 1 2 and the buffer layer 1 4 propagates up the stack, increasing the tensile strain in the growth layer as the number of layer pairs in the stack increases, until the accumulated tensile strain causes cracks to form in the growth layer to relieve the strain. The second experiment shows that the problem just described can be solved by making the material of the buffer layer of all the layer pairs low-temperature-deposited AIN. When the material of the buffer layer is AIN, the in-plane strain of the single-crystal layer grown on the buffer layer is compressive strain. However, such deposition substrates suffer from low conductivity. Accordingly, to increase the conductivity in the first embodiment 100 of the multi-layer deposition substrate according to the invention, the inventors used AIGaN instead of AIN as the material of the buffer layers.

The third experiment shows that the above-described problem can be solved by forming the stack 204 to include the AIN/GaN layer pair 210 in which the material of the buffer layer 21 2 is low-temperature-deposited AIN. The in-plane strain in the single-crystal layer 214 of the layer pair 210 tends towards compressive strain regardless of the in-plane strain in the single-crystal layer 21 8 on which the layer pair 210 is grown.

Since the single-crystal layers 1 14 and 214 have lattice constants that are larger than, or only slightly smaller than, the bulk lattice constant of GaN, the lattice constants of these layers are small enough to allow additional GaN/GaN layer pairs, in which the material of both the buffer layer and the single-crystal layer is GaN, to be grown on such single-crystal layers without the tensile strain in the growth layer increasing as the number of layer pairs is increased. This enables the number of layer pairs to be increased without incurring the risk of cracks in the growth layer. Since the crystal dislocation density progressively decreases as the number of layer pairs is increased, increasing the number of layer pairs beyond the limit established by the first experiment enables a growth layer with a very low crystal dislocation density to be obtained. The inventors' experiments show that the crystal dislocation density in the growth layer of a multi-layer deposition substrate decreases as the number of layer pairs increases. However, in multi-layer deposition substrates in which the stack is composed exclusively of GaN/GaN layer pairs, increasing the number of layer pairs increases the in-plane tensile strain in the growth layer. Beyond a certain number of layer pairs, the tensile strain reaches a level at which it causes the growth layer to crack. The need to avoid cracks in the growth layer limits the number of layer pairs in such deposition substrates. As a result, the crystal dislocation density in the growth layer may be greater than would be desired.

The invention overcomes this problem by providing a practical way of fabricating a multilayer deposition substrate having a greater number of layer pairs than is possible in conventional deposition substrates in which the growth layer is subject to cracks. Consequently, a deposition substrate according to the invention can be fabricated to have a growth layer with a lower dislocation density than that of prior art deposition substrates.

The invention enables a multi-layer deposition substrate to be fabricated with a high electrical conductivity and with a growth layer having a low density of lattice defects. This results in a deposition substrate having an improved structure and characteristics that make the deposition substrate suitable for use in manufacturing not only optical elements such as laser diodes, but also many other semiconductor devices fabricated using Group Ill-nitride semiconductors. A non-comprehensive list of examples of such semiconductor devices includes AIGaN/GaN modulation-doped field effect transistors, ridge waveguide laser diodes, pn junction-type photo detectors (PDs), AIN/GaN semiconductor multilayer reflector films, and AIN/GaN sub-band transition devices.

Although this disclosure describes illustrative embodiments of the invention in detail, it is to be understood that the invention is not limited to the precise embodiments described, and that various modifications may be practiced within the scope of the invention defined by the appended claims.

Claims

ClaimsWe claim:

1 . A multi-layer nitride semiconductor deposition substrate, comprising: a substrate of a first material; and a stack of layer pairs located on the substrate, each of the layer pairs including: a buffer layer of a low-temperature-deposited nitride semiconductor, and a single-crystal layer of single-crystal GaN grown directly on the buffer layer; at least one of the layer pairs being structured have in-plane strain in its single-crystal layer that is no more tensile than the in-plane strain of the single-crystal layer of another of the layer pairs on which the at least one of the layers is located.

2. The multi-layer nitride semiconductor deposition substrate of claim 1 , in which the stack includes three layer pairs.

3. The multi-layer nitride semiconductor deposition substrate of claim 1 , in which the stack includes four layer pairs.

4. The multi-layer nitride semiconductor deposition substrate of any one of claims 1 to 3, in which the buffer layer of the at least one of the layer pairs consists essentially of AIGaN with an AIN molar fraction of between 5% and 100% .

5. The multi-layer nitride semiconductor deposition substrate of claim 4, in which the buffer layer of the others of the layer pairs consists essentially of GaN.

6. The multi-layer nitride semiconductor deposition substrate of claim 5, in which the number of contiguous layer pairs having a buffer layer consisting essentially of GaN is no more than six.

7. The multi-layer nitride semiconductor deposition substrate of any one of claims 1 -3, in which the buffer layer of a majority of the layer pairs consists essentially of AIGaN with an AIN molar fraction of between 10% and 90% .

8. The multi-layer nitride semiconductor deposition substrate of claim 4 or 7, in which the AIN molar fraction is between 10% and 50% .

9. The multi-layer nitride semiconductor deposition substrate of claim 8, in which the AIN molar fraction is approximately 10% .

10. A method of making a multi-layer nitride semiconductor deposition substrate, the method comprising: providing a substrate of a first material; forming a stack of layer pairs on the substrate, each of the layer pairs being formed by processes including: depositing a buffer layer of low-temperature-deposited nitride semiconductor at a temperature below that at which single-crystal growth occurs, and growing a single-crystal layer of single-crystal GaN directly on the buffer layer; in which, in forming the stack of layer pairs, at least one of the layer pairs is formed have in-plane strain in its single-crystal layer that is no more tensile than the in-plane strain of the single-crystal layer of another of the layer pairs on which the at least one of the layers is formed.

1 1 . The method of claim 10, in which, in forming the stack, a stack including three layer pairs is formed.

12. The method of claim 10, in which, in forming the stack, a stack including four layer pairs is formed.

13. The method of any one of claims 10 to 1 2, in which, in depositing the buffer layer, a layer of a semiconductor material consisting essentially of AIGaN with an AIN molar fraction of between 5% and 100% is deposited as the buffer layer of the at least one of the layer pairs.

14. The method of claim 13, in which, in depositing the buffer layer, a layer of a semiconductor material consisting essentially of GaN is deposited as the buffer layer of each of the others of the layer pairs.

1 5. The method of claim 14, in which, in forming the stack, a stack is formed in which the number of contiguous layer pairs having a buffer layer consisting essentially of GaN is no more than six.

16. The method of claim 13, in which, in depositing the buffer layer, a layer of semiconductor material consisting essentially of AIGaN with an AIN molar fraction of between 10% and 90% is deposited as the buffer layer of each of a majority of the layer pairs.

1 7. The method of claim 13 or 1 6, in which, in depositing the buffer layer, the AIN molar fraction is between 10% and 50% .

18. The method of claim 17, in which, in depositing the buffer layer, the AIN molar fraction is approximately 10%.

1 9. The method of any one of claims 10-1 8, additionally comprising measuring a lattice constant of the single-crystal layer at one of (a) room temperature and (b) an elevated temperature to determine the in-plane strain in the single-crystal layer.