JP5731785B2 - Multilayer semiconductor and method of manufacturing multilayer semiconductor - Google Patents

Description

  The present invention relates to a stacked semiconductor and a method for manufacturing the stacked semiconductor, and more particularly to a stacked structure of a semiconductor film that alleviates lattice mismatch between a growth substrate and a semiconductor film for crystal growth.

Conventional technology

  GaN-based nitride semiconductors are applied to light-emitting devices such as LEDs and laser diodes that emit light in the wavelength range from visible light to ultraviolet light, and their functions are being advanced. In the manufacture of GaN-based nitride semiconductor devices, sapphire substrates are mainly used as crystal growth substrates. However, since the lattice constants of sapphire substrates and GaN-based nitride semiconductors are greatly different, if a GaN-based nitride semiconductor film is directly formed on a sapphire substrate, the defect density increases and a high-quality semiconductor film cannot be obtained. In order to alleviate lattice distortion caused by such lattice mismatch, a buffer layer exhibiting an amorphous state or a polycrystalline state is inserted between the sapphire substrate and the GaN-based nitride semiconductor layer (device layer). .

  In Patent Document 1 and Patent Document 2, a first buffer layer composed of a multilayer film formed on a growth substrate at a temperature lower than a single crystal growth temperature, and a first buffer layer formed at a single crystal growth temperature. A semiconductor element is disclosed in which a layer in contact therewith has a second buffer layer made of a multilayer film made of a nitride containing no Ga and In.

Patent Document 3 _discloses that Al _x1 Ga _y1 In _1-x1-y1 N (0 ≦ X1 ≦ 1, 0 ≦ y1 ≦ 1, 0 ≦ x1) formed on a growth substrate at a temperature lower than the single crystal growth temperature. + y1 ≦ 1) and a buffer layer made of Al _x2 Ga _y2 In _1-x2-y2 N (0 ≦ X2 ≦ 1, 0 ≦ y2 ≦ 1, 0 ≦ x2 + y2 ≦ 1) , X1 = x2, y1 = y2), a group III nitride semiconductor in which three or more layers are alternately stacked is disclosed.

Japanese Patent No. 3505405 Japanese Patent No. 3976723 Japanese Patent No. 3712770

  The following two points are cited as technical problems in a semiconductor device having a buffer layer. First, even if a buffer layer is inserted between the growth substrate and the device layer, it is difficult to completely prevent lattice distortion and threading dislocations, and further improvement in crystallinity is required.

  Second, if it is attempted to obtain conductivity in the buffer layer, the crystallinity of the device formed on the buffer layer is significantly deteriorated. Generally, when forming a nitride semiconductor film having n-type conductivity, crystal growth is performed while doping silicon (Si). However, when the nitride semiconductor is doped with Si, the atomic arrangement is disturbed and the crystallinity is deteriorated. In general, the buffer layer is formed at a relatively low temperature and exhibits an amorphous state or a polycrystalline state. However, when exposed to a high temperature, the outermost surface becomes a single crystal-like amorphous state. When the buffer layer is doped with Si, the crystallinity of the single crystal-like surface layer is deteriorated, which adversely affects the crystallinity of the device layer formed thereon. The deterioration of crystallinity due to Si doping becomes more prominent as the doping concentration increases.

  Conventionally, in order to avoid the deterioration of crystallinity due to Si doping, the buffer layer is not provided with conductivity, or the crystallinity is sacrificed. For example, in the case of manufacturing a so-called thin film LED manufactured by removing the growth substrate, if the buffer layer does not have conductivity, the buffer layer is polished to obtain an n-type semiconductor layer (device Layer) needs to be exposed. However, adding a polishing step causes a decrease in yield and an increase in cost. On the other hand, in a semiconductor device using a growth substrate having conductivity such as a SiC substrate, it is necessary to make the buffer layer conductive at the expense of crystallinity in order to secure a current path.

  Each of the above-mentioned patent documents relates to a technique for reducing threading dislocations and lattice distortion and obtaining a semiconductor film with good crystallinity, but dealing with adverse effects when the buffer layer is made conductive. Does not mention any.

  The present invention has been made in view of such a point, and a laminated semiconductor capable of ensuring good crystallinity in a device layer formed on a buffer layer while providing conductivity to the buffer layer, and its manufacture It aims to provide a method.

The method for producing a laminated semiconductor according to the present invention is a method for producing a laminated semiconductor including a GaN-based nitride semiconductor film, wherein the first buffer is formed on a growth substrate made of a material different from the GaN-based nitride semiconductor film. Forming an intermediate layer in which layers and second buffer layers are alternately and repeatedly stacked three or more times, and growing a GaN-based nitride semiconductor film on the intermediate layer to form a device layer. The first buffer layer is formed by growing an In _x Ga _1-x N (0 <x ≦ 1) film while doping silicon at a temperature lower than a single crystal growth temperature, buffer layer, while doping the silicon single crystal growth temperature is formed by repeatedly alternately growing two kinds of GaN based nitride semiconductor films having different compositions from each other, the second buffer layer, said device layer A strain reducing layer made of _{In x Ga 1-x N (} 0 <x ≦ 1) having an intermediate lattice constant of the GaN-based nitride semiconductor layer lattice constant and the lattice constant of the growth substrate constituting, GaN layer And the first buffer layer is doped with silicon at a higher concentration than the second buffer layer. In the step of forming the intermediate layer, the first buffer layer is formed on the growth substrate. In the step of sequentially forming the first buffer layer and the second buffer layer in this order three or more times and forming the device layer, the device layer is the second buffer layer. The intermediate layer is formed at a higher concentration than the second buffer layer by continuously exposing the first buffer layer and the second buffer layer to the single crystal growth temperature. Silicon dough Is characterized in that is the first from the buffer layer of the silicon toward the second buffer layer atoms are diffused with, it has a substantially constant conductivity across the intermediate layer.

The laminated semiconductor of the present invention is a laminated semiconductor including a GaN-based nitride semiconductor film,
The growth substrate made of a different material from the GaN-based nitride semiconductor film and the growth substrate are provided on the growth substrate, and the first buffer layer and the second buffer layer are alternately and repeatedly stacked three or more times. An intermediate layer to be formed; and a device layer made of a GaN-based nitride semiconductor provided on the intermediate layer, wherein the first buffer layer is formed at a growth temperature lower than a single crystal growth temperature. In addition , the second buffer layer is made of silicon-doped In _x Ga _1-x N (0 <x ≦ 1) , and the second buffer layer is formed at a single crystal growth temperature and is silicon-doped two types of GaN having different compositions from each other The second buffer layer is formed between the lattice constant of the GaN-based nitride semiconductor film constituting the device layer and the lattice constant of the growth substrate. Lattice constant A strain reducing layer made of _{In x Ga 1-x N (} 0 <x ≦ 1) which is formed by repeatedly alternately laminating GaN layer, the first buffer layer, from the second buffer layer The growth substrate is adjacent to the first buffer layer, the device layer is formed adjacent to the second buffer layer, and the intermediate layer is the first buffer layer. The silicon atoms diffuse from the buffer layer toward the second buffer layer, and the difference in silicon concentration between the first buffer layer and the second buffer layer is reduced. The entire layer is characterized by conductivity .

  According to the laminated semiconductor and the manufacturing method thereof of the present invention, it is possible to obtain good crystallinity in the device layer formed on the buffer layer while making the buffer layer conductive.

It is sectional drawing which shows the structure of the laminated semiconductor which is an Example of this invention. It is sectional drawing which shows the manufacturing method of the laminated semiconductor which is an Example of this invention. It is sectional drawing which shows the manufacturing method of the laminated semiconductor which is an Example of this invention. It is sectional drawing which shows the manufacturing method of the laminated semiconductor which is an Example of this invention. It is a figure which shows the density | concentration profile of Si in the 1st and 2nd buffer layer which is an Example of this invention.

  Embodiments of the present invention will be described below with reference to the drawings. In the following drawings, substantially the same or equivalent components and parts are denoted by the same reference numerals.

  FIG. 1 is a cross-sectional view showing a configuration of a laminated semiconductor 1 according to an embodiment of the present invention. The laminated semiconductor 1 includes three first buffer layers 21 and two second buffer layers 22 made of GaN-based nitride semiconductor alternately between the growth substrate 10 and the device layer 30 made of GaN-based nitride semiconductor. It is constructed by stacking.

  The growth substrate 10 is a substrate for crystal growth of a GaN-based nitride semiconductor film, for example, a C-plane sapphire substrate made of a material different from that of a GaN-based nitride semiconductor. The difference in lattice constant between sapphire and GaN is as large as 16%. When the device layer is grown directly on the sapphire substrate, many defects such as threading dislocations are absorbed to absorb the lattice constant mismatch between the substrate and GaN. Resulting in poor crystallinity. For this reason, in this embodiment, the intermediate layer 20 in which the first buffer layer 21 and the second buffer 22 are alternately stacked is inserted between the growth substrate 10 and the device layer 30, thereby causing lattice mismatch. Generation of lattice distortion and threading dislocation is suppressed.

A first buffer layer 21 having a thickness of about 30 nm is formed on the growth substrate 10. The first buffer layer is an amorphous layer (amorphous layer) or a polycrystalline layer represented by, for example, In _x Ga _1-x N (0 ≦ x ≦ 1) made of a GaN-based nitride semiconductor. The first buffer layer 21 exhibits an amorphous state or a polycrystalline state by being formed at a growth temperature lower than the single crystal growth temperature. Note that the single crystal growth temperature refers to a temperature in a range where a substantially single crystal semiconductor film is formed. The substantially single crystal state includes one in which the entire semiconductor film is in a single crystal state, or one in which a part of the semiconductor film is in an amorphous state or a polycrystalline state, but most of the portion is in a single crystal state. The first buffer layer 21 is formed by crystal growth while doping Si at a relatively high concentration (for example, 5 × 10 ¹⁹ atoms / cm ³ ), and has conductivity.

A second buffer layer 22 is formed on the first buffer layer 21. The second buffer layer is a multilayer in which a strain relaxation layer 22a made of In _x Ga _1-x N (0 <x ≦ 1) and a GaN layer 22b made of GaN and having a thickness of about 5 nm are repeatedly stacked. It has a structure. In this embodiment, the strain relaxation layers 22a and the GaN layers 22b are alternately stacked in this order four times. That is, the second buffer layer 22 is composed of eight layers. The relaxation layer 22a is made of a GaN-based nitride semiconductor having a composition different from that of the GaN layer 22b and having a lattice constant intermediate between the lattice constant of the GaN-based nitride semiconductor constituting the device layer 30 and the lattice constant of the growth substrate. Can be configured. By laminating such strain relaxation layers 22a alternately with the GaN layers 22b, lattice strain caused by lattice mismatch between the growth substrate 10 and the device layer 30 is relaxed, and the crystallinity of the device layer 30 is reduced. Can be improved.

  Note that the lowermost layer of the second buffer layer 22 may be either the strain relaxation layer 22a or the GaN layer 22b. When the composition of the lowermost layer of the device layer 30 adjacent to the second buffer layer 22 is GaN, the uppermost layer of the second buffer layer 22 is preferably the GaN layer 22b. This is because a high-quality semiconductor film with few defects in the device layer 30 can be obtained by matching the compositions of the layers adjacent to each other in the second buffer layer 22 and the device layer 30.

The strain relaxation layer 22a and the GaN layer 22b constituting the second buffer layer 22 are both formed at a single crystal growth temperature, thereby exhibiting a single crystal state. Each of the strain relaxation layer 22a and the GaN layer 22b is formed by crystal growth while doping Si at a relatively low concentration (for example, 1 × 10 ¹⁶ atoms / cm ³ ), and has conductivity.

  The first buffer layer 21 and the second buffer layer 22 are alternately and repeatedly stacked, whereby the intermediate layer 20 is configured. The intermediate layer 20 is formed, for example, by alternately stacking the first buffer layer 21 and the second buffer layer 22 three times each.

  The device layer 30 is formed on the second buffer layer 22 located in the uppermost layer exhibiting a single crystal state. When the stacked semiconductor 1 is, for example, a semiconductor light emitting device, the device layer 30 includes an n-type semiconductor layer, an active layer, and a p-type semiconductor layer made of a GaN-based nitride semiconductor. To illustrate a more detailed configuration, an n-type contact layer made of GaN having a thickness of about 4 μm is formed on the second buffer layer 22. An active layer is formed on the n-type contact layer. The active layer may have a multiple quantum well structure in which InGaN well layers / GaN barrier layers are alternately and repeatedly stacked. A p-type cladding made of AlGaN having a thickness of about 40 nm is formed on the active layer, and a p-type contact layer having a thickness of about 150 nm is formed on the p-type cladding layer.

  A method for manufacturing the laminated semiconductor 1 having the above-described structure will be described below. In the following, a case where the stacked semiconductor 1 constitutes a semiconductor light emitting device will be described as an example.

  2 to 4 are cross-sectional views for each process step in the manufacturing process of the laminated semiconductor 1. First, the growth substrate 10 is prepared. In this example, a C-plane sapphire substrate on which a GaN-based nitride semiconductor layer can be formed by metal organic chemical vapor deposition (MOCVD) was used as a growth substrate. The growth substrate 10 was put into an MOCVD apparatus and heated for about 10 minutes in a hydrogen atmosphere at about 1000 ° C. (thermal cleaning).

(First buffer layer forming step)
The substrate temperature (growth temperature) is about 500 ° C., which is lower than the single crystal growth temperature (low growth temperature), and trimethylgallium (TMG), ammonia (NH ₃ ), and silane (SiH ₄ ) as a dopant are supplied. A first buffer layer 21 made of GaN containing Si with a concentration of 5 × 10 ¹⁹ atoms / cm ³ and having a thickness of about 30 nm was formed. The first buffer layer 21 is formed at the above growth temperature, thereby exhibiting an amorphous state or a polycrystalline state. The growth temperature can be set to a temperature at which an amorphous film can be formed, that is, in the range of 350 to 800 ° C. The Si concentration is set so as to obtain a target conductivity in the first and second buffer layers, and is set to a range of, for example, 1 × 10 ¹⁹ atoms / cm ³ or more and 1 × 10 ²¹ atoms / cm ³ or less. be able to. The thickness of the first buffer layer 21 can be set, for example, in the range of 20 to 40 nm (FIG. 2A).

(Second buffer layer forming step)
The substrate temperature (growth temperature) is set to a single crystal growth temperature (high growth temperature) 1000 ° C., and trimethylgallium (TMG), trimethylindium (TMI), ammonia (NH ₃ ), and silane (SiH ₄ ) as a dopant are used. Then, a strain relaxation layer 22 a having a thickness of about 5 nm and made of InGaN containing Si at a concentration of 1 × 10 ¹⁶ atoms / cm ³ was formed on the first buffer layer 21. Subsequently, trimethyl gallium (TMG), ammonia (NH ₃ ), and silane (SiH ₄ ) as a dopant are supplied, and the strain relaxation layer 22a contains Si having a concentration of 1 × 10 ¹⁶ atoms / cm ³ with a thickness of about 5 nm. A GaN layer 22b was formed. By repeating the above process four times alternately, the second buffer layer 22 composed of eight layers in which the strain relaxation layers 22a and the GaN layers 22b are alternately stacked was formed. The strain relaxation layer 22a and the GaN layer 22b are both formed in the above-described growth temperature, thereby exhibiting a single crystal state. Si doping was performed so that the Si concentration in the second buffer layer 22 was lower than the Si concentration in the first buffer layer 21.

The growth temperature of the second buffer layer 22 can be set to a temperature at which a single crystal semiconductor film can be formed, that is, a range of 9000 to 1200 ° C. The Si concentration is set to be lower than the Si concentration in the first buffer layer and to obtain a target conductivity in the first and second buffer layers, for example, 1 × 10 ¹⁵ atoms / cm ³ or more and 1 × It can be set in a range of 10 ¹⁸ atoms / cm ³ or less. The thickness of the strain relaxation layer 22a and the GaN layer 22b can be set in a range of 4 to 10 nm, for example. The lowermost layer of the second buffer 22 may be either the strain relaxation layer 22a or the GaN layer 22b made of InGaN, but the uppermost layer is preferably the GaN layer 22b (FIG. 2B).

(Lamination process of the first buffer layer and the second buffer layer)
The formation process of the first buffer layer 21 and the formation process of the second buffer layer were repeated alternately. As a result, the intermediate layer 20 formed by alternately laminating the first buffer layer 21 and the second buffer layer 22 on the growth substrate 10 was formed. Note that the number of first and second buffer layers may be four or more. In the step of laminating the first buffer layer 21 and the second buffer layer 22, the laminated layers are continuously exposed to high temperatures. Thereby, Si atoms diffuse from the first buffer layer 21 doped with Si at a relatively high concentration toward the second buffer layer 22 doped with Si at a relatively low concentration, and the first buffer layer 21 The difference in Si concentration with the second buffer layer 22 is reduced, and the entire intermediate layer 20 composed of the first and second buffer layers has a substantially constant conductivity (FIG. 2C). .

FIG. 5 shows Si concentration profiles in the first and second buffer layers. The broken line in the figure shows the Si concentration profile immediately after the deposition of each layer. Finally, a Si concentration of 1 × 10 ¹⁹ atoms / cm ³ or more was secured in each layer, and sufficient conductivity could be obtained.

(Device layer formation process)
A device layer 30 composed of an n-type contact layer 31, an active layer 32, a p-type cladding layer 33, and a p-type contact layer 34 was formed on the surface of the second buffer layer 22 located at the uppermost layer.

Trimethyl gallium (TMG), ammonia (NH ₃ ), and silane (SiH ₄ ) were supplied at a substrate temperature (growth temperature) of 1000 ° C. to form an n-type contact layer 31 made of GaN having a thickness of about 4 μm.

A multiple quantum well structure made of InGaN / GaN was applied to the active layer 32. The InGaN well layer / GaN barrier layer was used as one cycle, and five cycles were grown. Trimethylgallium (TMG), trimethylindium (TMI) and ammonia (NH ₃ ) are supplied at a substrate temperature of about 700 ° C. to form an InGaN well layer having a thickness of about 2.2 nm, followed by trimethylgallium (TMG) and ammonia (NH ₃ ) was supplied to form a GaN barrier layer having a thickness of about 15 nm. The active layer 32 was formed by repeating this process for five cycles.

Next, the substrate temperature is raised to 870 ° C., and trimethylgallium (TMG), trimethylaluminum (TMA), ammonia (NH ₃ ), CP2Mg (bis-cyclopentadienyl Mg) is supplied, and p-type made of AlGaN having a thickness of about 40 nm. A clad 33 was formed. Subsequently, trimethylgallium (TMG), ammonia (NH ₃ ), and CP 2 Mg were supplied to form a p-type contact layer 34 made of GaN and having a thickness of about 150 nm (FIG. 3A).

(Metal support forming process)
The support 40 was formed on the p-type contact layer 34 provided on the outermost surface of the device layer 30. In this embodiment, the support 40 is made of a Cu plating film from the viewpoints of thermal conductivity (heat dissipation), electrical conductivity, and manufacturability (yield).

  First, Pt / Ag / Ti / Pt / Au was sequentially deposited on the p-type contact layer 34 by an electron beam evaporation method or the like to form a metal underlayer. Next, the wafer was dipped in a dilute sulfuric acid solution, and the Au surface of the metal underlayer serving as the plating start surface was acid activated. Subsequently, the wafer was immersed in a mixed bath of nickel sulfate and nickel chloride to form a nickel plating film having a thickness of 2 μm on the metal underlayer. Subsequently, the wafer was immersed in a copper sulfate plating bath, and a Cu plating film constituting the support 40 was formed on the nickel plating film (FIG. 3B).

  The support 40 can be made of other materials, for example, a doped Si wafer or Ge wafer, or a metal substrate such as Cu or CuW. Further, the support 40 may be one in which conductivity is formed on the surface of an insulating substrate, or one in which a conductive layer is formed on the surface of a conductive substrate via an insulating layer. Further, the method for forming the support 40 is not limited to the plating method, and the wafer or metal substrate constituting the support and the device layer 30 may be bonded together by thermocompression bonding.

(Growth substrate removal process)
The sapphire substrate, which is the growth substrate 10 used for crystal growth, was removed by a laser lift-off method (LLO method). In the LLO method, a laser is irradiated from the back side of the growth substrate 10 to decompose the GaN-based nitride semiconductor film near the interface with the growth substrate 10 into metal Ga and N ₂ gas. By removing the growth substrate 10, the first buffer layer 21 or the second buffer layer 22 is exposed (FIG. 4A).

(Electrode formation process)
After the metal Ga adhering to the surface of the exposed first buffer layer 21 or second buffer layer 22 is removed by cleaning with hydrochloric acid or the like, the growth substrate 10 is peeled off by photolithography, electron beam heating vapor deposition or the like. Then, Ti (1 nm) / Pt (100 nm) / Au (1500 nm) was sequentially deposited on the surface of the first buffer layer 21 or the second buffer layer 22 exposed to form the n-side electrode 50 (FIG. 4). (B)). Since the first and second buffer layers have conductivity, the n-side electrode 50 can be formed without removing these layers.

  Through the above steps, a laminated semiconductor is completed. According to the laminated semiconductor and the manufacturing method thereof according to the embodiments of the present invention described above, the following effects can be obtained.

  First, since the second buffer layer 22 having a single crystal structure is doped with Si at a relatively low concentration, the crystallinity of the second buffer layer 22 can be kept relatively good. Therefore, the crystallinity of the device layer 30 formed thereon is relatively good.

  Further, in the process of repeatedly laminating the first buffer layer 21 and the second buffer layer 22, each of the laminated layers continues to be exposed to a high temperature, so that the first buffer layer 21 doped with Si at a relatively high concentration is used. Si atoms diffuse toward the second buffer layer 22 doped with Si at a relatively low concentration, and the Si concentration becomes substantially uniform in the first and second buffer layers, and a constant conductivity is obtained in each of these layers. It becomes possible. As described above, when Si doping is performed by thermal diffusion, the influence on crystallinity can be reduced as compared with the case where Si doping is performed by supplying a dopant gas during crystal growth. That is, the second buffer layer 22 can have sufficient conductivity without deteriorating crystallinity.

  For example, in a laminated semiconductor using a growth substrate having conductivity, it is essential to provide conductivity to the buffer layer in order to pass current from the back surface of the growth substrate. According to the semiconductor and its manufacturing method, the buffer layer can be made conductive without sacrificing crystallinity. Further, since the first and second buffer layers have conductivity, so-called thin film LED can be easily manufactured. That is, an electrode can be formed directly on the exposed buffer layer without removing the first and second buffer layers exposed by peeling the growth substrate 10.

  Second, by repeatedly laminating the first buffer layer 21 having an amorphous structure and the second buffer layer 22 having a single crystal structure, it is possible to suppress the occurrence of threading dislocations. That is, dislocations generated in the second buffer layer 22 having a single crystal structure are unlikely to penetrate the first buffer layer 21 having an amorphous structure formed thereon. That is, the epitaxial growth is interrupted by laminating the first buffer layer 21 having an amorphous structure between the second buffer layers 22 having a single crystal structure, so that the second layer positioned at the uppermost portion adjacent to the device layer 30 is second. It is possible to reduce the defect density in the buffer layer 22, thereby reducing the defect density in the device layer 30. Further, since the device layer 30 is formed on the second buffer layer 22 having a single crystal structure, the device layer 30 is compared with the conventional structure in which the device layer is formed on the buffer layer having an amorphous structure. Crystallinity can be improved.

  Third, the second buffer layer 22 includes alternating strain relaxation layers 22 a having a lattice constant intermediate between the lattice constant of the nitride semiconductor constituting the device layer 30 and the lattice constant of the growth substrate, and GaN layers 22 b. Therefore, the lattice strain caused by the lattice mismatch between the growth substrate 10 and the device layer 30 is gradually reduced, and the crystallinity of the device layer 30 is further improved. For example, the second buffer layer 22 has a laminated structure in which strain relaxation layers 22a and GaN layers 22b made of elastic InGaN are alternately stacked, so that a device layer 30 made of a GaN-based nitride semiconductor layer and a sapphire substrate It is possible to alleviate lattice distortion caused by lattice mismatch between the two.

DESCRIPTION OF SYMBOLS 10 Growth substrate 20 Intermediate layer 21 First buffer layer 22 Second buffer layer 22a Strain relaxation layer 22b GaN layer 30 Device layer

Claims (7)

A method for manufacturing a laminated semiconductor including a GaN-based nitride semiconductor film,
Forming an intermediate layer in which a first buffer layer and a second buffer layer are alternately and repeatedly stacked three or more times on a growth substrate made of a material different from the GaN-based nitride semiconductor film;
Forming a device layer by growing a GaN-based nitride semiconductor film on the intermediate layer, and
The first buffer layer is formed by growing an In _x Ga _1-x N (0 <x ≦ 1) film while doping silicon at a temperature lower than a single crystal growth temperature.
The second buffer layer is formed by alternately and repeatedly growing two types of GaN-based nitride semiconductor films having different compositions while doping silicon at a single crystal growth temperature,
The second buffer layer includes In _x Ga _1-x N (0 <x) having a lattice constant intermediate between a lattice constant of the GaN-based nitride semiconductor film constituting the device layer and a lattice constant of the growth substrate. ≦ 1) is formed by alternately laminating strain relaxation layers and GaN layers,
The first buffer layer is silicon doped at a higher concentration than the second buffer layer ;
In the step of forming the intermediate layer, the stacking step of sequentially forming the first buffer layer and the second buffer layer in this order on the growth substrate is repeated three times or more,
In the step of forming the device layer, the device layer is formed adjacent to the second buffer layer;
The intermediate layer is a first buffer doped with silicon at a higher concentration than the second buffer layer by continuously exposing the first buffer layer and the second buffer layer to the single crystal growth temperature. A method of manufacturing, wherein the silicon atoms diffuse from a layer toward the second buffer layer and the intermediate layer has a substantially constant conductivity . The first buffer layer is silicon-doped at a concentration of 1 × 10 ¹⁹ atoms / cm ^{3 to} 1 × 10 ²¹ atoms / cm ³ , and the second buffer layer is 1 × 10 ¹⁶ atoms / cm ^{3 to} 1 ×. 2. The method according to claim 1 , wherein the silicon is doped at a concentration of 10 ¹⁹ atoms / cm ³ or less . Forming a support substrate on the device layer;
The process according to claim 1 or 2, wherein the further comprising the steps of: by the growth substrate is removed to expose the first buffer layer or the second buffer layer. In the stacking step, the first buffer layer is formed at a growth temperature within a range of 350 ° C. to 800 ° C., and the second buffer layer is formed at a growth temperature within a range of 1000 ° C. to 1200 ° C. the process according to any one of claims 1 to 3, characterized in that to form set. A laminated semiconductor including a GaN-based nitride semiconductor film,
  The growth substrate made of a different material from the GaN-based nitride semiconductor film,
  An intermediate layer provided on the growth substrate and formed by alternately and repeatedly stacking a first buffer layer and a second buffer layer at least three times;
  A device layer made of a GaN-based nitride semiconductor provided on the intermediate layer,
  The first buffer layer is formed at a growth temperature lower than a single crystal growth temperature and is silicon-doped In _x Ga _1-x N (0 <x ≦ 1)
  The second buffer layer is formed by alternately and repeatedly laminating two kinds of GaN-based nitride semiconductor films having different compositions, which are formed at a single crystal growth temperature and are silicon-doped,
  The second buffer layer has an lattice constant intermediate between a lattice constant of the GaN-based nitride semiconductor film constituting the device layer and a lattice constant of the growth substrate. _x Ga _1-x Formed by alternately and repeatedly laminating strain relaxation layers made of N (0 <x ≦ 1) and GaN layers,
  The first buffer layer is silicon doped at a higher concentration than the second buffer layer;
  The growth substrate is adjacent to the first buffer layer;
  The device layer is formed adjacent to the second buffer layer;
  In the intermediate layer, the silicon atoms diffuse from the first buffer layer toward the second buffer layer, and a difference in silicon concentration between the first buffer layer and the second buffer layer. The laminated semiconductor is characterized in that the intermediate layer as a whole has electrical conductivity by being reduced in size. The stacked semiconductor according to claim 5, wherein the growth substrate has conductivity. A laminated semiconductor including a GaN-based nitride semiconductor film,
  An intermediate layer formed by alternately and repeatedly laminating the first buffer layer and the second buffer layer at least three times;
  An electrode provided under the intermediate layer;
  A device layer made of a GaN-based nitride semiconductor provided on the intermediate layer;
  A conductive support provided on the device layer,
  The first buffer layer is amorphous or polycrystalline, and silicon-doped In _x Ga _1-x N (0 <x ≦ 1)
  The second buffer layer is a single crystal and silicon-doped In _x Ga _1-x Formed by alternately and repeatedly laminating strain relaxation layers made of N (0 <x ≦ 1) and GaN layers,
  The first buffer layer is silicon doped at a higher concentration than the second buffer layer;
  In the intermediate layer, the silicon atoms diffuse from the first buffer layer toward the second buffer layer, and a difference in silicon concentration between the first buffer layer and the second buffer layer. The laminated semiconductor is characterized in that the intermediate layer as a whole has electrical conductivity by being reduced in size.

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