JP6117010B2 - Nitride semiconductor device, nitride semiconductor wafer, and method of forming nitride semiconductor layer - Google Patents

Description

  Embodiments described herein relate generally to a nitride semiconductor device, a nitride semiconductor wafer, and a method for forming a nitride semiconductor layer.

  A light emitting diode (LED), which is a semiconductor light emitting element using a nitride semiconductor, is used in, for example, a display device or illumination. Electronic devices using nitride semiconductors are used for high-speed electronic devices and power devices.

  In order to improve the performance of such a nitride semiconductor device, it is important to reduce defects in the nitride semiconductor layer. A technique for producing a nitride semiconductor crystal with few dislocations is desired.

JP 2011-233936 A

  Embodiments of the present invention provide a nitride semiconductor device, a nitride semiconductor wafer, and a method for forming a nitride semiconductor layer with few dislocations.

According to the embodiment of the present invention, a nitride semiconductor device including a stacked body and a functional layer is provided. The stacked body includes a first Si-containing layer containing Si at a concentration of 7 × 10 ¹⁹ / cm ³ or more and 4 × 10 ²⁰ / cm ³ or less, a first GaN layer including a convex portion provided in the first Si-containing layer, , A second GaN layer provided in the first GaN layer, and a second Si-containing layer containing Si provided between the first GaN layer and the second GaN layer . The functional layer is provided in the stacked body and includes a nitride semiconductor.
According to another embodiment of the present invention, there is provided a nitride semiconductor wafer including a substrate, a buffer layer provided on the substrate and including a nitride semiconductor, and a stacked body provided on the buffer layer. The stacked body includes a first Si-containing layer containing Si at a concentration of 7 × 10 ¹⁹ / cm ³ or more and 4 × 10 ²⁰ / cm ³ or less, a first GaN layer including a convex portion provided in the first Si-containing layer, , A second GaN layer provided in the first GaN layer, and a second Si-containing layer containing Si provided between the first GaN layer and the second GaN layer.
According to another embodiment of the present invention, the buffer layer provided on the substrate and including the nitride semiconductor contains Si at a concentration of 7 × 10 ¹⁹ / cm ³ or more and 4 × 10 ²⁰ / cm ³ or less. Forming a 1Si-containing layer, forming a first GaN layer including a protrusion on the first Si-containing layer, forming a second GaN layer on the first GaN layer, and between the first GaN layer and the second GaN layer, A method for forming a nitride semiconductor layer is provided that forms a second Si-containing layer containing Si.

1 is a schematic cross-sectional view showing a nitride semiconductor device according to a first embodiment. FIG. 3 is a schematic cross-sectional view showing a part of the nitride semiconductor device according to the first embodiment. FIG. 3A and FIG. 3B are views showing the nitride semiconductor device according to the first embodiment. FIG. 4A to FIG. 4D are views showing the nitride semiconductor device according to the first embodiment. Fig.5 (a)-FIG.5 (f) are typical sectional drawings which show a sample. FIG. 6A to FIG. 6F are scanning electron microscope images of the cross section of the sample. It is a graph which shows the measurement result of the dislocation density in a sample. FIG. 8A to FIG. 8C are schematic views showing the nitride semiconductor device according to the embodiment. FIG. 9A to FIG. 9C are electron micrograph images showing the nitride semiconductor device according to the embodiment. FIG. 10A to FIG. 10D are graphs showing characteristics of the nitride semiconductor device. It is a graph which shows the characteristic of the nitride semiconductor element which concerns on 1st Embodiment. It is a graph which shows the characteristic of the nitride semiconductor element which concerns on 1st Embodiment. FIG. 13A and FIG. 13B are graphs showing characteristics of the nitride semiconductor device according to the first embodiment. It is a graph which shows the characteristic of the nitride semiconductor element which concerns on 1st Embodiment. FIG. 15A and FIG. 15B are graphs showing the characteristics of the nitride semiconductor device according to the first embodiment. It is a graph which shows the characteristic of the nitride semiconductor element which concerns on 1st Embodiment. 1 is a graph showing a nitride semiconductor device according to a first embodiment. FIG. 18A and FIG. 18B are graphs illustrating the nitride semiconductor device of the reference example. 6 is a schematic cross-sectional view illustrating another nitride semiconductor element according to the first embodiment. FIG. 5 is a schematic cross-sectional view showing a nitride semiconductor device according to a second embodiment. FIG. 1 is a schematic cross-sectional view showing a nitride semiconductor device according to an embodiment. 1 is a schematic cross-sectional view showing a nitride semiconductor device according to an embodiment. 6 is a schematic cross-sectional view illustrating another nitride semiconductor element according to the embodiment. FIG. 1 is a schematic cross-sectional view showing a nitride semiconductor device according to an embodiment. It is a flowchart figure which shows the formation method of the nitride semiconductor layer which concerns on 3rd Embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(First embodiment)
The present embodiment relates to a nitride semiconductor device and a nitride semiconductor wafer. The nitride semiconductor device according to the embodiment includes a semiconductor device such as a semiconductor light emitting device, a semiconductor light receiving device, and an electronic device. The semiconductor light emitting element includes, for example, a light emitting diode (LED) and a laser diode (LD). The semiconductor light receiving element includes a photodiode (PD) and the like. The electronic device includes, for example, a high electron mobility transistor (HEMT), a heterojunction bipolar transistor (HBT), a field transistor (FET), a Schottky barrier diode (SBD), and the like. The nitride semiconductor wafer according to the embodiment includes at least a part of the nitride semiconductor device according to the embodiment.

FIG. 1 is a schematic cross-sectional view illustrating the nitride semiconductor device according to the first embodiment.
As shown in FIG. 1, the nitride semiconductor device 110 according to this embodiment includes a stacked body 50 and a functional layer 15. The functional layer 15 is provided on the stacked body 50.

  In this example, the nitride semiconductor device 110 further includes a buffer layer 60. The buffer layer 60 includes a nitride semiconductor. A stacked body 50 is provided on the buffer layer 60. In this example, an AlN buffer layer 62 is used as the buffer layer 60.

  In this example, the nitride semiconductor device 110 further includes a substrate 40. A buffer layer 60 is disposed between the substrate 40 and the stacked body 50.

  The substrate 40 is, for example, a silicon substrate. As the substrate 40, for example, a Si (111) substrate is used. When a silicon substrate is used as the substrate 40, the plane orientation of the silicon substrate may be, for example, a plane orientation represented by (11n) (n: integer). The plane orientation may be, for example, the (100) plane. As the substrate 40, for example, a (110) plane silicon substrate is preferably used. Thereby, the lattice mismatch between the silicon substrate and the nitride semiconductor layer is reduced.

  As the substrate 40, a substrate including an oxide layer may be used. For example, an SOI (silicon on insulator) substrate is used as the substrate 40. As the substrate 40, a substrate of a material different from the lattice constant of the functional layer 15 can be used. As the substrate 40, a substrate made of a material different from the thermal expansion coefficient of the functional layer 15 can be used. For example, as the substrate 40, any one of sapphire, spinel, GaAs, InP, ZnO, Ge, SiGe, and SiC can be used.

  For example, the buffer layer 60 is formed on the substrate 40. A stacked body 50 is formed on the buffer layer 60. The functional layer 15 is formed on the stacked body 50. In these formations, epitaxial growth is performed.

  In the present embodiment, at least a part of the substrate 40 may be removed after the formation of each layer. In the present embodiment, at least a part of the buffer layer 60 may be removed after the formation of each layer.

  As shown in FIG. 1, the stacked body 50 includes an AlGaN layer 51a, a first Si-containing layer 51s, a first GaN layer 51g, a second Si-containing layer 52s, and a second GaN layer 52g.

Al _x Ga _1-x N (0 <x ≦ 1) is used for the AlGaN layer 51a. The AlGaN layer 51a has an upper surface 51au.

  The AlGaN layer 51a may be a single layer or may include a plurality of layers. In this example, the AlGaN layer 51a includes a first AlGaN layer 51aa, a second AlGaN layer 51ab, and a third AlGaN layer 51ac. The number of layers included in the AlGaN layer 51a may be two or four or more. The second AlGaN layer 51ab is provided on the first AlGaN layer 51aa. The third AlGaN layer 51ac is provided on the second AlGaN layer 51ab. The Al composition ratio in the second AlGaN layer 51ab (Al composition ratio in the III element) is lower than the Al composition ratio in the first AlGaN layer 51aa. The Al composition ratio in the third AlGaN layer 51ac is lower than the Al composition ratio in the second AlGaN layer 51ab.

The first Si-containing layer 51s is in contact with the upper surface 51au of the AlGaN layer 51a. Thus, the first Si-containing layer 51s is provided on the AlGaN layer 51a. The first Si-containing layer 51s contains Si at a concentration of 7 × 10 ¹⁹ / cm ³ or more and 4 × 10 ²⁰ / cm ³ or less. The first Si-containing layer 51s has an upper surface 51su. The upper surface 51su of the first Si-containing layer 51s is substantially parallel to the upper surface 51au of the AlGaN layer 51a.

  The first GaN layer 51g is provided on the first Si-containing layer 51s. The first GaN layer 51g is in contact with the upper surface 51su of the first Si-containing layer 51s. The first GaN layer 51g includes a convex portion 51gp. The convex portion 51gp has a slope 51gs. The inclined surface 51gs is inclined with respect to the upper surface 51au of the AlGaN layer 51a. The slope 51gs may be a curved surface.

  The convex portion 51gp may have a top surface 51gt in addition to the inclined surface 51gs. The top surface 51gt is parallel to the upper surface 51au of the AlGaN layer 51a. The convex portion 51gp does not necessarily have to be provided with the top surface 51gt parallel to the upper surface 51au of the AlGaN layer 51a.

  The first GaN layer 51g has an island shape, for example. An island-like film is also called a “layer”. A plurality of independent plurality of convex portions 51gp may be provided. The first GaN layer 51g may be continuous.

  The second Si-containing layer 52s is provided on the first GaN layer 51g. The second Si-containing layer 52s is in contact with the first GaN layer 51g. The second Si-containing layer 52s contains Si. The second Si-containing layer 52s covers, for example, the first GaN layer 51g.

  In this example, a part of the second Si-containing layer 52s is in contact with the first Si-containing layer 51s. For example, the upper surface 51su of the first Si-containing layer 51s includes a first region 51sp and a second region 51sq. The first GaN layer 51g is provided on the first region 51sp. For example, the convex portion 51gp of the first GaN layer 51g is provided on the first region 51sp. The first GaN layer 51g is not provided on the second region 51sq. A part of the second Si-containing layer 52s is in contact with the first Si-containing layer 51s in the second region 51sq.

  As will be described later, the first GaN layer 51g may cover the upper surface 51su of the first Si-containing layer 51s. In this case, the second Si-containing layer 52s does not contact the first Si-containing layer 51s. Hereinafter, an example (nitride semiconductor element 110) in which a part of the second Si-containing layer 52s is in contact with the first Si-containing layer 51s will be described.

  The second Si-containing layer 52s is along the shape of the first GaN layer 51g (the shape of the convex portion 51gp). The upper surface of the second Si-containing layer 52s is uneven along the shape of the protrusion 51gp.

  A second GaN layer 52g is provided on the second Si-containing layer 52s. The second GaN layer 52g fills the recesses of the irregularities of the first GaN layer 51g (irregularities of the second Si-containing layer 52s). The upper surface of the second GaN layer 52g is substantially flat.

The first GaN layer 51g includes, for example, Al _z1 Ga _1-z1 N (0 ≦ z1 <1, z1 <x). For example, GaN is used for the first GaN layer 51g. The first GaN layer 51g may contain an n-type impurity.

The second GaN layer 52g includes, for example, Al _{z2Ga1 -z2N} (0 ≦ z2 <1, z2 <x). For example, GaN is used for the second GaN layer 52g. The second GaN layer 52g may contain an n-type impurity.

  For example, at least one of Si, Ge, Te, Sb, and O is used as the n-type impurity.

  A direction perpendicular to the upper surface 51au of the AlGaN layer 51a is taken as a Z-axis direction. One direction perpendicular to the Z-axis direction is taken as an X-axis direction. A direction perpendicular to the Z-axis direction and the X-axis direction is taken as a Y-axis direction.

  The functional layer 15 is stacked with the stacked body 50 along the Z-axis direction. In the specification of the application, “stacking” includes not only the case of being stacked in contact with each other but also the case of being stacked with another layer inserted therebetween. Further, “provided on” includes not only the case of being provided in direct contact but also the case of being provided with another layer interposed therebetween.

  The Z-axis direction is perpendicular to the upper surface 51su of the first Si-containing layer 51s. The interface 151 between the stacked body 50 and the functional layer 15 is perpendicular to the Z-axis direction.

  The thickness of the AlGaN layer 51a is, for example, 100 nanometers (nm) or more and 500 nm or less (for example, about 250 nm). The composition ratio of Al in the group III element in the AlGaN layer 51a is, for example, not less than 0.15 and not more than 0.35 (for example, 0.25).

  The thickness ts1 of the first Si-containing layer 51s is, for example, not less than 0.4 atomic layers and not more than 2 atomic layers. The thickness ts1 is, for example, not less than 0.1 nm and not more than 2 nm. The first Si-containing layer 51s may not be a uniform film, but may be a discontinuous island-shaped film or the like. The first Si-containing layer 51s may be a film provided with an opening.

  The height tg1 of the convex portion 51gp of the first GaN layer 51g is, for example, not less than 100 nm and not more than 1000 nm. When the first GaN layer 51g is provided on a part of the first Si-containing layer 51s as in this example, the height tg1 of the convex portion 51gp is equal to the upper surface 51su of the first Si-containing layer 51s and the first GaN layer 51g. It is the distance between the upper end of the convex part 51gp. When the convex portion 51gp has the top surface 51gt, the height tg1 is a distance between the top surface 51su of the first Si-containing layer 51s and the top surface 51gt. The height tg1 of the convex portion 51gp of the first GaN layer 51g is such that the upper surface 51su of the first Si-containing layer 51s in the convex portion 51gp having the highest height among the convex portions 51gp of the first GaN layer 51g and the first GaN layer 51g It is set as the distance between the upper end of the convex part 51gp.

  As will be described later, the first GaN layer 51g may cover the first Si-containing layer 51s. In this case, the height of the convex portion 51gp in the first GaN layer 51g is the height (depth) of the irregularities of the first GaN layer 51g, that is, along the Z-axis direction between the convex and concave portions of the irregularities. Corresponds to distance.

  The first GaN layer 51g is provided with a convex portion 51gp, and the thickness of the first GaN layer 51g is not uniform. The thickness of the first GaN layer 51g is different from the height tg1 of the convex portion 51gp of the first GaN layer 51g. The thickness of the first GaN layer 51g is the average thickness of the first GaN layer 51g.

  The thickness ts2 of the second Si-containing layer 52s is, for example, not less than 0.4 atomic layer and not more than 1.5 atomic layer. The thickness ts2 is, for example, not less than 0.1 nm and not more than 1.5 nm. The second Si-containing layer 52s may not be a uniform film, but may be a discontinuous island film or the like. The second Si-containing layer 52s may be a film provided with an opening.

  The thickness tg2 of the second GaN layer 52g is, for example, not less than 100 nm and not more than 5000 nm. The thickness tg2 of the second GaN layer 52g is the Z between the upper end of the second Si-containing layer 52s and the upper surface of the second GaN layer 52g (in this example, the interface 15l between the stacked body 50 and the functional layer 15). The distance along the axial direction.

  The thickness of the AlGaN layer 51a, the thickness ts1 of the first Si-containing layer 51s, the thickness of the first GaN layer 51g, and the thickness ts2 of the second Si-containing layer 52s are lengths along the Z-axis direction. The thickness of the second Si-containing layer 52s is, for example, along the direction perpendicular to the inclined surface 51gs of the portion of the second Si-containing layer 52s provided on the inclined surface 51gs of the convex portion 51gp of the first GaN layer 51g. Length.

  These thicknesses are obtained from, for example, at least one of a scanning electron microscope (SEM) image and a transmission electron microscope (TEM) image.

  The thickness of the functional layer 15 is, for example, about 1.5 micrometers (μm) or more and 5 μm or less (for example, 2 μm).

  The functional layer 15 includes, for example, a layer having a light emitting function of a semiconductor light emitting element. The functional layer 15 includes, for example, a layer having a light receiving function of a semiconductor light receiving element. The functional layer 15 includes, for example, a layer having a function of at least one of rectification, switching, and amplification of an electronic device. Below, the example in case the functional layer 15 contains the layer which has a light emission function is demonstrated.

FIG. 2 is a schematic cross-sectional view illustrating a part of the nitride semiconductor device according to the first embodiment.
FIG. 2 shows an example of the configuration of the functional layer 15. As shown in FIG. 2, in this example, the functional layer 15 includes an n-type semiconductor layer 10, a p-type semiconductor layer 20, and a light emitting layer 30. The light emitting layer 30 is provided between the n-type semiconductor layer 10 and the p-type semiconductor layer 20. The n-type semiconductor layer 10 includes a nitride semiconductor. The p-type semiconductor layer 20 includes a nitride semiconductor. The light emitting layer 30 includes a nitride semiconductor.

  The functional layer 15 may further include a low impurity concentration layer 10i. The impurity concentration in the low impurity concentration layer 10 i is lower than the impurity concentration in the n-type semiconductor layer 10. The low impurity concentration layer 10i is provided as necessary and may be omitted. A low impurity concentration layer 10 i is provided on the stacked body 50.

  The n-type semiconductor layer 10 is provided on the stacked body 50. The n-type semiconductor layer 10 is provided on the low impurity concentration layer 10i. A light emitting layer 30 is provided on the n-type semiconductor layer 10. A p-type semiconductor layer 20 is provided on the light emitting layer 30.

  The light emitting layer 30 includes a plurality of barrier layers 31 and a well layer 32 provided between the plurality of barrier layers 31. The number of well layers 32 may be one or plural. That is, the light emitting layer 30 has, for example, an SQW (Single-Quantum Well) structure or an MQW (Multi-Quantum Well) structure.

  The band gap energy of the barrier layer 31 is larger than the band gap energy of the well layer 32. For the well layer 32, for example, InGaN is used. GaN is used for the barrier layer 31. When InGaN is used for the barrier layer 31, the In composition ratio in the barrier layer 31 is lower than the In composition ratio in the well layer 32. The peak wavelength of light emitted from the light emitting layer 30 is, for example, not less than 200 nm and not more than 1900 nm.

  1 and 2 also illustrate the configuration of the nitride semiconductor wafer 210 according to this embodiment. The nitride semiconductor wafer 210 includes a substrate 40, a buffer layer 60, and a stacked body 50. The nitride semiconductor wafer 210 may further include a functional layer 15. Each of the configurations described with respect to the nitride semiconductor element 110 can be applied to the substrate 40, the buffer layer 60, the stacked body 50, and the functional layer 15.

  An example of a method for manufacturing a nitride semiconductor device and a nitride semiconductor wafer according to this embodiment will be described.

  As the substrate 40, for example, a silicon substrate whose main surface is a (111) plane is used. The substrate 40 is cleaned using, for example, a mixed chemical solution of sulfuric acid and hydrogen peroxide and dilute hydrofluoric acid. After cleaning, the substrate 40 is introduced into the reaction chamber of the MOCVD apparatus.

The substrate 40 is heated to 1080 ° C., for example. In a mixed atmosphere where the ratio of hydrogen to nitrogen is 2: 1, trimethylaluminum (TMAl) is supplied at a flow rate of 50 cc / min and ammonia (NH ₃ ) at a flow rate of 0.8 L / min for 20 minutes. As a result, an AlN buffer layer 60 (AlN buffer layer 62) is formed. The thickness of the AlN buffer layer 62 is, for example, about 100 nm.

  The substrate temperature (the temperature of the substrate 40) is set to 1040 ° C. In a mixed atmosphere where the ratio of hydrogen and nitrogen is 2: 1, trimethylgallium (TMGa) is supplied at a flow rate of 10 cc / min, TMAl at a flow rate of 50 cc / min, and ammonia at a flow rate of 2.5 L / min for 5 minutes. Thereby, the first AlGaN layer 51aa is formed. The Al composition ratio in the first AlGaN layer 51aa is 0.55. The thickness of the first AlGaN layer 51aa is, for example, about 100 nm.

  The TMGa flow rate is changed to 17 cc / min, and the TMAl flow rate is changed to 30 cc / min, and supplied for 10 minutes. Thereby, the second AlGaN layer 51ab is formed. The Al composition ratio in the second AlGaN layer 51ab is, for example, 0.3. The thickness of the second AlGaN layer 51ab is, for example, about 200 nm.

  The TMGa flow rate is changed to 20 cc / min and the TMAl flow rate is changed to 15 cc / min and supplied for 11 minutes. Thereby, the third AlGaN layer 51ac is formed. The Al composition ratio in the third AlGaN layer 51ac is, for example, 0.15. The thickness of the third AlGaN layer 51ac is, for example, about 250 nm.

Maintaining the substrate temperature at 1040 ° C., in a mixed atmosphere where the ratio of hydrogen and nitrogen is 2: 1, silane (SiH ₄ ) at a concentration of 10 ppm is flowed at 350 cc / min, and ammonia is flowed at 20 L / min for 8 minutes. Supply. Thereby, the first Si-containing layer 51s is formed. The thickness of the first Si-containing layer 51s is, for example, about one atomic layer. The Si concentration of the first Si-containing layer 51s is, for example, 2 × 10 ²⁰ / cm ³ .

  In a mixed atmosphere where the substrate temperature is 1090 ° C. and the ratio of hydrogen and nitrogen is 2: 1, TMGa is supplied at a flow rate of 56 cc / min and ammonia is supplied at a flow rate of 40 L / min for 5 minutes. Thereby, the first GaN layer 51g is formed. For example, the first GaN layer 51g is an island-shaped crystal. The convex portion 51gp of the first GaN layer 51g has an inclined surface 51gs inclined with respect to the XY plane. The height tg1 of the convex portion 51gp of the first GaN layer 51g is, for example, about 400 nm.

In a mixed atmosphere with a substrate temperature of 1040 ° C. and a nitrogen ratio of 2: 1, silane (SiH ₄ ) with a concentration of 10 ppm is supplied at a flow rate of 350 cc / min and ammonia is supplied at a flow rate of 20 L / min for 3 minutes. Thereby, the second Si-containing layer 52s is formed. The thickness of the second Si-containing layer 52s is, for example, about 0.4 atomic layer. The Si concentration of the second Si-containing layer 51s is, for example, 7.5 × 10 ¹⁹ / cm ³ .

  In a mixed atmosphere where the substrate temperature is 1090 ° C. and the ratio of hydrogen to nitrogen is 2: 1, TMGa is supplied at a flow rate of 56 cc / min and ammonia is supplied at a flow rate of 40 L / min for 60 minutes. Thereby, the second GaN layer 52g is formed. The thickness of the second GaN layer 52g is about 2 μm, for example.

Further, TMGa is supplied at a flow rate of 56 cc / min, ammonia is supplied at a flow rate of 40 L / min, and silane (SiH ₄ ) at a concentration of 10 ppm is supplied at a flow rate of 56 cc / min for 30 minutes. Thereby, an n-type GaN layer is formed. The Si concentration in the n-type GaN layer is, for example, 5 × 10 ¹⁸ (/ cm ³ ). The thickness of the n-type GaN layer is, for example, about 1 μm. The n-type GaN layer becomes the n-type semiconductor layer 10 (at least a part of the functional layer 15). Thereby, the nitride semiconductor device or nitride semiconductor wafer according to the present embodiment can be formed.

  The low impurity concentration layer 10i may be formed before the formation of the n-type GaN layer. By further forming the light emitting layer 30 and the p-type semiconductor layer 20 on the n-type semiconductor layer 10, the nitride semiconductor element 110 and the nitride semiconductor wafer 210 can be formed.

FIG. 3A and FIG. 3B are views illustrating the nitride semiconductor device according to the first embodiment.
FIG. 3A is a cross-sectional TEM image of the nitride semiconductor device and the nitride semiconductor wafer. FIG. 3B is a schematic diagram drawn based on FIG. In FIG. 3B, the configurations of the first Si-containing layer 51s, the first GaN layer 51g, the second Si-containing layer 52s, and the second GaN layer 52g included in the stacked body 50 are schematically illustrated. The shape of the first Si-containing layer 51s and the shape of the second Si-containing layer 52s are drawn with solid lines. Dislocations 80 in the region above the first Si-containing layer 51s are schematically drawn with dotted lines.

  As can be seen from FIGS. 3A and 3B, dislocations 80 are generated at the interface between the substrate 40 and the AlN buffer layer 62. The density of dislocations 80 is very high in the AlN buffer layer 62 and the AlGaN layer 51a. The dislocations 80 are greatly reduced in the layer above the first Si-containing layer 51s. By providing the first Si-containing layer 51s, the density of dislocations 80 is reduced. The first Si-containing layer 51 s has an effect of shielding the dislocation 80.

  In this example, a part of the second Si-containing layer 52s is in contact with the first Si-containing layer 51s. In the region where the second Si-containing layer 52s is in contact with the first Si-containing layer 51s, the total thickness of the Si-containing layers is thick. In this region, it is considered that the shielding effect of dislocations 80 is enhanced by the first Si-containing layer 51s and the second Si-containing layer 52s. This is considered to further reduce the density of dislocations 80.

  Further, the density of dislocations 80 is further reduced in the second GaN layer 52g. That is, the density of dislocations 80 is reduced in the region between the first Si-containing layer 51s and the second GaN layer 52g (that is, the region including the first GaN layer 51g and the second Si-containing layer 52s).

  A part of the dislocation 80 is bent inside the first GaN layer 51g. This is because the first GaN layer 51g is three-dimensionally grown by forming the first GaN layer 51g on the first Si-containing layer 51s. Propagation of the dislocation 80 in the stacking direction is suppressed by bending a part of the dislocation 80.

  Further, the dislocations 80 are further reduced on the slope 51gs of the convex portion 51gp of the first GaN layer 51g. This phenomenon will be further described.

FIG. 4A to FIG. 4D are diagrams illustrating the nitride semiconductor device according to the first embodiment.
FIG. 4A and FIG. 4C are cross-sectional TEM images of the nitride semiconductor element and the nitride semiconductor wafer. FIG. 4A is an enlarged image of the slope 51gs portion of the first GaN layer 51g. FIG. 4C is an enlarged image of the top surface 51gt portion of the first GaN layer 51g. FIG. 4B is a schematic diagram drawn based on FIG. FIG.4 (d) is the schematic diagram drawn based on FIG.4 (c). 4B and 4D, the shape of the first Si-containing layer 51s and the shape of the second Si-containing layer 52s are drawn with solid lines. Dislocations 80 in the region above the first Si-containing layer 51s are schematically drawn with dotted lines.

  As can be seen from FIGS. 4A and 4B, the dislocation 80 disappears in the second GaN layer 52g provided on the slope 51gs of the convex portion 51gp of the first GaN layer 51g. Thus, the dislocation 80 decreases on the slope 51gs. For example, the first GaN layer 51g has a plurality of first dislocations 81 connected to the inclined surface 51gs in the convex portion 51gp. The number of dislocations 80 in the second GaN layer 52g that are continuous with the first dislocations 81 via the second Si-containing layer 52s is smaller than the number of the plurality of first dislocations 81. In the region shown in FIGS. 4A and 4B, the number of dislocations 80 in the second GaN layer 52g that are continuous with the first dislocations 81 through the second Si-containing layer 52s is observed as 0. Is done. In contrast, the number of first dislocations 81 connected to the slope 51gs is large in the convex portion 51gp. Thus, the phenomenon that the dislocation 80 decreases on the slope 51gs is a phenomenon newly found by the inventor of the present application.

  On the other hand, as shown in FIGS. 4C and 4D, the second GaN layer 52g provided on the top surface 51gt of the convex portion 51gp of the first GaN layer 51g has an effect of suppressing the dislocation 80. small. In this example, the dislocation 80 (second dislocation 82) on the lower side (first GaN layer 51g) of the top surface 51gt is connected to the dislocation 80 (third dislocation 83) on the upper side (second GaN layer 52g) of the top surface 51gt. Yes. In the second Si-containing layer 52s, in the portion located on the top surface 51gt, the change in the dislocation 80 is small, and the dislocation 80 propagates from the first GaN layer 51g toward the second GaN layer 52g.

  Thus, the dislocation reduction effect on the slope 51gs is greater than the dislocation reduction effect on the top surface 51gt.

  For example, when the convex portion 51gp of the first GaN layer 51g has a top surface 51gt parallel to the upper surface 51au of the AlGaN layer 51a, the first GaN layer 51g has the first dislocation 81 (see FIG. 4B). The second dislocation 82 (see FIG. 4D). The first dislocation 81 is connected to the slope 51gs of the convex portion 51gp in the convex portion 51gp. The second dislocation 82 is connected to the top surface 51gt in the convex portion 51gp.

  The second GaN layer 52 g has a plurality of third dislocations 83. A part of the plurality of third dislocations 83 is continuous with the second dislocations 82. Even when dislocations continue through the thin second Si-containing layer 52s, the dislocations continue. Of the plurality of third dislocations 83, the number of third dislocations 83 (for example, positive integer N1 of 0 or more) that are continuous with the first dislocation 81 is the number of third dislocations (for example, positive integer N3). The ratio is the first ratio (N1 / N3). Among the plurality of third dislocations 83, the ratio of the number of third dislocations 83 (for example, a positive integer N2) continuous with the second dislocation 82 to the number of third dislocations (N3) is set to the second ratio (N2 / N3). The first ratio (N1 / N3) is lower than the second ratio (N2 / N3).

  The number of the plurality of first dislocations 81 in the convex portion 51gp is N01. The number of the plurality of second dislocations 82 in the convex portion 51g is N02. For example, among the plurality of third dislocations 83, the ratio (N1 / N01) of the number (N1) of third dislocations 83 that are continuous with the first dislocation 81 to the number (N01) of the plurality of first dislocations is a plurality of the first dislocations 83. Among the three dislocations 83, the ratio (N2 / N02) of the number (N2) of the third dislocations 83 continuous with the second dislocations 82 to the number (N02) of the plurality of second dislocations 82 is lower.

  Thus, in the case where the convex portion 51gp having the slope 51gs is provided, the dislocation 80 transmitted to the second GaN layer 52g can be significantly reduced by forming the second Si-containing layer 52s in contact with the slope 51gs. Thereby, the dislocation 80 reaching the functional layer 15 can be greatly reduced.

  FIGS. 3A and 3B and FIGS. 4A to 4D also show the characteristics of the nitride semiconductor wafer according to this embodiment. Also in the nitride semiconductor wafer according to the embodiment, dislocations can be reduced similarly to the nitride semiconductor element.

  According to the embodiment, a nitride semiconductor device and a nitride semiconductor wafer with few dislocations can be provided.

  Hereinafter, experimental results regarding samples of nitride semiconductor devices (or nitride semiconductor wafers) having various configurations will be described.

FIG. 5A to FIG. 5F are schematic cross-sectional views illustrating samples.
As shown in FIG. 5A, the first sample 151 is provided with the AlGaN layer 51a, the first Si-containing layer 51s, the first GaN layer 51g, the second Si-containing layer 52s, and the second GaN layer 52g. . The first GaN layer 51g is provided on a part of the first Si-containing layer 51s, and a part of the second Si-containing layer 52s is in contact with the first Si-containing layer 51s. The first GaN layer 51g includes a convex portion 51gp having a slope 51gs. The first sample 151 corresponds to the nitride semiconductor device 110 or the nitride semiconductor wafer 210 described above. The manufacturing method of the first sample 151 is the same as the manufacturing method described regarding the nitride semiconductor device 110.

  As shown in FIG. 5B, the second sample 152 also includes an AlGaN layer 51a, a first Si-containing layer 51s, a first GaN layer 51g, a second Si-containing layer 52s, and a second GaN layer 52g. In the second sample 152, the first GaN layer 51g is provided on the entire surface of the first Si-containing layer 51s. The second Si-containing layer 52s is not in contact with the first Si-containing layer 51s. The first GaN layer 51g includes a convex portion 51gp having a slope 51gs. The first GaN layer 51g is continuous. A part of the manufacturing method of the second sample 152 is different from the manufacturing method of the first sample 151. In the second sample 152, TMGa is supplied at a flow rate of 112 cc / min and ammonia is supplied at a flow rate of 40 L / min for 2.5 minutes in forming the first GaN layer 51g. That is, the growth rate of the first GaN layer 51g in the second sample 152 is twice the growth rate of the first GaN layer 51g in the first sample 151. Other conditions are the same as those of the first sample 151.

  As shown in FIG. 5C, the third sample 153 also includes an AlGaN layer 51a, a first Si-containing layer 51s, a first GaN layer 51g, a second Si-containing layer 52s, and a second GaN layer 52g. In the third sample 153, the first GaN layer 51g does not include the convex portion 51gp. The first GaN layer 51g is flat. The thickness of the first GaN layer 51g is about 600 nm. The second Si-containing layer 52s is also flat. In the production of the third sample 153, the growth time of the first GaN layer 51g is 15 minutes. Other conditions are the same as those of the first sample 151.

  As shown in FIG. 5D, the fourth sample 154 includes an AlGaN layer 51a, a first GaN layer 51g, a second Si-containing layer 52s, and a second GaN layer 52g. In the fourth sample 154, the first Si-containing layer 51s is not provided. The first GaN layer 51g includes a convex portion 51gp having a slope 51gs. The first GaN layer is continuous. In the fourth sample 154, in the formation of the first GaN layer 51g, the supply amount of ammonia is 2.5 L / min. That is, the V / III ratio in forming the first GaN layer 51g in the fourth sample 154 is 1/16 of that in the first sample 151. Other conditions are the same as those of the first sample 151.

  As shown in FIG. 5E, in the fifth sample 155, an AlGaN layer 51a, a first GaN layer 51g, a second Si-containing layer 52s, and a second GaN layer 52g are provided. In the fifth sample 155, the first Si-containing layer 51s is not provided. Furthermore, the first GaN layer 51g does not include the convex portion 51gp, and the first GaN layer 51g is flat. The fifth sample 155 corresponds to a configuration in which the first Si-containing layer 51s is not provided in the third sample 153.

  As shown in FIG. 5F, in the sixth sample 156, an AlGaN layer 51a, a second Si-containing layer 52s, and a second GaN layer 52g are provided. In the sixth sample 156, the first Si-containing layer 51s and the first GaN layer 51g are not provided in the third sample 153.

FIG. 6A to FIG. 6F are scanning electron microscope images of the cross section of the sample.
6A to 6F show cross-sectional SEM images of the first to sixth samples 151 to 156, respectively.
As can be seen from FIG. 6A, in the first sample 151, the first GaN layer 51g includes a convex portion 51gp having a slope 51gs. In the region between the convex portions 51gp, a part of the second Si-containing layer 52s is in contact with the first Si-containing layer 51s. The height of the unevenness in the first GaN layer 51g (the height tg1 of the convex portion 51gp) is about 400 nm.

  As can be seen from FIG. 6B, in the second sample 152, the first GaN layer 51g is provided with a convex portion 51gp, but the first GaN layer 51g is a continuous crystal. The second Si-containing layer 52s is not in contact with the first Si-containing layer 51s. The height of the protrusion 51gp (the height of the unevenness) in the first GaN layer 51g is about 300 nm. The height of the unevenness of the first GaN layer 51g in the second sample 152 is smaller than the height of the unevenness of the first GaN layer 51g in the first sample 151 (nitride semiconductor element 110). In the second sample 152, the crystal density of the first GaN layer 51g is high, and the first GaN layer 51g is a continuous crystal. When the growth rate of the GaN layer is increased, the height of the unevenness is reduced and the density of the crystal is increased.

  As can be seen from FIG. 6C, in the third sample 153, the first GaN layer 51g has no protrusion. The first GaN layer 51g is a flat film.

  As can be seen from FIG. 6D, in the fourth sample 154, the first Si-containing layer 51s is not provided. The first GaN layer 51g includes a convex portion 51gp having a slope 51gs. The first GaN layer 51g is continuous.

  As can be seen from FIG. 6 (e), the fifth sample 155 is not provided with the first Si-containing layer 51s. Furthermore, the first GaN layer 51g is flat.

  As can be seen from FIG. 6F, in the sixth sample 156, the first Si-containing layer 51s and the first GaN layer 51g are not provided.

FIG. 7 is a graph showing an example of measurement results of dislocation density in a sample.
FIG. 7 shows the measurement results of the dislocation density (edge dislocation density) in the first to sixth samples 151 to 156. The vertical axis represents the edge dislocation density De. The edge dislocation density De is derived from the full width at half maximum of the rocking curve of the X-ray diffraction measurement.

As shown in FIG. 7, the edge dislocation density De in the first sample 151 is 2.8 × 10 ⁻⁸ (/ cm ² ), and the dislocation density is low. The edge dislocation density De in the first sample 151 corresponds to the edge dislocation density in the nitride semiconductor element 110 or the nitride semiconductor wafer 210. In the first sample 151, it is considered that the edge dislocation density De is reduced due to the following.

  The first GaN layer 51g grows three-dimensionally, and the dislocation 80 generated in the buffer layer 60 can be bent in the first GaN layer 51g in a direction parallel to the stacking direction (Z-axis direction). Thereby, dislocations 80 reaching the upper layer (functional layer 15) can be reduced.

  In the region where the growth of the first GaN layer 51g is suppressed by the first Si-containing layer 51s (the region between the convex portions 51gp), the dislocation 80 generated in the buffer layer 60 is shielded by the first Si-containing layer 51s. Thereby, propagation to the upper layer of the dislocation 80 is suppressed, and the dislocation 80 can be reduced.

  Furthermore, the number of dislocations 80 propagating to the upper layer side decreases on the slope 51gs of the convex portion 51gp of the first GaN layer 51g. The dislocation 80 bends on the slope 51gs. That is, the dislocation 80 bends in the second Si-containing layer 52s provided on the slope 51gs. On the slope 51gs, the propagation of the dislocation 80 is blocked. As a result, the dislocation 80 reaching the upper layer can be greatly reduced.

As shown in FIG. 7, the edge dislocation density De in the second sample 152 is 4.8 × 10 ⁻⁸ (/ cm ² ), and the dislocation density is low. The edge dislocation density De in the first sample 151 is lower than the edge dislocation density De in the second sample 152. In the second sample 152, the second Si-containing layer 52s is not in contact with the first Si-containing layer 51s. For this reason, in the 2nd sample 152, it is thought that the shielding effect of the dislocation 80 propagating from the AlGaN layer 51a is small. In the configuration in which the second Si-containing layer 52s is in contact with the first Si-containing layer 51s (for example, the first sample 151), the edge dislocation density De can be reduced to about 60% compared to the configuration in which the second Si-containing layer 52s is not in contact (for example, the second sample 152). .

As can be seen from FIG. 7, in the third sample 153, the edge dislocation density De is 6.2 × 10 ⁻⁸ (/ cm ² ), and the dislocation density is high. In the third sample 153, the first GaN layer 51g is not provided with the convex portion 51gp. For this reason, the bending effect or shielding effect of the dislocation 80 on the slope 51gs of the convex part 51gp cannot be obtained. Further, the second Si-containing layer 52s is not in contact with the first Si-containing layer 51s. For this reason, the shielding effect of the dislocation 80 is small. From the above, it is considered that the edge dislocation density De is high in the third sample 153.

As can be seen from FIG. 7, in the fourth sample 154, the edge dislocation density De is 7.5 × 10 ⁻⁸ (/ cm ² ), and the dislocation density is high. In the fourth sample 154, since the first Si-containing layer 51s is not provided, the shielding effect of the dislocation 80 by the first Si-containing layer 51s cannot be obtained. The edge dislocation density De in the fourth sample 154 is about 1.6 times the edge dislocation density De in the second sample 152. That is, in the configuration in which the first Si-containing layer 51s is provided (for example, the second sample 152), the edge dislocation density De can be reduced to about 64% compared to the configuration in which the first Si-containing layer 51s is not provided (for example, the fourth sample 154).

As can be seen from FIG. 7, in the fifth sample 155, the edge dislocation density De is 1.1 × 10 ⁻⁹ (/ cm ² ), and the dislocation density is high. In the fifth sample 155, the first Si-containing layer 51s is not provided. For this reason, the shielding effect of the dislocation 80 by the first Si-containing layer 51s cannot be obtained. Further, in the fifth sample 155, the first GaN layer 51g is not provided with the convex portion 51gp. For this reason, the bending effect or shielding effect of the dislocation 80 by the slope 51gs of the convex part 51gp (or the second Si-containing layer 52s provided on the slope 51gs) cannot be obtained. For this reason, in the 5th sample 155, it is thought that edge dislocation density De is high. The edge dislocation density De in the fifth sample 155 is about 1.7 times that in the fourth sample 154. That is, in the configuration in which the first GaN layer 51g includes the convex portion 51gp having the inclined surface 51gs (for example, the fourth sample 154), the edge dislocation density is higher than that in the configuration in which the first GaN layer 51g is flat (for example, the fifth sample 155). De can be reduced to about 70%.

As can be seen from FIG. 7, in the sixth sample 156, the edge dislocation density De is 6.0 × 10 ⁻⁸ (/ cm ² ), and the dislocation density is high. In the sixth sample 156, the first GaN layer 51g and the second Si-containing layer 52s are not provided. For this reason, the bending effect or shielding effect of the dislocation 80 by the slope 51gs of the convex part 51gp of the first GaN layer 51g (or the second Si-containing layer 52s provided on the slope 51gs) cannot be obtained. In addition, since the Si-containing layer is one layer and the second Si-containing layer 52s is in contact with the first Si-containing layer 51s, the shielding effect of the dislocations 80 cannot be enhanced. From the above, in the sixth sample 156, it is considered that the edge dislocation density De is high.

  As described above, the stack 50 includes the AlGaN layer 51a, the first Si-containing layer 51s, the first GaN layer 51g including the convex portion 51gp having the slope 51gs, the second Si-containing layer 52s, and the second GaN layer 52g. By providing, the dislocation density can be reduced. A nitride semiconductor device and a nitride semiconductor wafer with few dislocations can be obtained.

  Dislocations can be reduced by the configuration of the first sample 151 and the second sample 152. In the configuration in which the first GaN layer 51g is provided on a part of the first Si-containing layer 51s and the second Si-containing layer 52s is in contact with the first Si-containing layer 51s as in the first sample 151, the dislocation density Reduction effect is high.

FIG. 8A to FIG. 8C are schematic views showing the nitride semiconductor device according to the embodiment.
FIG. 8A and FIG. 8B are graphs showing examples of results of energy dispersive X-ray spectroscopic analysis (EDS analysis) of 110 (or the nitride semiconductor wafer 210) according to the embodiment. FIG. 8C shows the analysis location in the EDS analysis. FIG. 8C shows the first analysis position Ap1 and the second analysis position Ap2 on the cross-sectional TEM image illustrated in FIG. 4C as EDS analysis locations. The first analysis position Ap1 corresponds to the position of the first Si-containing layer 51s. The second analysis position Ap2 corresponds to the position of the second Si-containing layer 52s.

  FIG. 8A corresponds to the analysis result at the first analysis position Ap1. FIG. 8B corresponds to the analysis result at the second analysis position Ap2. The horizontal axis of Fig.8 (a) and FIG.8 (b) is energy Eg (keV: kiloelectron volt | bolt). The vertical axis represents intensity I (counts). The detection limit of Si in this EDS analysis is 1000 ppm.

In this example, the growth time TMs1 of the first Si-containing layer 51s is 8 minutes. This condition corresponds to the condition that the Si surface density in the first Si-containing layer 51s is 1.2 × 10 ¹⁵ / cm ² . The growth time TMs2 of the second Si-containing layer 52s is 3 minutes. This condition corresponds to the condition that the Si surface density in the second Si-containing layer 52s is 3.8 × 10 ¹⁴ / cm ² .

  As can be seen from FIGS. 8A and 8B, in the present embodiment, Si is detected from the first Si-containing layer 51s and the second Si-containing layer 52s. The Si concentration in the first Si-containing layer 51s is estimated to be about 4.5 (atomic /%). The Si concentration in the second Si-containing layer 52s is estimated to be about 3.9 (atomic /%). Thus, in the present embodiment, the Si concentration in the Si-containing layer is not less than the detection limit (1000 ppm). By setting the Si concentration in the Si-containing layer to 1000 ppm or more, a great effect of reducing dislocations can be obtained.

  As a method for growing a group III nitride semiconductor, crystal nuclei of a group III nitride semiconductor are formed in an island shape, and then a silicon source gas and a group III source gas are alternately supplied while supplying a nitrogen source gas. There is a method in which crystal nuclei are grown in island shapes, and further, a nitrogen source gas and a group III source gas are supplied to grow group III nitride semiconductors from the island-like crystal nuclei. In this method, a group III nitride semiconductor is grown laterally from a crystal nucleus, and dislocations are concentrated at the junction where crystals grown from adjacent crystal nuclei join, and the difference in thickness of the crystal nuclei is utilized. Confine dislocations to reduce the dislocation density in the upper layer. That is, dislocations are reduced between crystal nuclei. In this method, Si is hardly detected from the buffer layer or the crystal nucleus in the EDS analysis in which the detection limit of Si is 1000 ppm.

On the other hand, in the nitride semiconductor device and the nitride semiconductor wafer according to the present embodiment, the dislocation 80 in the convex portion 51gp of the first GaN layer 51g is provided with the second Si provided on the inclined surface 51gs of the convex portion 51gp. It decreases in the layer 52s. And as already demonstrated, in this embodiment, Si concentration in Si content layer is fully more than a detection limit. The Si concentration in the first Si-containing layer 51 s is, for example, 7 × 10 ¹⁹ / cm ³ or more and 4 × 10 ²⁰ / cm ³ or less.

Hereinafter, an example of a configuration according to the present embodiment will be described.
The buffer layer 60 includes, for example, an AlN buffer layer 62. The thickness of the AlN buffer layer 62 is, for example, about 100 nm (for example, not less than 10 nm and not more than 400 nm). A GaN layer may be used as the buffer layer 60. When a GaN layer is used as the buffer layer 60, the thickness of the GaN layer is about 30 nm (for example, 20 nm to 50 nm). The buffer layer 60 may be a mixed crystal such as AlGaN, InGaN, or AlInN.

  When a silicon substrate is used as the substrate 40, it is easy to suppress meltback etching caused by the reaction between silicon and gallium by using AlN, which hardly causes chemical reaction with silicon, as the buffer layer 60 in contact with silicon. When the buffer layer 60 contains In, lattice mismatch with the silicon substrate is suppressed, and dislocation is easily suppressed. When the buffer layer 60 contains In, an In elimination reaction is likely to occur during crystal growth. For this reason, in order to obtain the buffer layer 60 with good flatness, the In composition ratio is preferably 0.5 or less.

  By providing the laminated body 50 with the AlGaN layer 51a, the effect of suppressing meltback etching can be increased. Compressive stress is formed in the AlGaN layer 51a, and tensile stress generated by the difference in thermal expansion coefficient between the nitride semiconductor and the silicon substrate is reduced in the temperature lowering process after crystal growth. Thereby, generation | occurrence | production of a crack can be suppressed.

  As already described, the AlGaN layer 51a may include a plurality of layers (for example, the first to third AlGaN layers 51aa, 51ab, and 51ac). Thereby, the compressive stress formed in the AlGaN layer 51a can be increased. When the AlGaN layer 51a includes a plurality of layers, it is preferable that the Al composition ratio decreases in the upward direction.

  For example, when AlN is used as the buffer layer 60, the Al composition ratio of the plurality of AlGaN layers provided in the AlGaN layer 51a is, for example, a lattice constant difference obtained by dividing the lattice constant of AlN and GaN at equal intervals by the number of layers. Set to The lattice mismatch between AlN and GaN at room temperature is about 2.1%.

  For example, when three AlGaN layers are provided in the AlGaN layer 51a, the lattice constant difference between the AlGaN layers is set to about 0.7%. For example, the Al composition ratio in the first AlGaN layer 51aa is about 0.55. The Al composition ratio in the second AlGaN layer 51ab is, for example, 0.3. The Al composition ratio in the third AlGaN layer 51ac is, for example, 0.15.

  For example, when two AlGaN layers are provided in the AlGaN layer 51a, the lattice constant difference between the AlGaN layers is set to about 1.0%. For example, the Al composition ratio in the first AlGaN layer 51aa is about 0.5. The Al composition ratio in the second AlGaN layer 51ab is, for example, 0.2.

  The difference in Al composition ratio between AlGaN layers is not constant. This is because strain is formed in the AlGaN layer. The lattice mismatch rate at room temperature in the AlGaN layer is calculated by, for example, X-ray diffraction measurement.

  At least one of the first Si-containing layer 51s and the second Si-containing layer 52s may include a SiN layer. At least one of the first Si-containing layer 51s and the second Si-containing layer 52s may be a layer (δ-doping layer) in which a part of GaN is doped with Si at a high concentration.

  By providing the first Si-containing layer 51s, the first GaN layer 51g grows three-dimensionally when the first GaN layer 51g is formed on the first Si-containing layer 51s. In the first Si-containing layer 51s, the Si concentration and thickness fluctuate within a plane (XY plane) perpendicular to the stacking direction. For example, the first GaN layer 51g is likely to grow selectively in a portion having a low Si concentration or a portion having a small thickness. Thereby, the first GaN layer 51g grows three-dimensionally.

  As the first GaN layer 51g grows three-dimensionally, the dislocations 80 generated in the buffer layer 60 bend in a direction parallel to the stacking direction (Z-axis direction). Thereby, the number of dislocations 80 reaching the upper layer (functional layer 15) can be reduced.

  In the region where the growth of the first GaN layer 51g is suppressed by the first Si-containing layer 51s (the region between the protrusions 51gp of the first GaN layer 51g), the dislocation 80 generated in the buffer layer 60 is shielded by the first Si-containing layer 51s. Is done. Thereby, propagation to the upper layer of the dislocation 80 is suppressed. When the coverage of the first Si-containing layer 51s is high, the effect of reducing dislocations 80 increases.

  The first Si-containing layer 51s is in contact with the AlGaN layer 51a. The AlGaN layer 51a and the first GaN layer 51g are close to each other through the first Si-containing layer 51s. As a result, the first GaN layer 51g grows while being affected by the lattice mismatch difference with the AlGaN layer 51a. By providing the lattice mismatch difference, the first GaN layer 51g is more easily grown three-dimensionally, and the dislocation reduction effect is increased. Furthermore, dislocations that occur in a portion where the AlGaN layer 51a and the first GaN layer 51g are close to each other via the first Si-containing layer 51s can be reduced.

  The thickness of the first Si-containing layer 51s is not less than 0.4 atomic layer and not more than 2 atomic layer, for example, 1 atomic layer. If the thickness of the first Si-containing layer 51s is thinner than the 0.4 atomic layer, the three-dimensional growth of the first GaN layer 51g is difficult to occur, and the effect of reducing the dislocations 80 is reduced. If the thickness of the first Si-containing layer 51s is thicker than the diatomic layer, the growth of the first GaN layer 51g becomes difficult.

The thickness of the first Si-containing layer 51s can be estimated by direct observation using a transmission electron microscope image or by secondary ion mass spectrometry (SIMS). In the case of SIMS analysis, the case where the Si concentration in the layer is about 2 × 10 ²⁰ cm ³ corresponds to one atomic layer. This Si concentration corresponds to a Si surface density of about 1 × 10 ¹⁵ cm ² in terms of surface density.

  A second Si-containing layer 52s is provided on the first GaN layer 51g. The first GaN layer 51g includes a convex portion 51gp. The convex part 51gp has a slope 51gs inclined with respect to a plane (XY plane) perpendicular to the stacking direction (Z-axis direction). The inclined surface 51gs is, for example, a facet surface such as a (10-11) surface or a (11-22) surface. The slope 51gs may not be a specific crystal plane. In the convex portion 51gp, the angle between the inclined surface 51gs and the XY plane may change. The convex portion 51gp may have a conical shape or a dome shape.

  A part of the first Si-containing layer 51s is exposed between the protrusions 51gp included in the first GaN layer 51g. A second Si-containing layer 52s is formed on the exposed first Si-containing layer 51s, on the first GaN layer 51g (on the slope 51gs of the convex portion 51gp and on the upper surface (top surface 51gt) of the convex portion 51gp). Is done. By forming the second Si-containing layer 52s on the inclined surface 51gs of the first GaN layer 51g, the dislocation 80 is caused to bend at the interface between the inclined surface 51gs and the second Si-containing layer 52s and propagates to the functional layer 15. Can be reduced.

  When a part of the second Si-containing layer 52s is in contact with the first Si-containing layer 51s, the shielding effect of the dislocation 80 by the Si-containing layer is increased. As a result, the effect of suppressing propagation of dislocations 80 generated in the buffer layer 60 to the upper layer (functional layer 15) is increased.

  The thickness of the second Si-containing layer 52s is preferably 0.2 atomic layer or more and 2 atomic layer or less (for example, 0.5 atomic layer). If the thickness of the second Si-containing layer 52s is smaller than the 0.2 atomic layer, the bending effect or shielding effect of the dislocation 80 on the inclined surface 51gs cannot be sufficiently obtained, and the dislocation density reducing effect is reduced. If the thickness of the second Si-containing layer 52s is thicker than the diatomic layer, the second GaN layer 52g is difficult to grow. As a result, it is difficult to planarize the second GaN layer 52g.

  The thickness of the second Si-containing layer 52s is preferably thinner than the thickness of the first Si-containing layer 51s. When the thickness of the second Si-containing layer 52s is larger than the thickness of the first Si-containing layer 51s, high-density irregularities are formed on the slope 51gs of the convex portion 51gp of the first GaN layer 51g, and the surface flatness is lowered. For this reason, the characteristics of the functional layer 15 are likely to deteriorate.

  The sum of the thickness of the first Si-containing layer 51s and the thickness of the second Si-containing layer 52s is preferably 0.7 atomic layer or more and 2 atomic layers or less. If the sum of the thicknesses is thinner than the 0.7 atomic layer, it is difficult to obtain the bending effect or shielding effect of the dislocation 80 by the Si-containing layer. If the sum of the thicknesses is thicker than the diatomic layer, the formation of irregularities in the GaN layer becomes excessive and the flatness deteriorates. Furthermore, if the sum of the thicknesses is greater than the diatomic layer, cracks are likely to occur due to the formation of tensile stress in the GaN layer due to the formation of irregularities.

  By forming the sufficiently thick second GaN layer 52g on the second Si-containing layer 52s, the upper surface of the second GaN layer 52g becomes flat. The main surface of the functional layer 15 formed on the second GaN layer 52g is flat.

FIG. 9A to FIG. 9C are electron micrograph images illustrating the nitride semiconductor device according to the embodiment.
These drawings are SEM images of three samples in which the first GaN layer 51g is formed on the first Si-containing layer 51s. In these drawings, the shape of the first GaN layer 51g is shown. In these samples, the formation conditions of the layers are different from each other. These figures also show examples of nitride semiconductor wafers.

In the first example S01 shown in FIG. 9A, on the AlGaN layer 51a, the substrate temperature is 1040 ° C., silane (SiH ₄ ) having a concentration of 10 ppm is flowed 350 cc, and ammonia is flowed 20 L / min for 3 minutes. The first Si-containing layer 51s is formed. Thereafter, TMGa is supplied at a flow rate of 56 cc / min and ammonia is supplied at a flow rate of 40 L / min for 5 minutes at a substrate temperature of 1090 ° C., thereby forming the first GaN layer 51 g. The TMGa flow rate of 56 cc / min corresponds to 273 μmol / min. Therefore, in the first example S01, the V / III ratio at the time of forming the first GaN layer 51g is 6500. The thickness of the first Si-containing layer 51s is about 0.4 atomic layer.

  In the second example S02 shown in FIG. 9B, the growth time for forming the first Si-containing layer 51s is 8 minutes. The rest is the same as the first example S01. The thickness of the first Si-containing layer 51s in the second example S02 is about one atomic layer.

  In the third example S03 shown in FIG. 9C, the ammonia flow rate when forming the first GaN layer 51g is 2.5 L / min. The rest is the same as the first example S01. In the third example S03, the V / III ratio at the time of forming the first GaN layer 51g is as low as 490.

  As can be seen from FIG. 9A, in the first example S01, the first GaN layer 51g is an island-shaped crystal. The height tg1 of the convex portion 51gp of the first GaN layer 51g is 150 nm to 200 nm. The diameter (width, that is, the length in the direction facing the XY plane) of the convex portion 51gp of the first GaN layer 51g is about 1.5 μm. In the first example S01, many microcrystals having a height of 50 nm or less are observed.

  As can be seen from FIG. 9B, in the second example S02 (the formation time of the first Si-containing layer 51s is as long as 8 minutes), the height tg1 of the first GaN layer 51g increases to 200 nm to 500 nm. On the other hand, the diameter (width) of the convex portion 51gp of the first GaN layer 51g is reduced to about 0.8 μm. In the second example S02, the above-mentioned microcrystals (microcrystals having a height of 50 nm or less) are not substantially observed.

  Thus, the height tg1 and the diameter (width) of the convex portion 51gp of the first GaN layer 51g can be changed depending on the thickness of the first Si-containing layer 51s. When the growth time of the Si-containing layer 51s is long, that is, when the thickness of the first Si-containing layer 51s is thick, the height tg1 of the convex portion 51gp of the first GaN layer 51g increases.

  As can be seen from FIG. 9C, in the third example S03 (V / III ratio when forming the first GaN layer 51g is as low as 490), the height tg1 of the convex portion 51gp of the first GaN layer 51g is 400 nm. Increase to ˜700 nm. And the area of the slope 51gs increases. The convex portion 51gp has a conical shape or a dome shape. On the other hand, the diameter (width) of the convex portion 51gp of the first GaN layer 51g is about 1.5 μm, which is substantially the same as the first example S01.

  Thus, the convex part 51gp height tg1 of the first GaN layer 51g and the shape of the slope 51gs can be changed by the V / III ratio in the formation of the first GaN layer 51g. When the V / III ratio is low, the height tg1 is high. When the V / III ratio is low, the ratio of the slope 51gs to the entire convex portion 51gp increases.

FIG. 10A to FIG. 10D are graphs illustrating characteristics of the nitride semiconductor device. These drawings show the first GaN layer when the growth time (thickness) of the first Si-containing layer 51s, the V / III ratio, the growth temperature, and the growth rate when the first GaN layer 51g is formed are changed. The example of the height tg1 of the 51g convex part 51gp is represented. These figures also illustrate examples of characteristics of nitride semiconductor wafers.
In this example, the conditions not described below with respect to the first Si-containing layer 51s and the first GaN layer 51g are the same as the conditions described with reference to FIG.

  In these drawings, the vertical axis represents the height tg1 of the convex portion 51gp of the first GaN layer 51g. The horizontal axis of FIG. 10A is the growth time TMs1 (minute) of the first Si-containing layer 51s. The horizontal axis of FIG.10 (b) is Rg1 (V / III) which is V / III ratio at the time of formation of the 1st GaN layer 51g. The horizontal axis of FIG.10 (c) is the growth temperature GTg1 (degreeC) at the time of formation of the 1st GaN layer 51g. The horizontal axis of FIG. 10D is the growth rate GRg1 (nm / min) when the first GaN layer 51g is formed.

  As shown in FIG. 10A, when the growth time TMs1 of the first Si-containing layer 51s is long, the height tg1 of the convex portion 51gp of the first GaN layer 51g increases. For example, when the growth time TMs1 of the first Si-containing layer 51s is 5 minutes, the height tg1 is 300 nm. When the growth time TMs1 is 11 minutes, the height tg1 is 600 nm.

  FIG. 10B shows a change in the height tg1 of the convex portion 51gp of the first GaN layer 51g when the V / III ratio is changed when the first GaN layer 51g is formed. In this experiment, the supply amount of TMGa, which is a group III source gas, is constant at 56 cc / min, and the supply amount of ammonia is changed.

  As shown in FIG. 10B, when the V / III ratio (Rg1 (V / III)) when forming the first GaN layer 51g is low, the height tg1 of the convex portion 51gp of the first GaN layer 51g is large. Become. When the V / III ratio is 3250, the height tg1 is 450 nm. When the V / III ratio is 410, the height tg1 is 1000 nm.

  As shown in FIG. 10C, when the growth temperature GTg1 (substrate temperature) at the time of forming the first GaN layer 51g is low, the height tg1 of the convex portion 51gp of the first GaN layer 51g increases. For example, when the growth temperature GTg1 in forming the first GaN layer 51g is 1050 ° C., the height tg1 is 550 nm. When the growth temperature GTg1 is 1120 ° C., the height tg1 is 210 nm. If the growth temperature GTg1 of the first GaN layer 51g is higher than 1120 ° C., meltback etching is likely to occur, and the crystal is likely to deteriorate. If the growth temperature GTg1 of the first GaN layer 51g is lower than 1000 ° C., pits are likely to be generated, and the crystal is likely to deteriorate. The growth temperature GTg1 of the first GaN layer 51g is preferably 1000 ° C. or higher and 1120 ° C. or lower.

  FIG. 10D shows a change in the height tg1 of the convex portion 51gp of the first GaN layer 51g when the growth rate GRg1 when forming the first GaN layer 51g is changed. In this experiment, the supply amount of TMGa is changed. At this time, the growth time is changed so that the total supply amount of the source gas when forming the first GaN layer 51g is constant. For example, when the flow rate of TMGa is doubled to 112 cc / min, the growth time is halved to 2.5 minutes.

  As shown in FIG. 10D, when the growth rate GRg1 of the first GaN layer 51g is low (slow), the height tg1 of the convex portion 51gp of the first GaN layer 51g increases. For example, when the growth rate GRg1 of the first GaN layer 51g is 19 nm / min, the height tg1 is 550 nm. When the growth rate GRg1 is 48 nm / min, the height tg1 is 250 nm.

  FIG. 11 is a graph illustrating characteristics of the nitride semiconductor device according to the first embodiment. FIG. 11 illustrates the relationship between the height tg1 of the convex portion 51gp of the first GaN layer 51g and the edge dislocation density De in the nitride semiconductor element (and nitride semiconductor wafer).

  The horizontal axis in FIG. 11 is the height tg1 of the convex portion 51gp of the first GaN layer 51g. The height tg1 is the height of the highest convex portion 51gp among the plurality of convex portions 51gp observed in the cross-sectional SEM image. This value corresponds to the largest island height among the plurality of convex portions 51gp observed in the cross-sectional SEM image.

  As described above, the height tg1 of the protrusion 51gp of the first GaN layer 51g corresponds to the growth time TMs1 (corresponding to the thickness of the first Si-containing layer 51s) of the first Si-containing layer 51s and the formation of the first GaN layer 51g. The V / III ratio (Rg1 (V / III)), the growth temperature GTg1 in the formation of the first GaN layer 51g, and the growth rate GRg1 in the formation of the first GaN layer 51g were changed. Specifically, the height tg1 is increased by increasing the growth time TMs1 of the first Si-containing layer 51s (thickening the first Si-containing layer 51s). The height tg1 is increased by decreasing the ammonia supply amount (V / III ratio) when forming the first GaN layer 51g. By reducing the growth temperature GTg1 when forming the first GaN layer 51g, the height tg1 increases. The height tg1 is increased by decreasing (slowing) the growth rate GRg1 of the first GaN layer 51g.

  As shown in FIG. 11, when the height tg1 of the convex portion 51gp of the first GaN layer 51g is 0 nm, the edge dislocation density De is high. The case where the height tg1 is 0 nm corresponds to the case where the first GaN layer 51g is flat. On the other hand, also when the height tg1 is larger than 1000 nm, the edge dislocation density De is high.

On the other hand, when the height tg1 of the convex portion 51gp of the first GaN layer 51g is 100 nm or more and 1000 nm or less, the edge dislocation density De is low. When the height tg1 is 100 nm or more and 1000 nm or less, the edge dislocation density De is 4 × 10 ⁸ (/ cm ² ) or less (eg, 3 × 10 ⁸ (/ cm ² ) or more and 4 × 10 ⁸ (/ cm ^2). ) Below).

  When the height tg1 of the convex portion 51gp is lower than 100 nm, the slope 51gs is not sufficiently formed, and the ratio of the flat surface (top surface 51gt) perpendicular to the stacking direction to the crystal surface is large. For this reason, it is considered that the bending effect or shielding effect of the dislocation 80 by the second Si-containing layer 52s provided on the inclined surface 51gs is not sufficiently obtained. When the height tg1 of the convex portion 51gp is lower than 100 nm, since the volume (surface area) of the crystal of the first GaN layer 51g is small, the propagation direction of the dislocation 80 does not change in the crystal, and the first GaN layer 51g It is considered that the effect of reducing dislocation is reduced.

  When the height tg1 of the convex portion 51gp is higher than 1000 nm, adjacent convex portions 51gp are easily united, and the region where the first Si-containing layer 51s and the second Si-containing layer 52s are in contact with each other is reduced. As a result, it is considered that the shielding effect of dislocations 80 generated in the buffer layer 60 is reduced and the dislocation density is increased.

  When unevenness having a height tg1 larger than 1000 nm is formed, it is difficult to planarize the second GaN layer 52g, and pits are easily formed on the surface of the second GaN layer 52g. As a result of the experiment, it was found that when the thickness of the second GaN layer 52g is about twice or more the height tg1 of the convex portion 51gp of the first GaN layer 51g, a flat second GaN layer 52g is obtained. In the present embodiment, the thickness of the second GaN layer 52g is, for example, about 2 μm. The height tg1 of the convex portion 51gp of the first GaN layer 51g is ½ or less of the thickness of the second GaN layer 52g.

  In a flat layer, a region having an area of 90% or more of the surface area of the layer is parallel to the main surface of the layer.

  Thus, the height tg1 of the convex portion 51gp of the first GaN layer 51g is preferably 100 nm or more and 1000 nm or less. In this case, the dislocation density is effectively reduced. The height tg1 is more preferably not less than 300 nm and not more than 800 nm.

  FIG. 12 is a graph illustrating characteristics of the nitride semiconductor device according to the first embodiment. FIG. 12 illustrates the experimental results regarding the change in the edge dislocation density De when the growth time of the first Si-containing layer 51s is changed. The horizontal axis represents the growth time TMs1 of the first Si-containing layer 51s and corresponds to the thickness of the first Si-containing layer 51s. In this experiment, the growth time TMs2 of the second Si-containing layer 52s is 3 minutes. The first GaN layer 51g is formed at a substrate temperature of 1090 ° C., in a mixed atmosphere with a hydrogen / nitrogen ratio of 2: 1, with a TMGa flow rate of 56 cc / min and an ammonia flow rate of 40 L / min. The growth time of the first GaN layer 51g is 5 minutes.

  As can be seen from FIG. 12, the edge dislocation density De decreases when the growth time TMs1 of the first Si-containing layer 51s is 3 minutes or more and 16 minutes or less. When the growth time TMs1 is shorter than 3 minutes or longer than 16 minutes, the edge dislocation density De is high. When the growth time TMs1 of the first Si-containing layer 51s is 17 minutes, pits are formed on the surface of the functional layer 15, and sufficient planarization cannot be performed.

  In this experiment, the time when the growth time TMs1 of the first Si-containing layer 51s is 8 minutes corresponds to the condition that the thickness of the first Si-containing layer 51s is one atomic layer.

  From the result of FIG. 12, it can be seen that a low edge dislocation density De is obtained when the thickness of the first Si-containing layer 51s is not less than 0.4 atomic layer and not more than 2 atomic layer. When the thickness of the first Si-containing layer 51s is thinner than the 0.4 atomic layer, the dislocation density is increased. This is presumably because three-dimensional growth of the first GaN layer 51g hardly occurs and the effect of reducing the dislocation density is small. When the thickness of the first Si-containing layer 51s is thicker than 2 atoms, the dislocation density is increased. This is considered because the first GaN layer 51g does not substantially grow.

  The thicknesses of the first Si-containing layer 51s and the second Si-containing layer 52s can be estimated by direct observation with a TEM image or SIMS analysis.

  In the case of SIMS analysis, the Si concentration may be observed to expand in the thickness (depth) direction depending on measurement conditions such as the sputtering rate. In this case, for example, with respect to the maximum value (maximum value) of the Si concentration in the region corresponding to the Si-containing layer, the sum of the Si concentrations up to the region where the Si concentration is reduced to a value of 10% (the thickness of the Si atoms) (Integral value of direction) can be regarded as the number of Si atoms per unit area (Si surface density) contained in the Si-containing layer.

  The thickness of the Si-containing layer can be estimated using the sum of the Si concentrations (Si surface density). That is, it can be estimated as the thickness of the GaN layer substituted with Si when Si atoms in the Si-containing layer are uniformly substituted with Ga atoms (Group III atoms) in the GaN layer.

  In the present specification, the thickness of the Si-containing layer when the number of Si atoms in the Si-containing layer is a number that replaces Ga atoms corresponding to one layer of the GaN layer is defined as one atomic layer.

The surface density of Ga atoms (Group III atoms) on the (0001) plane in the GaN layer is about 1 × 10 ¹⁵ (/ cm ² ). Therefore, when the surface density of Si in the film is about 1 × 10 ¹⁵ (/ cm ² ), this corresponds to the thickness of the first Si-containing layer 51s and the second Si-containing layer 52s being one atomic layer.

In SIMS analysis, for example, when the peak value of the Si concentration is 2 × 10 ²⁰ (/ cm ³ ) and has a width of 200 nm, when converted to the surface density, it is about 1 × 10 ¹⁵ (/ cm ² ). This corresponds to the Si surface density.

That is, the case where the Si concentration in the film is about 2 × 10 ²⁰ (/ cm ³ ) corresponds to the thickness of the Si-containing layer being one atomic layer. Therefore, “the dislocation density is reduced when the thickness of the first Si-containing layer 51s is not less than 0.4 atomic layer and not more than 2 atomic layers” means that the Si concentration in the first Si-containing layer 51s is 7 × 10 ¹⁹ / cm. ^The dislocation density is reduced when it is ³ or more and 4.0 × 10 ²⁰ (/ cm ³ ) or less ”, and the dislocation density becomes low. And when Si surface density in a film is 3.5 * 10 < ¹⁴ > (/ cm < ² >) or more and 2.0 * 10 < ¹⁵ > (/ cm < ² >) or less, a dislocation density becomes low.

  When the growth time TMs1 of the first Si-containing layer 51s is changed, the Si concentration in the first Si-containing layer 51s changes. The relationship between the Si concentration in the first Si-containing layer 51s and the dislocation density will be described for the sample in which the Si concentration in the first Si-containing layer 51s is changed by changing the growth time TMs1 of the first Si-containing layer 51s.

FIG. 13A and FIG. 13B are graphs illustrating characteristics of the nitride semiconductor device according to the first embodiment.
These figures show the relationship between the Si concentration in the first Si-containing layer 51s and the edge dislocation density De for the sample shown in FIG. The horizontal axis of FIG. 13A is the Si concentration CSv1 (/ cm ³ ) in the first Si-containing layer 51s. The horizontal axis of FIG.13 (b) is Si surface density CSa1 (/ cm < ² >) in the 1st Si content layer 51s. CSv1 is substantially CSa1 × 2 × 10 ⁵ .

As can be seen from FIG. 13A, when the Si concentration CSv1 in the first Si-containing layer 51s is 7 × 10 ¹⁹ or more and 4 × 10 ²⁰ (/ cm ³ ), a low edge dislocation density De is obtained.

As can be seen from FIG. 13B, a low edge dislocation density De is obtained when the Si surface density CSa1 in the first Si-containing layer 51s is 3.5 × 10 ¹⁴ or more and 2 × 10 ¹⁵ (/ cm ² ). .

  FIG. 14 is a graph illustrating characteristics of the nitride semiconductor device according to the first embodiment. FIG. 14 illustrates the experimental result of the edge dislocation density De when the growth time of the second Si-containing layer 52s is changed. The horizontal axis represents the growth time TMs2 of the second Si-containing layer 52s and corresponds to the thickness of the second Si-containing layer 52s. In this experiment, the growth time TMs1 of the first Si-containing layer 51s is 8 minutes. The first GaN layer 51g is formed at a substrate temperature of 1090 ° C. and a hydrogen / nitrogen ratio of 2: 1 with a TMGa flow rate of 56 cc / min and an ammonia flow rate of 40 L / min. The growth time of the first GaN layer 51g is 5 minutes.

  As can be seen from FIG. 14, the edge dislocation density De decreases when the growth time TMs2 of the second Si-containing layer 52s is 3 minutes or more and 12 minutes or less. When the growth time TMs2 is shorter than 3 minutes or longer than 12 minutes, the edge dislocation density De is high.

  When the growth time TMs2 of the second Si-containing layer 52s is 8 minutes, the thickness of the second Si-containing layer 52s corresponds to one atomic layer.

  From the result of FIG. 14, when the thickness of the second Si-containing layer 52s is not less than 0.4 atomic layer and not more than 1.5 atomic layer, a low edge dislocation density De is obtained. When the thickness of the second Si-containing layer 52s is thinner than the 0.4 atomic layer, the dislocation bending effect or the shielding effect in the second Si-containing layer 52s cannot be sufficiently obtained. When the thickness of the second Si-containing layer 52s is thicker than the 1.5 atomic layer, the growth of the second GaN layer 52g on the second Si-containing layer 52s is inhibited, and the bending effect of dislocation in the second Si-containing layer 52s or The shielding effect cannot be obtained sufficiently. Further, the surface flatness of the second GaN layer 52g is lowered.

  As can be seen from the results shown in FIG. 14, the dislocation density is likely to be reduced when the thickness of the second Si-containing layer 52s is equal to or less than the thickness of the first Si-containing layer 51s. If the thickness of the second Si-containing layer 52s is larger than the thickness of the first Si-containing layer 51s, the second GaN layer 52g is excessively uneven, and the flatness tends to deteriorate. For this reason, the dislocation density increases. Furthermore, for example, tensile stress is generated due to excessive unevenness, and cracks are likely to increase.

  When the growth time TMs2 of the second Si-containing layer 52s is changed, the Si concentration in the second Si-containing layer 52s changes. The relationship between the Si concentration in the second Si-containing layer 52s and the dislocation density will be described for a sample in which the Si concentration in the second Si-containing layer 52s is changed by changing the growth time TMs2 of the second Si-containing layer 52s.

FIG. 15A and FIG. 15B are graphs illustrating characteristics of the nitride semiconductor device according to the first embodiment.
These figures show the relationship between the Si concentration in the second Si-containing layer 52s and the edge dislocation density De for the sample shown in FIG. The horizontal axis of FIG. 15A is the Si concentration CSv2 (/ cm ³ ) in the second Si-containing layer 52s. The horizontal axis of FIG.15 (b) is Si surface density CSa2 (/ cm < ² >) in the ^2nd Si content layer 52s. CSv2 is substantially CSa2 × 2 × 10 ⁵ . In these drawings, the Si concentration CSv1 in the first Si-containing layer 51s is 2 × 10 ²⁰ (/ cm ³ ), and the Si surface density CSa1 in the first Si-containing layer 51s is 1 × 10 ¹⁵ (/ cm ² ).

As can be seen from FIG. 15A, when the Si concentration CSv2 in the second Si-containing layer 52s is 7 × 10 ¹⁹ or more and 3 × 10 ²⁰ (/ cm ³ ) or less, a low edge dislocation density De is obtained.

As can be seen from FIG. 15B, when the Si surface density CSa2 in the second Si-containing layer 52s is not less than 3.5 × 10 ^{14 and not} more than 1.5 × 10 ¹⁵ (/ cm ² ), the low edge dislocation density De is low. Is obtained.

  The Si concentration CSv2 in the second Si-containing layer 52s is preferably not more than the Si concentration CSv1 in the first Si-containing layer 51s. In this case, as shown in FIG. 15A, the dislocation density is easily reduced.

  The Si surface density CSa2 in the second Si-containing layer 52s is preferably equal to or lower than the Si surface density CSa1 in the first Si-containing layer 51s. In this case, as shown in FIG. 15B, the dislocation density tends to be small.

  When the Si concentration CSv2 in the second Si-containing layer 52s is higher than the Si concentration CSv1 in the first Si-containing layer 51s, the unevenness is excessively formed in the second GaN layer 52g, and the flatness is likely to deteriorate. For this reason, the dislocation density increases. Furthermore, for example, tensile stress is generated due to excessive unevenness, and cracks are likely to increase.

  FIG. 16 is a graph illustrating characteristics of the nitride semiconductor device according to the first embodiment. FIG. 16 illustrates the relationship between the total thickness of the first Si-containing layer 51s and the second Si-containing layer 52s and the edge dislocation density De. The horizontal axis represents the total thickness ts, and the unit is an atomic layer.

  As can be seen from FIG. 16, when the total thickness ts of the first Si-containing layer 51s and the second Si-containing layer 52s is 0.7 atomic layer or more and 2 atomic layers, the low edge dislocation density De is low. can get. When the total thickness ts is thinner than 0.7 atomic layers or thicker than two atomic layers, the dislocation density is high. When the total thickness ts is thinner than the 0.7 atomic layer, the dislocation bending effect or shielding effect by the Si-containing layer is lowered. If the total thickness ts is thicker than the diatomic layer, the formation of irregularities in the GaN layer becomes excessive and the flatness deteriorates. This increases the dislocation density. Furthermore, if the total thickness ts is thicker than the diatomic layer, cracks are likely to occur due to the formation of tensile stress in the GaN layer due to the formation of irregularities, and the crystal quality deteriorates.

When the total thickness ts of the thickness of the first Si-containing layer 51s and the thickness of the second Si-containing layer 52s is 0.7 atomic layer, the sum of the Si concentrations of the first Si-containing layer 51s and the second Si-containing layer 52s Corresponds to 1.5 × 10 ²⁰ / cm ³ . When the total thickness ts is a diatomic layer, the sum of the Si concentrations of the first Si-containing layer 51s and the second Si-containing layer 52s corresponds to 4.0 × 10 ²⁰ / cm ³ . The sum of the Si concentrations of the first Si-containing layer 51 s and the second Si-containing layer 52 s is preferably 1.5 × 10 ²⁰ / cm ³ or more and 4.0 × 10 ²⁰ / cm ³ or less.

When the total thickness ts is 0.7 atomic layer, the sum of the Si surface densities of the first Si-containing layer 51s and the second Si-containing layer 52s corresponds to 7.5 × 10 ¹⁴ / cm ² . When the total thickness ts is a diatomic layer, the sum of the Si surface densities of the first Si-containing layer 51s and the second Si-containing layer 52s corresponds to 2.0 × 10 ¹⁵ / cm ² . The sum of the Si surface densities of the first Si-containing layer 51s and the second Si-containing layer 52s is preferably 7.5 × 10 ¹⁴ / cm ² or more and 2.0 × 10 ¹⁵ / cm ² or less.

FIG. 17 is a graph illustrating the nitride semiconductor device according to the first embodiment.
FIG. 17 shows an example of the SIMS analysis result of the nitride semiconductor device 110 (or the nitride semiconductor wafer 210) according to this embodiment. In this example, measurement is performed at intervals of 5 nm along the depth (stacking direction). The horizontal axis in FIG. 17 is the depth Zd (corresponding to the position in the Z-axis direction). The vertical axis represents the Si concentration CS (atoms / cm ³ ). In this example, the growth time TMs1 of the first Si-containing layer 51s is 8 minutes. This condition corresponds to the condition that the Si surface density in the first Si-containing layer 51s is 1.2 × 10 ¹⁵ / cm ² . The growth time TMs2 of the second Si-containing layer 52s is 3 minutes. This condition corresponds to the condition that the Si surface density in the second Si-containing layer 52s is 3.8 × 10 ¹⁴ / cm ² .

  As can be seen from FIG. 17, three levels of Si peaks are observed in the range of the stacked body 50. For example, the Si concentration profile in the stacked body 50 includes first to seventh portions p1 to p7. The first to seventh portions p1 to p7 are stacked along the Z-axis direction. The second portion p2 is provided on the upper side of the first portion p1.

The first portion p1 has a first concentration of Si concentration of 7 × 10 ¹⁹ / cm ³ or more and 4 × 10 ²⁰ / cm ³ or less.

The second portion p2 has a second concentration in which the Si concentration is lower than the first concentration. The second concentration is, for example, less than 2 × 10 ¹⁷ / cm ³ . In the second portion p2, the Si concentration is relatively constant.

The third portion p3 is provided between the first portion p1 and the second portion p2. The third portion p3 has a third concentration where the Si concentration is between the first concentration and the second concentration. The third concentration is, for example, 3 × 10 ¹⁸ / cm ³ or more and 5 × 10 ¹⁹ / cm ³ . In the third portion p3, the Si concentration is relatively constant.

The fourth portion p4 is provided between the third portion p3 and the second portion p2. The fourth portion p4 has a fourth concentration where the Si concentration is between the third concentration and the second concentration. The fourth concentration is, for example, 2 × 10 ¹⁷ / cm ³ or more and 2 × 10 ¹⁸ / cm ³ or less. In the fourth portion p4, the Si concentration is relatively constant.

  The fifth part p5 is provided between the first part p1 and the third part p3. The rate of change with respect to the thickness of the Si concentration in the fifth portion p5 is higher than the rate of change with respect to the thickness of the Si concentration in the third portion p3. In the fifth portion p5, the Si concentration changes abruptly.

  The sixth part p6 is provided between the third part p3 and the fourth part p4. The rate of change with respect to the thickness of the Si concentration in the sixth portion p6 is higher than the rate of change with respect to the thickness of the Si concentration in the third portion p3. The rate of change with respect to the thickness of the Si concentration in the sixth portion p6 is higher than the rate of change with respect to the Si concentration in the fourth portion p4. In the sixth portion p6, the Si concentration changes abruptly.

  The seventh portion p7 is provided between the fourth portion p4 and the second portion p2. The rate of change with respect to the thickness of the Si concentration in the seventh portion p7 is higher than the rate of change with respect to the thickness of the Si concentration in the fourth portion p4. The rate of change with respect to the thickness of the Si concentration in the seventh portion p7 is higher than the rate of change with respect to the Si concentration in the second portion p2.

In the first portion p1, the Si concentration peak width (width in the thickness direction) is narrow. The first portion p1 corresponds to the first Si-containing layer 51s. At least a part of the fifth portion p5 is further included in the first Si-containing layer 51s.
In this example, the peak (maximum value) of the Si concentration in the first portion p1 is 2.8 × 10 ²⁰ / cm ³ . The peak width until the Si concentration is reduced to 10% of the peak value is about 160 nm. The total Si concentration in this region (the integrated value of the Si concentration in the thickness direction) is 1.2 × 10 ¹⁵ / cm ² , and corresponds to the Si surface density of the first Si-containing layer 51s.

  The thickness (width) of the first portion p1 is, for example, not less than 1 nm and not more than 200 nm. If the thickness of the first portion p1 is smaller than 1 nm, the three-dimensional growth of the first GaN layer 51g does not occur sufficiently. When the thickness of the first portion p1 is greater than 200 nm, the growth of the first GaN layer 51g is hindered, the area of the slope is reduced, and the effect of reducing the dislocation density cannot be sufficiently obtained.

The third portion p3 and the sixth portion p6 correspond to the first GaN layer 51g and the second Si-containing layer 52s. The Si concentration in the second Si-containing layer 52s is 8.0 × 10 ¹⁸ / cm ³ . The first GaN layer 51g includes a convex portion 51gp, and the second Si-containing layer 52s is provided on the convex portion 51gp. As described above, the diameter of the convex portion 51gp is, for example, not less than 50 nm and not more than 1500 nm. In SIMS analysis, the analysis area is larger than the size (area) of the convex portion 51gp. For this reason, the Si concentration by SIMS analysis is detected as an average value of a range including the plurality of convex portions 51gp (a range of the second GaN layer 52g, the second Si-containing layer 52s, and the first GaN layer 51g). For this reason, in the Si concentration profile, the spread occurs in the thickness (depth) direction, the peak value becomes smaller than the actual Si concentration, and the third portion p3 and the sixth portion p6 are generated.

In this example, the peak of the Si concentration in the third portion p3 is about 8.0 × 10 ¹⁸ / cm ³ , and the width of the third portion p3 and the sixth portion p6 (the Si concentration is 10% of the peak value). (Corresponding to the width of the peak until reduced to about 500 nm). The total Si concentration in this region (the integrated value of the Si concentration in the thickness direction) is 3.8 × 10 ¹⁴ / cm ² , and corresponds to the Si surface density of the second Si-containing layer 52s.

  The thickness (width) of the third portion p3 is, for example, not less than 100 nm and not more than 1000 nm. The case where the thickness of the third portion p3 is smaller than 100 nm corresponds to the case where the height of the first GaN layer 51g is 100 nm or less. At this time, the formation of the slope is insufficient, and the effect of reducing the dislocation density is reduced. The case where the thickness of the third portion p3 is thicker than 1000 nm corresponds to the case where the height of the first GaN layer 51g is 1000 nm or less. At this time, the flatness of the second GaN layer 51g tends to deteriorate.

  For example, the fourth portion p4, the seventh portion p7, and the second portion p2 correspond to the second GaN layer 52g. It is considered that Si diffuses into a part (a part on the lower side) of the second GaN layer 52g from at least one of the first Si-containing layer 51s and the second Si-containing layer 52s. This Si diffusion region is considered to correspond to the fourth portion p4.

  The thickness of the fourth portion p4 is, for example, not less than 300 nm and not more than 2500 nm. When the thickness of the fourth portion p4 is smaller than 300 nm, the dislocation bending effect or the shielding effect in the second Si-containing layer 52s cannot be sufficiently obtained. When the thickness of the fourth portion p4 is thicker than 2500 nm, the flatness of the second GaN layer 51g tends to be lowered.

  For example, in the SIMS analysis, the presence of the first Si-containing layer 51s can be determined by the presence of the first portion p1.

  Since the first GaN layer 51g including the convex portion 51gp is observed in the SEM observation or the TEM observation, the presence of the second Si-containing layer 52s can be determined. Since the third portion p3 and the fourth portion p4 are generated in the SIMS analysis, the presence of the second Si-containing layer 52s can be determined.

FIG. 18A and FIG. 18B are graphs illustrating the nitride semiconductor device of the reference example.
18A and 18B show examples of SIMS analysis results of the nitride semiconductor elements (or nitride semiconductor wafers) of the first reference example and the second reference example, respectively.
In the first reference example, a GaN layer is provided instead of the AlGaN layer 51a of the stacked body 50, and a first Si-containing layer 51s is provided on the GaN layer. A first GaN layer 51g including a protrusion 51gp is provided thereon. A second GaN layer 52g is provided thereon. That is, the second Si-containing layer 52s is not provided.

  On the other hand, in the second reference example, a plurality of flat GaN layers and flat Si-containing layers are alternately stacked. In this example, the number of Si-containing layers is four.

  As shown in FIG. 18A, in the first reference example in which the second Si-containing layer 52s is not provided, the Si concentration peak has two steps.

  As shown in FIG. 18B, when a Si-containing layer is provided on a flat GaN layer, a sharp peak of Si concentration is observed. The peak of the Si concentration is one step.

  On the other hand, as already described, in the nitride semiconductor device 110 and the nitride semiconductor wafer 210 according to this embodiment, a three-stage peak is observed in the Si concentration.

FIG. 19 is a schematic cross-sectional view illustrating another nitride semiconductor element according to the first embodiment.
As shown in FIG. 19, in another nitride semiconductor device 111 and nitride semiconductor wafer 211 according to the present embodiment, an n-type n-GaN layer 51n is used as the first GaN layer 51g. Other configurations are the same as those of the nitride semiconductor device 110 and the nitride semiconductor wafer 210.

  The nitride semiconductor element 111 and the nitride semiconductor wafer 211 can also provide a nitride semiconductor element and a nitride semiconductor wafer with few dislocations.

Hereinafter, experimental results will be described.
In the n-GaN layer 51n, for example, in a mixed atmosphere with a substrate temperature of 1090 ° C. and a hydrogen / nitrogen ratio of 2: 1, TMGa has a flow rate of 56 cc / min, ammonia has a flow rate of 40 L / min, and a concentration of 10 ppm silane ( SiH ₄ ) is supplied at a flow rate of 56 cc / min for 5 minutes. The Si concentration in the n-GaN layer 51n is, for example, 5 × 10 ¹⁸ (/ cm ³ ). In this example, the n-GaN layer 51n is an island-shaped crystal. The n-GaN layer 51n may be continuous. The n-GaN layer 51n includes a convex portion 51gp. The convex portion 51gp of the n-GaN layer 51n has a slope 51gs inclined with respect to the XY plane. The height tg1 of the convex portion 51gp of the n-GaN layer 51n is, for example, about 500 nm. The method for manufacturing the other layers is the same as the manufacturing method described for the nitride semiconductor device 110.

The edge dislocation density De in the nitride semiconductor element 111 is 2.1 × 10 ⁸ (/ cm ² ), and the edge dislocation density in the nitride semiconductor element 110 (2.8 × 10 ⁸ (/ cm ² )). The value is even lower than. In the configuration in which the n-GaN layer 51n is provided, the dislocation density is reduced to about 75% compared to the configuration in which the first GaN layer 51g is provided.

  As a result of examining the shape of the n-GaN layer 51n by the same evaluation as that described with reference to FIGS. 9A to 9C, the n-GaN layer 51n is not doped with an n-type impurity (Si). Compared with the case, the height of the convex portion increases, and the area of the slope increases. This is probably because the formation of facets was promoted by doping with n-type impurities. The area of the second Si-containing layer 52s formed on the inclined surface 51gs of the convex portion 51gp of the n-GaN layer 51n is increased, so that the dislocation shielding effect or bending effect is increased and the dislocation is reduced.

The n-type impurity concentration in the n-GaN layer 51n is preferably 1.0 × 10 ¹⁷ (/ cm ³ ) or more and 1.0 × 10 ¹⁹ (/ cm ³ ) or less. The n-type impurity concentration in the n-GaN layer 51n is more preferably 5.0 × 10 ¹⁷ (/ cm ³ ) or more and 6.0 × 10 ¹⁸ (/ cm ³ ) or less. When the n-type impurity concentration in the n-GaN layer 51n is lower than 1.0 × 10 ¹⁷ (/ cm ³ ), facet formation is not sufficient, and the effect of reducing the dislocation density in the second Si-containing layer 52s is achieved. Decrease. When the n-type impurity concentration in the n-GaN layer 51n is higher than 1.0 × 10 ¹⁹ (/ cm ³ ), the growth of the n-GaN layer 51n is inhibited by the n-type impurity, and the n-GaN layer 51n The area of the slope 51gs of the convex portion 51gp is reduced, and the effect of reducing the dislocation density is reduced.

  The height tg1 of the convex portion 51gp of the n-GaN layer 51n is preferably 100 nm or more and 1000 nm or less. In this case, the dislocation density is effectively reduced. The height tg1 is more preferably not less than 300 nm and not more than 800 nm.

  When the height tg1 of the convex portion 51gp is lower than 100 nm, the slope 51gs is not sufficiently formed, and the ratio of the flat surface (top surface 51gt) perpendicular to the stacking direction to the crystal surface is large. For this reason, the bending effect or shielding effect of the dislocations 80 by the second Si-containing layer 52s provided on the inclined surface 51gs cannot be sufficiently obtained. Moreover, since the volume (surface area) of the crystal of the n-GaN layer 51n is small, the propagation direction of the dislocation 80 does not change in the crystal, and the dislocation reduction effect in the n-GaN layer 51n is reduced.

  When the height tg1 of the convex portion 51gp is higher than 1000 nm, adjacent convex portions 51gp are easily united, and the region where the first Si-containing layer 51s and the second Si-containing layer 52s are in contact with each other is reduced. As a result, it is considered that the shielding effect of dislocations 80 generated in the buffer layer 60 is reduced and the dislocation density is increased.

(Second Embodiment)
FIG. 20 is a schematic cross-sectional view illustrating the nitride semiconductor device according to the second embodiment.
As shown in FIG. 20, the nitride semiconductor device 120 according to this embodiment includes a buffer layer 60, a stacked intermediate layer 70, a stacked body 50, and a functional layer 15. A stacked body 50 is provided on the buffer layer 60. The stacked intermediate layer 70 is provided between the buffer layer 60 and the stacked body 50. The functional layer 15 is provided on the stacked body 50. The nitride semiconductor wafer 220 according to this embodiment includes a substrate 40, a buffer layer 60, a stacked intermediate layer 70, and a stacked body 50. The nitride semiconductor wafer 220 may further include a functional layer 15. The configuration described in regard to the first embodiment can be applied to each of the substrate 40, the buffer layer 60, the stacked body 50, and the functional layer 15. Hereinafter, the laminated intermediate layer 70 will be described.

  In this example, the laminated intermediate layer 70 includes a first intermediate layer 70a and a second intermediate layer 70b. The second intermediate layer 70b is provided on the first intermediate layer 70a.

  The first intermediate layer 70a includes a first AlGaN intermediate layer 71a, a first GaN intermediate layer 72a, and a first AlN intermediate layer 73a. The first GaN intermediate layer 72a is provided on the first AlGaN intermediate layer 71a. The first AlN intermediate layer 73a is provided on the first GaN intermediate layer 72a.

  The second intermediate layer 70b includes a second AlGaN intermediate layer 71b, a second GaN intermediate layer 72b, and a second AlN intermediate layer 73b. The second GaN intermediate layer 72b is provided on the second AlGaN intermediate layer 71b. The second AlN intermediate layer 73b is provided on the second GaN intermediate layer 72b.

  In this example, a configuration including an AlGaN intermediate layer, a GaN intermediate layer, and an AlN intermediate layer is repeatedly stacked twice. The number of repetitions may be one time or three or more times.

  In the present embodiment, in the first intermediate layer 70a, the lattice spacing (corresponding to the lattice spacing of the a-axis in this example) in the direction perpendicular to the stacking direction (Z-axis direction) is the first GaN intermediate layer 72a. The largest value is abruptly reduced at the first AlN intermediate layer 73a. In the second intermediate layer 70b, the lattice spacing in the direction perpendicular to the stacking direction (Z-axis direction) (corresponding to the lattice spacing of the a-axis in this example) is the largest in the second GaN intermediate layer 72b, and the second AlN The intermediate layer 73b decreases rapidly.

  In this specification, an unstrained lattice spacing of a nitride semiconductor is defined as “lattice constant”. The actual lattice length of the formed nitride semiconductor layer is defined as “lattice spacing”. The lattice constant is, for example, a physical property constant. The lattice spacing is, for example, the actual length of the lattice in the nitride semiconductor layer included in the formed nitride semiconductor element. The lattice spacing is obtained from, for example, X-ray diffraction measurement.

The first AlGaN intermediate layer 71a is formed on the buffer layer 60 (for example, the AlN buffer layer 62). The formation temperature of the first AlGaN intermediate layer 71a is, for example, about 1040 ° C. AlGaN is formed so as to be lattice-matched to the lattice constant of AlN in a thin state, that is, in the early stage of growth, and grows while receiving compressive strain. The strain gradually relaxes as the growth of AlGaN progresses, and AlGaN approaches the lattice spacing of Al _X Ga _1-X N in a state where it is not strained.

  A first GaN intermediate layer 72a having a lattice constant larger than that of the first AlGaN intermediate layer 71a is formed on the first AlGaN intermediate layer 71a. The formation temperature of the first GaN intermediate layer 72a is, for example, about 1090 ° C. The thickness of the first GaN intermediate layer 72a is, for example, about 300 nm. The first GaN intermediate layer 72a is formed so as to lattice match with the lattice constant of AlGaN at the initial stage of growth, and grows while receiving compressive strain. Then, as the growth of GaN progresses, the strain gradually relaxes, and the lattice constant of GaN approaches the lattice constant of GaN that is not subjected to strain.

  Further, a first AlN intermediate layer 73a is formed on the first GaN intermediate layer 72a. The thickness of the first AlN intermediate layer 73a is, for example, about 12 nm. The crystal growth temperature of the first AlN intermediate layer 73a is preferably 500 ° C. or higher and 1050 ° C. or lower, for example. The formation temperature of the first AlN intermediate layer 73a is, for example, 800 ° C. Therefore, the first AlN intermediate layer 73a is easily lattice-relaxed. This makes it difficult to receive tensile strain from the first GaN intermediate layer 72a serving as the base from the initial stage of formation of the first AlN intermediate layer 73a. As a result, the first AlN intermediate layer 73a can be formed so as to reduce the influence of strain from the first GaN intermediate layer 72a serving as a base. Thus, the lattice-relaxed first AlN intermediate layer 73a is formed on the first GaN intermediate layer 72a.

  Subsequently, a second AlGaN intermediate layer 71b is formed on the first AlN intermediate layer 73a. The Al composition ratio (the ratio of Al in the group III element) in the second AlGaN intermediate layer 71b is less than or equal to the relaxation rate α of the first AlN intermediate layer 73a.

  The relaxation rate α is the absolute value of the difference between the lattice spacing dg of the first axis (eg, a axis) of unstrained GaN and the lattice spacing da of the first axis (eg, a axis) of unstrained AlN. This is the ratio of the difference between the lattice spacing dg of the first axis (for example, the a axis) of unstrained GaN and the actual lattice spacing Da of the first axis (for example, the a axis) of the first AlN intermediate layer 73a. The first axis is a stacking direction (one axis perpendicular to the Z-axis direction).

  The thickness of the second AlGaN intermediate layer 71b is preferably not less than 5 nm and not more than 100 nm, for example. If the thickness of the second AlGaN intermediate layer 71b is less than 5 nm, it is difficult to obtain the effect of suppressing the occurrence of cracks and the effect of reducing dislocations. When the thickness of the second AlGaN intermediate layer 71b is thicker than 100 nm, the effect of reducing dislocation is saturated. Furthermore, cracks are likely to occur. The thickness of the second AlGaN intermediate layer 71b is more preferably less than 50 nm. By setting the thickness of the second AlGaN intermediate layer 71b to less than 50 nm, the dislocation density can be effectively reduced. The thickness of the second AlGaN intermediate layer 71b is, for example, about 25 nm.

  When the formation temperature of the second AlGaN intermediate layer 71b is higher than the formation temperature of the first AlN intermediate layer 73a and the difference is 80 ° C. or more, the effect of growing so as to lattice match with the lattice constant of AlN can be obtained. Furthermore, the effect of reducing dislocations can be obtained more greatly. The formation temperature of the second AlGaN intermediate layer 71b is, for example, about 1120 ° C.

  A second GaN intermediate layer 72b is formed on the second AlGaN intermediate layer 71b. A configuration similar to that of the first GaN intermediate layer 72a can be applied to the second GaN intermediate layer 72b.

  Further, a second AlN intermediate layer 73b is formed on the second GaN intermediate layer 72b. A configuration similar to that of the first AlN intermediate layer 73a can be applied to the second AlN intermediate layer 73b.

  An example of a method for manufacturing the nitride semiconductor device 120 (and the nitride semiconductor wafer 220) according to this embodiment will be described.

The substrate 40 is heated to 1080 ° C., and in a mixed atmosphere where the ratio of hydrogen and nitrogen is 2: 1, trimethylaluminum (TMAl) is supplied at a flow rate of 50 cc / min, and ammonia (NH ³ ) is supplied at a flow rate of 0.8 L / min. Feed for 20 minutes. Thus, an AlN buffer layer 60 (Al buffer layer 62) is formed. The thickness of the AlN buffer layer 62 is about 100 nm.

  The substrate temperature is 1040 ° C., TMGa is supplied at a flow rate of 18 cc / min, TMAl is supplied at a flow rate of 25 cc / min, and ammonia is supplied at a flow rate of 2.5 L / min for 11 minutes. Thereby, the first AlGaN intermediate layer 71a is formed. The Al composition ratio in the first AlGaN intermediate layer 71a is, for example, 0.25.

  The substrate temperature is set to 1090 ° C., TMGa is supplied at a flow rate of 56 cc / min, and ammonia is supplied at a flow rate of 40 L / min for 15 minutes. Thereby, the first GaN intermediate layer 72a is formed. The thickness of the first GaN layer 51g is, for example, about 300 nm.

  The substrate temperature is set to 800 ° C., TMAl is supplied at a flow rate of 17 cc / min, and ammonia is supplied at a flow rate of 10 L / min for 3 minutes. Thereby, the first AlN intermediate layer 73a is formed. The thickness of the first AlN intermediate layer 73a is, for example, about 12 nm.

  The substrate temperature is set to 1120 ° C., TMGa is supplied at a flow rate of 18 cc / min, TMAl is supplied at a flow rate of 6 cc / min, and ammonia is supplied at a flow rate of 2.5 L / min for 2.5 minutes. Thereby, the second AlGaN intermediate layer 71b is formed. The Al composition ratio in the second AlGaN intermediate layer 71b is, for example, 0.5.

  The substrate temperature is set to 1090 ° C., TMGa is supplied at a flow rate of 56 cc / min, and ammonia is supplied at a flow rate of 40 L / min for 15 minutes. Thereby, the second GaN intermediate layer 72b is formed. The thickness of the second GaN intermediate layer 72b is, for example, about 300 nm.

  The substrate temperature is set to 800 ° C., TMAl is supplied at a flow rate of 17 cc / min, and ammonia is supplied at a flow rate of 10 L / min for 3 minutes. Thereby, the second AlN intermediate layer 73b is formed. The thickness of the second AlN intermediate layer 73b is, for example, about 12 nm. Thus, the laminated intermediate layer 70 is formed.

The stacked body 50 and the functional layer 15 are formed on the stacked intermediate layer 70. The conditions described in regard to the first embodiment are applied to the stacked body 50 and the functional layer 15.
Thereby, the nitride semiconductor device 120 and the nitride semiconductor wafer 220 according to the present embodiment are manufactured.

In the nitride semiconductor device 120 and the nitride semiconductor wafer 220 according to the present embodiment, the edge dislocation density De shows a low value of 2.0 × 10 ⁸ (/ cm ² ).

The edge dislocation density De in the nitride semiconductor device 110 and the nitride semiconductor wafer 210 according to the first embodiment is 2.8 × 10 ⁸ (/ cm ³ ) (first sample 151 illustrated in FIG. 7). . In the configuration in which the laminated intermediate layer 70 is provided, the dislocation density is reduced to about 70% compared to the configuration in which the stacked intermediate layer 70 is not provided.

  The warpage at room temperature of the nitride semiconductor device 120 including the substrate 40 and the nitride semiconductor wafer 220 is concave, and the warpage is approximately 10 μm. On the other hand, the warpage in the nitride semiconductor device 110 and the nitride semiconductor wafer 210 according to the first embodiment is concave, and the magnitude of the warpage is about 40 μm. In the configuration in which the stacked intermediate layer 70 is provided, the warpage is reduced as compared with the configuration in which the stacked intermediate layer 70 is not provided. That is, the tensile formed in the nitride semiconductor element 120 and the nitride semiconductor wafer 220 by providing the stacked intermediate layer 70. Distortion can be reduced and cracks can be reduced.

  As described above, the laminated intermediate layer 70 includes a GaN intermediate layer (for example, the first GaN intermediate layer 72a), an AlN intermediate layer (for example, the first AlN intermediate layer 73a), and an AlGaN intermediate layer (for example, the second AlGaN intermediate layer 71b). Including. The AlN intermediate layer (for example, the first AlN intermediate layer 73a) is provided on the GaN intermediate layer (for example, the first GaN intermediate layer 72a). The AlGaN intermediate layer (for example, the second AlGaN intermediate layer 71b) is provided on the AlN intermediate layer (for example, the first AlN intermediate layer 73a).

  As described above, by providing the stacked intermediate layer 70 between the buffer layer 60 and the stacked body 50, a nitride semiconductor element and a nitride semiconductor wafer having a lower dislocation density can be obtained. Furthermore, by providing the lamination | stacking intermediate | middle layer 70, curvature can be reduced and a crack can be suppressed.

  By X-ray diffraction measurement, the first-axis lattice spacing (corresponding to the a-axis lattice spacing in this example) perpendicular to the stacking direction of the first AlN intermediate layer 73a can be evaluated. In this measurement, the lattice spacing Da of the first AlN intermediate layer 73a is 0.3145 nm, which is larger than the lattice spacing da of unstrained AlN, 0.3112 nm. Therefore, compressive stress is formed on the second AlGaN intermediate layer 73b formed on the first AlN intermediate layer 73a. The a-axis lattice spacing dg of unstrained GaN is 0.3189 nm. Therefore, the relaxation rate α of the first AlN intermediate layer 73a corresponds to 0.57.

  On the other hand, cracks occurred in the reference example in which the second AlGaN intermediate layer 73b having an Al composition ratio of 0.7 was formed. When this sample was evaluated in the same manner as described above, it was found that tensile stress was formed in the second AlGaN intermediate layer 73b. That is, a tensile stress was formed on the AlGaN layer even though an AlGaN layer having an unstrained lattice spacing larger than that of AlN and having an Al composition ratio of 0.7 was formed on the AlN layer. This is because the first AlN intermediate layer 73a is distorted and the actual lattice spacing is larger than the unstrained lattice spacing.

  Thus, by forming an AlGaN intermediate layer having an Al composition ratio equal to or less than the relaxation rate α, a high-quality nitride semiconductor device with few cracks can be obtained.

  With such a nitride semiconductor element 120 and nitride semiconductor wafer 220, a nitride semiconductor element and nitride semiconductor wafer with few dislocations can be provided. Furthermore, cracks can be suppressed.

FIG. 21 is a schematic cross-sectional view illustrating the nitride semiconductor device according to the embodiment.
As illustrated in FIG. 21, the nitride semiconductor device 121 according to the embodiment further includes a first electrode 10e and a second electrode 20e. The functional layer 15 includes an n-type semiconductor layer 10, a p-type semiconductor layer 20, and a light emitting layer 30. In this example, a low impurity concentration layer 10i is also provided. The nitride semiconductor element 121 is a semiconductor light emitting element.

  In this example, the n-type semiconductor layer 10 includes a first portion 11 and a second portion 12. The second portion 12 is aligned with the first portion 11 in the XY plane. A light emitting layer 30 is provided between the second portion 12 and the p-type semiconductor layer 20.

  The first electrode 10 e is electrically connected to the first portion 11 of the n-type semiconductor layer 10. The second electrode 20 e is electrically connected to the p-type semiconductor layer 20. A current is supplied to the functional layer 15 through the first electrode 10 e and the second electrode 20 e, and light is emitted from the light emitting layer 30.

  In the nitride semiconductor device 121, the stack 50 according to the embodiment is provided, so that the dislocation density is low, and as a result, for example, high luminous efficiency is obtained.

FIG. 22 is a schematic cross-sectional view illustrating the nitride semiconductor device according to the embodiment.
As shown in FIG. 22, the nitride semiconductor element 122 according to the embodiment also includes the first electrode 10 e and the second electrode 20 e. In this example, after the functional layer 15 is formed on the stacked body 50, the substrate 40, the buffer layer 60, and the stacked body 50 are removed. For example, after forming the n-type semiconductor layer 10, the light emitting layer 30, and the p-type semiconductor layer 20 of the functional layer 15, the second electrode 20 e is formed on the p-type semiconductor layer 20. Then, the first bonding metal layer 46 is formed on the second electrode 20e. On the other hand, a support substrate 45 (for example, a silicon plate) on which the second bonding metal layer 47 is formed on the main surface is prepared. The first bonding metal layer 46 and the second bonding metal layer 47 are bonded to each other. Thereafter, at least a part of the substrate 40, the buffer layer 60, and the stacked body 50 used for crystal growth is removed.

  In the nitride semiconductor element 122, by using the functional layer 15 formed on the stacked body 50 according to the embodiment, the dislocation density is low, and as a result, for example, high luminous efficiency is obtained.

FIG. 23 is a schematic cross-sectional view illustrating another nitride semiconductor element according to this embodiment.
As illustrated in FIG. 23, another nitride semiconductor device 123 according to the embodiment includes a buffer layer 60, a stacked intermediate layer 70, a stacked body 50, and a functional layer 15. A stacked body 50 is provided on the buffer layer 60. A laminated intermediate layer 70 is provided on the laminated body 50. The functional layer 15 is provided on the stacked intermediate layer 70. The nitride semiconductor wafer 223 according to this embodiment includes a substrate 40, a buffer layer 60, a stacked intermediate layer 70, and a stacked body 50. The nitride semiconductor wafer 220 may further include a functional layer 15. The configuration described with respect to the nitride semiconductor element 120 can be applied to each of the substrate 40, the buffer layer 60, the stacked body 50, the stacked intermediate layer 70, and the functional layer 15.

  In nitride semiconductor device 123 (and nitride semiconductor wafer 223), stacked intermediate layer 70 includes a first intermediate layer 70a and a second intermediate layer 70b. The second intermediate layer 70b is provided on the first intermediate layer 70a.

  The first intermediate layer 70a includes a first AlGaN intermediate layer 71a, a first GaN intermediate layer 72a, and a first AlN intermediate layer 73a. The first AlGaN intermediate layer 71a is provided on the first AlN intermediate layer 73a. The first GaN intermediate layer 72a is provided on the first AlGaN intermediate layer 71a.

  The second intermediate layer 70b includes a second AlGaN intermediate layer 71b, a second GaN intermediate layer 72b, and a second AlN intermediate layer 73b. The second AlN intermediate layer 73b is provided on the first GaN intermediate layer 72a. The second AlGaN intermediate layer 71b is provided on the second AlN intermediate layer 73b. The second GaN intermediate layer 72b is provided on the second AlGaN intermediate layer 71b.

  The manufacturing method of the nitride semiconductor device 123 (and the nitride semiconductor wafer 223) can be applied by appropriately changing the manufacturing method described for the nitride semiconductor device 120.

In the nitride semiconductor element 123 and the nitride semiconductor wafer 223, the edge dislocation density De shows a low value of 2.2 × 10 ⁸ (/ cm ² ).

  The warpage at room temperature of the nitride semiconductor element 123 including the substrate 40 and the nitride semiconductor wafer 223 is convex, and the magnitude of the warpage is about 10 μm.

  On the other hand, the warpage in the nitride semiconductor device 110 including the substrate 40 and the nitride semiconductor wafer 210 is concave, and the size of the warpage is about 40 μm. The warpage in the nitride semiconductor device 120 including the substrate 40 and the nitride semiconductor wafer 220 is concave, and the magnitude of the warpage is about 10 μm.

  Like the nitride semiconductor element 123 and the nitride semiconductor wafer 223, by providing the stacked intermediate layer 70 on the stacked body 50, tensile strain formed in the nitride semiconductor element can be reduced, and the effect of reducing cracks can be obtained. Increase.

FIG. 24 is a schematic cross-sectional view illustrating the nitride semiconductor device according to the embodiment.
As shown in FIG. 24, the nitride semiconductor device 130 according to the embodiment is a HEMT (High Electron Mobility Transistor) device. In the nitride semiconductor device 130, the functional layer 15 includes a first layer 16, a second layer 17, a gate electrode 18g, a source electrode 18s, and a drain electrode 18d.

The first layer 16 is provided on the stacked body 50. The second layer 17 is provided on the first layer 16. For the first layer 16, for example, undoped Al _α Ga _1-α N (0 ≦ α ≦ 1) containing no impurities is used. For the second layer 17, for example, undoped or n-type Al _β Ga _1-β N (0 ≦ β ≦ 1, α <β) is used. For example, an undoped GaN layer is used for the first layer 16, and an undoped or n-type AlGaN layer is used for the second layer 17.

  The gate electrode 18 g, the source electrode 18 s, and the drain electrode 18 d are provided on the second layer 17. The source electrode 18s is separated from the drain electrode 18d in the XY plane. The source electrode 18 s and the drain electrode 18 d are in ohmic contact with the second layer 17. A gate electrode 18g is disposed on the second layer 17 between the source electrode 18s and the drain electrode 18d. The gate electrode 18g is in Schottky contact with the second layer 17.

  The lattice constant of the second layer 17 is smaller than the lattice constant of the first layer 16. As a result, distortion occurs in the second layer 17 and piezoelectric polarization occurs in the second layer 17 due to the piezoelectric effect. A two-dimensional electron gas 17 g is formed near the interface of the first layer 16 with the second layer 17. In the nitride semiconductor device 130, by controlling the voltage applied to the gate electrode 18g, the two-dimensional electron gas concentration under the gate electrode 18g increases or decreases, and the current flowing between the source electrode 18s and the drain electrode 18d is controlled. Is done.

  In the nitride semiconductor device 130, the dislocation density is low by using the functional layer 15 formed on the stacked body 50 according to the embodiment, and as a result, good electrical characteristics can be obtained.

  In the present embodiment, the stacked body 50 may be provided on the buffer layer 60, the stacked intermediate layer 70 may be provided on the stacked body 50, and the functional layer 15 may be provided on the stacked intermediate layer 70.

(Third embodiment)
FIG. 25 is a flowchart illustrating the method for forming the nitride semiconductor layer according to the third embodiment.
As shown in FIG. 25, in the method for forming a nitride semiconductor layer according to this embodiment, Al _x Ga _1-x N (0) is formed on the buffer layer 60 provided on the substrate 40 and including the nitride semiconductor. <X ≦ 1) AlGaN layer 51a is formed (step S110).

Further, a first Si-containing layer 51s containing Si at a concentration of 7 × 10 ¹⁹ / cm ³ or more and 4 × 10 ²⁰ / cm ³ or less is formed in contact with the upper surface 51au of the AlGaN layer 51a (step S120).

  Further, a first GaN layer 51g including a convex portion 51gp having a slope 51gs inclined with respect to the upper surface 51au is formed on the first Si-containing layer 51s (step S130).

  Further, a second Si-containing layer 52s containing Si is formed on the first GaN layer 51g (step S140).

  Further, the second GaN layer 52g is formed on the second Si-containing layer 52s (step S150).

Thereby, the stacked body 50 including the AlGaN layer 51a, the first Si-containing layer 51s, the first GaN layer 51g, the second Si-containing layer 52s, and the second GaN layer 52g is formed (step S110a).
According to this formation method, a method for forming a nitride semiconductor layer with few dislocations can be provided.

  As shown in FIG. 25, the formation method may further include a process (step S160) of forming the functional layer 15 on the second GaN layer 52g. The formation method may further include a process (step S105) for forming the buffer layer 60 on the substrate 40. The formation method may further include a process (step S106) of forming the stacked intermediate layer 70 on the buffer layer 60. In this case, in the formation of the AlGaN layer 51a (step S110), the AlGaN layer 51a is formed on the stacked intermediate layer 70.

  In the embodiment, the growth of the nitride semiconductor layer includes, for example, a metal-organic chemical vapor deposition (MOCVD) method, a metal-organic vapor phase epitaxy (MOVPE) method, a molecule A line beam epitaxy (MBE) method, a halide vapor phase epitaxy (HVPE) method, or the like can be used.

For example, when the MOCVD method or the MOVPE method is used, the following can be used as raw materials for forming each semiconductor layer. For example, TMGa (trimethyl gallium) and TEGa (triethyl gallium) can be used as the Ga raw material. As a source of In, for example, TMIn (trimethylindium), TEIn (triethylindium), or the like can be used. As a raw material for Al, for example, TMAl (trimethylaluminum) can be used. As a raw material of N, for example, NH ₃ (ammonia), MMHy (monomethylhydrazine), DMHy (dimethylhydrazine) and the like can be used. As a Si raw material, SiH ₄ (monosilane), Si ₂ H ₆ (disilane), or the like can be used.

  According to the embodiment, a nitride semiconductor device, a nitride semiconductor wafer, and a method for forming a nitride semiconductor layer with few dislocations can be provided.

In this specification, “nitride semiconductor” means B _x In _y Al _z Ga _1-xyz N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z ≦ 1) Semiconductors having all compositions in which the composition ratios x, y, and z are changed within the respective ranges are included. Furthermore, in the above chemical formula, those further containing a group V element other than N (nitrogen), those further containing various elements added for controlling various physical properties such as conductivity type, and unintentionally Those further including various elements included are also included in the “nitride semiconductor”.

  In the present specification, “vertical” and “parallel” include not only strictly vertical and strictly parallel, but also include, for example, variations in the manufacturing process, and may be substantially vertical and substantially parallel. It ’s fine.

  The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, regarding a specific configuration of each element such as a substrate, a buffer layer, a stacked intermediate layer, a stacked body, an AlGaN layer, a GaN layer, a Si-containing layer, and a functional layer included in a nitride semiconductor element and a nitride semiconductor wafer, It is included in the scope of the present invention as long as a person skilled in the art can carry out the present invention by selecting appropriately from the known ranges and obtain the same effect.

  Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, all nitride semiconductor elements that can be implemented by a person skilled in the art by appropriately modifying the design based on the nitride semiconductor element, nitride semiconductor wafer, and nitride semiconductor layer forming method described above as embodiments of the present invention. The nitride semiconductor wafer and the method for forming the nitride semiconductor layer also belong to the scope of the present invention as long as they include the gist of the present invention.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... n-type semiconductor layer, 10e ... 1st electrode, 10i ... Low impurity concentration layer, 11 ... 1st part, 12 ... 2nd part, 15 ... Functional layer, 15l ... Interface, 16 ... 1st layer, 17 2nd layer, 17g ... 2D electron gas, 18d ... drain electrode, 18g ... gate electrode, 18s ... source electrode, 20 ... p-type semiconductor layer, 20e ... 2nd electrode, 30 ... light emitting layer, 31 ... barrier layer, 32 ... Well layer, 40 ... Substrate, 45 ... Support substrate, 46 ... First junction metal layer, 47 ... Second junction metal layer, 50 ... Laminate, 51a ... AlGaN layer, 51aa ... First AlGaN layer, 51ab ... Second AlGaN 51ac ... third AlGaN layer, 51au ... upper surface, 51g ... first GaN layer, 51gp ... convex part, 51gs ... slope, 51gt ... top surface, 51n ... n-GaN layer, 5 s ... first Si-containing layer, 51sp ... first region, 51s1 ... second region, 51su ... upper surface, 52g ... second GaN layer, 52s ... second Si-containing layer, 60 ... buffer layer, 62 ... AlN buffer layer, 70 ... stacked Intermediate layer 70a ... first intermediate layer 70b ... second intermediate layer 71a ... first AlGaN intermediate layer 71b ... second AlGaN intermediate layer 72a ... first GaN intermediate layer 72b ... second GaN intermediate layer 73a ... first AlN intermediate Layer, 73b ... second AlN intermediate layer, 80 ... dislocation, 81 ... first dislocation, 82 ... second dislocation, 83 ... third dislocation, 110, 111, 120, 121, 122, 123, 130 ... nitride semiconductor element, 151 to 156... First to sixth samples, 210, 211, 220, 223... Nitride semiconductor wafer, Ap1, Ap2. Analysis position, CS ... Si concentration, CSa1, CSa2 ... Si surface density, CSv1, CSv2 ... Si concentration, De ... Edge dislocation density, GRg1 ... Growth rate, GTg1 ... Growth temperature, Rg1 (V / III) ... V / III Ratio, S01 to S03 ... first to third examples, TMs1, TMs2 ... growth time, Zd ... depth, p1-p7 ... first to seventh parts, tg1, ... height, tg2, ... thickness, ts, ts1, ts2 ... Thickness

Claims (20)

A first Si-containing layer containing Si at a concentration of 7 × 10 ¹⁹ / cm ³ or more and 4 × 10 ²⁰ / cm ³ or less;
A first GaN layer provided on the first Si-containing layer and including a protrusion;
A second GaN layer provided on the first GaN layer;
A second Si-containing layer provided between the first GaN layer and the second GaN layer and containing Si;
A laminate comprising:
A functional layer provided in the laminate and including a nitride semiconductor;
A nitride semiconductor device comprising: The laminate further includes an AlGaN layer of Al _x Ga _1-x N (0 <x ≦ 1),
The nitride semiconductor device according to claim 1, wherein the stacked body is disposed between the AlGaN layer and the functional layer. The first GaN layer has a plurality of first dislocations connected to the slope of the convex portion in the convex portion,
Wherein said 2Si via-containing layer is continuous with the first transition, the number of dislocation of the 2GaN layer, said plurality of first dislocation nitride semiconductor device of less claim 1 than the number of. The convex portion of the first GaN layer further has a top surface perpendicular to the direction from the stacked body toward the functional layer,
The first GaN layer includes
A plurality of first dislocations connected to the slope of the convex portion in the convex portion ;
A plurality of second dislocations connected to the top surface in the convex portion;
Have
The second GaN layer has a plurality of third dislocations;
A part of the plurality of third dislocations is continuous with the second dislocation,
The ratio of the number of the third dislocations continuing to the first dislocation among the plurality of third dislocations to the number of the first dislocations is continuous with the second dislocation among the plurality of third dislocations. The nitride semiconductor device according to claim 1, wherein the ratio of the number of the third dislocations to the number of the second dislocations is lower. Nitride semiconductor device according to the height of the convex portion is any one of claims 1-4 is 100nm or more 1000nm or less. The upper surface of the first Si-containing layer includes a first region and a second region,
The first GaN layer is provided on the first region;
Wherein the first 2Si part containing layer, a nitride semiconductor device according to any one of claims 1 to 5 in the second region in contact with said first 1Si-containing layer. The Si concentration profile in the laminate is
A first portion having a first concentration of Si concentration of 7 × 10 ¹⁹ / cm ³ or more and 4 × 10 ²⁰ / cm ³ or less;
A second portion having a second concentration having a Si concentration lower than the first concentration;
A third portion provided between the first portion and the second portion and having a third concentration between which the Si concentration is between the first concentration and the second concentration;
A fourth portion provided between the third portion and the second portion and having a Si concentration of a fourth concentration between the third concentration and the second concentration;
A fifth portion provided between the first portion and the third portion, wherein the rate of change with respect to the thickness of the Si concentration is higher than the rate of change with respect to the thickness of the Si concentration in the third portion;
Provided between the third portion and the fourth portion, the rate of change with respect to the thickness of the Si concentration is higher than the rate of change with respect to the thickness of the Si concentration in the third portion, and with respect to the Si concentration in the fourth portion. A sixth part higher than the rate of change;
Provided between the fourth portion and the second portion, the rate of change with respect to the thickness of the Si concentration is higher than the rate of change with respect to the thickness of the Si concentration in the fourth portion, and with respect to the Si concentration in the second portion. A seventh part higher than the rate of change;
The nitride semiconductor device according to any one of claims 1 to 6, having a. The nitride semiconductor device according to claim 7 , wherein the third concentration of the third portion is 3 × 10 ¹⁸ / cm ³ or more and 5 × 10 ¹⁹ / cm ³ or less. The thickness of the first portion is 1 nm or more and 200 nm or less,
The thickness of the third portion is 100 nm or more and 1000 nm or less,
The thickness of the fourth part, a nitride semiconductor device according to claim 7 or 8 is 300nm or more 2500nm or less. A buffer layer comprising a nitride semiconductor;
The nitride semiconductor device according to the laminate of any one of claims 1-9 provided between the buffer layer and the functional layer. A stack intermediate layer provided between the buffer layer and the stacked body;
The laminated intermediate layer is
A GaN intermediate layer;
An AlN intermediate layer provided between the GaN intermediate layer and the laminate;
An AlGaN intermediate layer provided between the AlN intermediate layer and the buffer layer;
Nitride semiconductor device according to claim 1 0, wherein including. Further comprising a substrate,
The nitride semiconductor device according to claim 1 0 or 1 1, wherein the buffer layer is disposed between the laminate and the substrate. The substrate, the nitride semiconductor device of claim 1 2 wherein the silicon substrate.   14. The nitride semiconductor device according to claim 1, wherein at least one of the first Si-containing layer and the second Si-containing layer includes SiN. A substrate,
A buffer layer provided on the substrate and including a nitride semiconductor;
A laminate provided in the buffer layer,
A first Si-containing layer containing Si at a concentration of 7 × 10 ¹⁹ / cm ³ or more and 4 × 10 ²⁰ / cm ³ or less;
A first GaN layer provided on the first Si-containing layer and including a protrusion;
A second GaN layer provided on the first GaN layer;
A second Si-containing layer provided between the first GaN layer and the second GaN layer and containing Si;
A laminate comprising:
A nitride semiconductor wafer comprising The laminate further includes an AlGaN layer of Al _x Ga _1-x N (0 <x ≦ 1),
The nitride semiconductor wafer according to claim 15, wherein the AlGaN layer is disposed between the buffer layer and the first Si-containing layer.   The nitride semiconductor wafer according to claim 15 or 16, wherein at least one of the first Si-containing layer and the second Si-containing layer contains SiN. Forming a first Si-containing layer containing Si at a concentration of 7 × 10 ¹⁹ / cm ³ or more and 4 × 10 ²⁰ / cm ³ or less in a buffer layer including a nitride semiconductor provided on the substrate;
Forming a first GaN layer including protrusions on the first Si-containing layer;
Forming a second GaN layer on the first GaN layer ;
A method for forming a nitride semiconductor layer, wherein a second Si-containing layer containing Si is formed between the first GaN layer and the second GaN layer . 19. The method for forming a nitride semiconductor layer according to claim 18, further comprising forming an Al _x Ga _1-x N (0 <x ≦ 1) AlGaN layer between the buffer layer and the first Si-containing layer.   The method for forming a nitride semiconductor layer according to claim 18, wherein at least one of the first Si-containing layer and the second Si-containing layer contains SiN.