JP6503049B2 - Nitride semiconductor device, nitride semiconductor wafer, and method of forming nitride semiconductor layer - Google Patents

Description

  Embodiments of the present invention relate to a nitride semiconductor device, a nitride semiconductor wafer, and a method of forming a nitride semiconductor layer.

As a nitride semiconductor element using a nitride semiconductor, for example, a light emitting diode (LED) is used for a display device, illumination, and the like. There are also electronic devices such as high-speed electronic devices and power devices as nitride semiconductor devices.
Such a nitride semiconductor device is mainly formed on a heterogeneous substrate such as sapphire or silicon (Si), but defects and warpage (cracks) of the substrate due to differences in lattice constant and thermal expansion coefficient occur. It's easy to do. In order to improve the performance of devices, it is important to reduce defects in a nitride semiconductor, and a technique for producing a nitride semiconductor crystal with few dislocations is desired.

JP, 2011-216580, A

  Embodiments of the present invention provide a method of forming a nitride semiconductor device, a nitride semiconductor wafer, and a nitride semiconductor layer with reduced dislocations.

According to the embodiment, there is provided a nitride semiconductor device provided with a laminate and a functional layer. The stacked body is a first GaN layer including a first convex portion, a first layer provided on the first GaN layer and containing Si, and a second GaN layer provided on the first layer and including a second convex portion. The length of the bottom of the second convex portion is shorter than the length of the bottom of the first convex portion, the second layer provided on the second GaN layer and containing Si, and Si And the third layer to be contained. The first GaN layer is provided between the third layer and the first layer. The functional layer is provided on the stacked body and includes a nitride semiconductor. Si concentration profile in the laminate comprises three peaks. The Si concentration profile includes a first portion of a first concentration having a Si concentration of 7 × 10 ¹⁹ / cm ³ or more and 4.5 × 10 ²⁰ / cm ³ or less and a second concentration having a Si concentration lower than the first concentration. And a third portion of a third concentration between the first concentration and the second concentration, provided between the first portion and the second portion, the third portion having a third concentration between the first concentration and the second concentration, Between the first portion and the second portion, the Si concentration being between the third portion and the fourth portion, and the fourth portion having a fourth concentration between the third concentration and the second concentration And a fifth portion provided between the third portion and the fourth portion, wherein the change rate of the Si concentration to the thickness is higher than the change rate of the Si concentration to the thickness of the third portion, The rate of change of Si concentration to thickness is greater than the rate of change of Si concentration to thickness in the third portion It is provided between the sixth portion which is higher than the change rate with respect to the Si concentration in the fourth portion, and between the fourth portion and the second portion, and the change rate of the Si concentration with respect to the thickness is Si in the fourth portion And a seventh portion that is higher than the rate of change with respect to the thickness of the concentration. In energy dispersive X-ray spectrometry, the first layer, the second layer and the third layer have peaks of Si and N.
According to the embodiment, the nitride semiconductor wafer includes a substrate and a laminate provided on the substrate. The stacked body is a first GaN layer including a first convex portion, a first layer provided on the first GaN layer and containing Si, and a second GaN layer provided on the first layer and including a second convex portion. The length of the bottom of the second convex portion is shorter than the length of the bottom of the first convex portion, the second layer provided on the second GaN layer and containing Si, and Si And the third layer to be contained. The first GaN layer is provided between the third layer and the first layer. The Si concentration profile in the laminate includes three peaks. The Si concentration profile includes a first portion of a first concentration having a Si concentration of 7 × 10 ¹⁹ / cm ³ or more and 4.5 × 10 ²⁰ / cm ³ or less and a second concentration having a Si concentration lower than the first concentration. And a third portion of a third concentration between the first concentration and the second concentration, provided between the first portion and the second portion, the third portion having a third concentration between the first concentration and the second concentration, Between the first portion and the second portion, the Si concentration being between the third portion and the fourth portion, and the fourth portion having a fourth concentration between the third concentration and the second concentration And a fifth portion provided between the third portion and the fourth portion, wherein the change rate of the Si concentration to the thickness is higher than the change rate of the Si concentration to the thickness of the third portion, The rate of change of Si concentration to thickness is greater than the rate of change of Si concentration to thickness in the third portion It is provided between the sixth portion which is higher than the change rate with respect to the Si concentration in the fourth portion, and between the fourth portion and the second portion, and the change rate of the Si concentration with respect to the thickness is Si in the fourth portion And a seventh portion that is higher than the rate of change with respect to the thickness of the concentration. In energy dispersive X-ray spectrometry, the first layer, the second layer and the third layer have peaks of Si and N.
According to the embodiment, the method of forming a nitride semiconductor layer includes the steps of forming a laminate on a substrate, and forming a functional layer containing a nitride semiconductor on the laminate. The step of forming the laminated body includes a step of forming a first GaN layer including a first convex portion, a step of forming a first layer containing Si on the first GaN layer, and a step of forming the first layer. Forming a second GaN layer including a second convex portion, wherein a length of a bottom portion of the second convex portion is shorter than a length of a bottom portion of the first convex portion, and the second GaN layer The steps of forming a second layer containing Si in the layer, and forming a third layer containing Si. The step of forming the first GaN layer includes forming the first GaN layer in the third layer. The Si concentration profile in the laminate includes three peaks. The Si concentration profile includes a first portion of a first concentration having a Si concentration of 7 × 10 ¹⁹ / cm ³ or more and 4.5 × 10 ²⁰ / cm ³ or less and a second concentration having a Si concentration lower than the first concentration. And a third portion of a third concentration between the first concentration and the second concentration, provided between the first portion and the second portion, the third portion having a third concentration between the first concentration and the second concentration, Between the first portion and the second portion, the Si concentration being between the third portion and the fourth portion, and the fourth portion having a fourth concentration between the third concentration and the second concentration And a fifth portion provided between the third portion and the fourth portion, wherein the change rate of the Si concentration to the thickness is higher than the change rate of the Si concentration to the thickness of the third portion, The rate of change of Si concentration to thickness is greater than the rate of change of Si concentration to thickness in the third portion It is provided between the sixth portion which is higher than the change rate with respect to the Si concentration in the fourth portion, and between the fourth portion and the second portion, and the change rate of the Si concentration with respect to the thickness is Si in the fourth portion And a seventh portion that is higher than the rate of change with respect to the thickness of the concentration. In energy dispersive X-ray spectrometry, the first layer, the second layer and the third layer have peaks of Si and N.

FIG. 1A and FIG. 1B are schematic cross-sectional views showing the nitride semiconductor device according to the first embodiment. FIGS. 2A to 2C are examples of SEM images representing the first GaN layer of the embodiment. FIG. 3A to FIG. 3D are graphs illustrating the characteristics of the nitride semiconductor device. FIG. 2 is a schematic cross-sectional view showing a part of the nitride semiconductor device according to the first embodiment. FIG. 5A to FIG. 5D are schematic cross-sectional views showing a sample. FIG. 6A to FIG. 6D are cross-sectional SEM images showing the buffer layer and the laminate. FIGS. 7A to 7C are transmission electron microscope images showing the nitride semiconductor device according to the reference example. FIG. 8A and FIG. 8B are views showing the nitride semiconductor device according to the first embodiment. It is a graph which shows the characteristic of the nitride semiconductor device concerning a 1st embodiment. It is a graph which shows the characteristic of the nitride semiconductor device concerning a 1st embodiment. FIGS. 11A and 11B are graphs showing characteristics of the nitride semiconductor device according to the first embodiment. 12 (a) and 12 (b) are graphs showing the nitride semiconductor device according to the first embodiment. FIG. 13A to FIG. 13D are views showing a nitride semiconductor device according to the embodiment. FIG. 14A to FIG. 14D are views showing the nitride semiconductor device and the nitride semiconductor wafer according to the second embodiment. It is a graph which shows the characteristic of the nitride semiconductor device concerning a 2nd embodiment. FIG. 6 is a schematic cross-sectional view illustrating another nitride semiconductor device and a nitride semiconductor wafer according to the embodiment. FIG. 17A and FIG. 17B are schematic cross-sectional views showing another nitride semiconductor device and a nitride semiconductor wafer according to the embodiment. FIG. 18A to FIG. 18D are schematic cross-sectional views showing a sample. FIGS. 19A to 19D are cross-sectional SEM images showing examples of the buffer layer and the laminate. It is a graph which shows the characteristic of the nitride semiconductor device concerning an embodiment. FIG. 21A to FIG. 21D are graphs showing the nitride semiconductor device according to the embodiment. FIG. 22A and FIG. 22B are views showing the nitride semiconductor device according to the embodiment. FIG. 7 is a schematic cross-sectional view illustrating another nitride semiconductor device according to the embodiment; FIG. 7 is a schematic cross-sectional view illustrating another nitride semiconductor device according to the embodiment; FIG. 7 is a schematic cross-sectional view illustrating another nitride semiconductor device according to the embodiment; It is a flowchart figure which shows the formation method of the nitride semiconductor layer which concerns on 3rd Embodiment. It is a flowchart figure which shows another formation method of the nitride semiconductor layer which concerns on 3rd Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of sizes between parts, and the like are not necessarily the same as the actual ones. In addition, even in the case of representing the same portion, the dimensions and ratios may be different from one another depending on the drawings.
In the specification of the present application and the drawings, the same elements as those described above with reference to the drawings are denoted by the same reference numerals, and the detailed description will be appropriately omitted.

First Embodiment
The present embodiment relates to a nitride semiconductor device and a nitride semiconductor wafer. The nitride semiconductor device according to the embodiment includes semiconductor devices such as a semiconductor light emitting device, a semiconductor light receiving device, and an electronic device. The semiconductor light emitting device includes, for example, a light emitting diode (LED) and a laser diode (LD). The semiconductor light receiving element includes a photodiode (PD) or the like. Electronic devices include, for example, high electron mobility transistors (HEMTs), heterojunction bipolar transistors (HBTs), electric field transistors (FETs) and Schottky barrier diodes (SBDs). The nitride semiconductor wafer according to the embodiment includes at least a part of the nitride semiconductor device according to the embodiment.

FIG. 1A and FIG. 1B are schematic cross-sectional views illustrating the nitride semiconductor device according to the first embodiment.
FIG.1 (b) is the figure which extracted a part of Fig.1 (a).
As shown in FIG. 1A, the nitride semiconductor device 110 according to the embodiment includes a buffer layer 60, a stacked body 50, and a functional layer 10. The stacked body 50 is provided on the buffer layer 60. The stacked body 50 is provided between the buffer layer 60 and the functional layer 10.
The direction from the laminate 50 toward the functional layer 10 is taken as the Z-axis direction. The Z-axis direction is the stacking direction of the buffer layer 60, the stack 50, and the functional layer 10. One direction perpendicular to the Z-axis direction is taken as the X-axis direction. A direction perpendicular to the Z-axis direction and the X-axis direction is taken as a Y-axis direction. In the following, the Z-axis direction (stacking direction) may be referred to as "upward" or "up". However, when the vertical direction of the nitride semiconductor device 110 is reversed, the “upper direction” and the “upper” described above are reversed.

  In this example, the nitride semiconductor device 110 further includes a substrate 40. The buffer layer 60 is disposed between the substrate 40 and the stack 50.

  The substrate 40 is, for example, a Si (111) substrate. In the embodiment, when the substrate 40 is a silicon substrate, the plane orientation of the substrate 40 does not have to be the (111) plane, and for example, the plane orientation represented by (11n) (n: integer) or the (100) plane May be. For example, the (110) plane is preferable because the lattice mismatch between the silicon substrate and the nitride semiconductor layer is reduced.

  The substrate 40 may be a substrate including an oxide layer. For example, the substrate 40 may be a silicon on insulator (SOI) substrate or the like. As the substrate 40, a substrate containing a material whose lattice constant is different from that of the functional layer 10 may be used. For the substrate 40, a substrate containing a material whose thermal expansion coefficient is different from that of the functional layer 10 may be used. For example, the substrate 40 may be any of sapphire, spinel, GaAs, InP, ZnO, Ge, SiGe, GaN, AlN and SiC.

  For example, the buffer layer 60 is formed on the substrate 40. The stacked body 50 is formed on the buffer layer 60. The functional layer 10 is formed on the laminate 50. Epitaxial growth is performed in these formations.

  The nitride semiconductor device 110 according to the embodiment may be used in a state where the substrate 40, the buffer layer 60, the stacked body 50, and a part of the functional layer 10 are removed. When the nitride semiconductor device 110 is a light emitting device, the functional layer 10 includes, for example, an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer.

  In the specification of the present application, the state in which the layers are stacked includes the state in which other layers are inserted and stacked in addition to the state in which the layers are stacked in contact with each other. The state provided on the top includes the state in which another layer is inserted and provided in addition to the state provided in direct contact.

The buffer layer 60 includes, for example, an AlN buffer layer 62.
The thickness of the AlN buffer layer 62 is preferably, for example, 10 nanometers (nm) or more and 400 nm or less, for example, about 200 nm. The buffer layer is not limited to the AlN layer, but may be a GaN layer. When a GaN layer is used as the buffer layer 60, the thickness of the GaN layer is, for example, 10 nm or more and 50 nm or less. The thickness of the GaN layer is, for example, about 30 nm. As the buffer layer 60, mixed crystals such as AlGaN or InGaN can be used.

  In the case where a silicon substrate is used as the substrate 40, problems such as meltback etching caused by the reaction of silicon and gallium can be solved by using AlN that hardly causes a chemical reaction with the substrate 40 (silicon substrate) as the buffer layer 60 in contact with silicon. Easy to solve. Preferably, at least a portion of the AlN used as the buffer layer 60 contains a single crystal. By epitaxially growing AlN at a high temperature of 1000 ° C. or more, a single crystal AlN buffer layer 62 can be formed. When a silicon substrate is used as the substrate 40, the difference in the thermal expansion coefficient between the nitride semiconductor and the silicon substrate is larger than the difference in the thermal expansion coefficients between the nitride semiconductor and the substrate of a material different from silicon. . Therefore, the warpage of the substrate 40 generated after the epitaxial growth is likely to be large, and a crack is easily generated. By using an AlN layer containing a single crystal as the buffer layer 60, stress (strain) is formed in the nitride semiconductor during epitaxial growth, and warpage of the substrate after completion of growth can be reduced.

  Preferably, tensile stress (strain) is formed in the AlN buffer layer 62. The formation of tensile stress (strain) in the AlN buffer layer 62 suppresses the formation of defects at the interface between the substrate 40 and the buffer layer 60.

  By the buffer layer 60 containing In, the lattice mismatch between the buffer layer 60 and the substrate 40 (silicon substrate) is relaxed, and the generation of dislocation is suppressed. When the buffer layer 60 contains In, a desorption reaction of In is likely to occur during crystal growth, and the In composition ratio is preferably 50% or less in order to obtain the buffer layer 60 with good flatness.

  The stacked body 50 includes a first GaN layer 53, a first layer 54, and a second GaN layer 55. For example, the stacked body 50 may further include an AlGaN layer 51, a second layer 56, a third layer 52, and a third GaN layer 57.

For the AlGaN layer 51, Al _x Ga _1-x N (0 <x ≦ 1) is used. The thickness of the AlGaN layer 51 is preferably, for example, 100 nm or more and 1000 nm or less, and for example, about 250 nm. The composition ratio of Al in the AlGaN layer 51 is preferably, for example, 0.1 or more and 0.9 or less, and is, for example, 0.25. The AlGaN layer 51 can increase the effect of suppressing the melt back etching. The compressive stress (strain) formed in the stacked body 50 can be increased by the AlGaN layer 51.

  When a plurality of nitride semiconductor layers having different compositions are stacked, the nitride semiconductor layer (for example, the AlGaN layer 51) stacked thereover is a nitride semiconductor layer (for example, the AlN buffer layer 62) formed below. It is formed to match the lattice spacing (length of the lattice) of. Therefore, the actual lattice spacing of the nitride semiconductor layer is different from the unstrained lattice spacing (lattice constant).

  In the present specification, the unstrained lattice spacing of the nitride semiconductor is referred to as “lattice constant”. In the present specification, the actual lattice length of the formed nitride semiconductor layer is referred to as "lattice spacing". The lattice constant is, for example, a physical property constant. The lattice spacing is, for example, the actual lattice length in the nitride semiconductor layer included in the formed nitride semiconductor device. The lattice spacing is determined, for example, from X-ray diffraction measurement.

The AlGaN layer 51 is crystalline at least in part. That is, at least a part of the AlGaN layer 51 is not amorphous but polycrystalline or single crystal. By forming the AlGaN layer 51 having a lattice constant larger than the lattice spacing of the AlN buffer layer 62 on the single crystal AlN buffer layer 62, a compressive stress (strain) is formed in the AlGaN layer 51 having crystallinity. . The lattice spacing of the compressively stressed (strained) formed AlGaN layer 51 is smaller than the unstrained lattice spacing (lattice constant). By forming the compressive stress (strain), it is possible to reduce the tensile stress (strain) generated due to the difference in thermal expansion coefficient between the nitride semiconductor and the silicon substrate in the temperature lowering process after crystal growth, and to warp or crack the substrate 40. Can be suppressed.
The crystallinity of the AlGaN layer 51 facilitates three-dimensional growth of a GaN layer to be a part of the stacked body 50 formed on the AlGaN layer 51. Thereby, dislocations are easily reduced. The crystallinity of the AlGaN layer 51 can be evaluated, for example, by observing a diffraction peak by X-ray diffraction measurement or the like. For example, it can be evaluated by observing a diffraction peak of a crystal plane (for example, (0002) plane) in a direction parallel to the growth direction (stacking direction).

The AlGaN layer 51 preferably has a flat surface without pits. By forming the GaN layer to be a part of the stacked body 50 on a flat surface, a larger compressive stress (strain) is easily formed in the GaN layer.
By forming the AlGaN layer 51 on the AlN buffer layer 62, dislocation can be reduced at the interface between the AlN buffer layer 62 and the AlGaN layer 51.

  The AlGaN layer 51 may be a single layer or may include a plurality of layers. In this example, the AlGaN layer 51 includes a first AlGaN layer 51a, a second AlGaN layer 51b, and a third AlGaN layer 51c. The number of layers included in the AlGaN layer 51 may be two or four or more. The second AlGaN layer 51b is provided on the first AlGaN layer 51a. The third AlGaN layer 51c is provided on the second AlGaN layer 51b. By forming a plurality of layers as the AlGaN layer 51, compressive stress (strain) formed in the AlGaN layer 51 can be increased. In that case, it is preferable to stack layers so that the Al composition ratio decreases in the upward direction from the buffer layer 60 (for example, in the direction from the buffer layer 60 toward the functional layer 10). That is, the Al composition ratio in the second AlGaN layer 51b is preferably lower than the Al composition ratio in the first AlGaN layer 51a, and the Al composition ratio in the third AlGaN layer 51c is preferably lower than the Al composition ratio in the second AlGaN layer 51b.

  For example, when AlN is used for the buffer layer 60, an AlGaN layer 51 with an Al composition ratio is obtained, in which the lattice mismatch rate of AlN and GaN at room temperature is divided at equal intervals by the number of stacked AlGaN layers 51. It is preferable to do. That is, for example, to form an AlGaN layer 51 having an Al composition ratio such that the lattice mismatch rate of each layer is a value obtained by dividing the lattice mismatch rate of AlN and GaN at room temperature by the number of laminations plus one. Is preferred. As a result, compressive stress (strain) formed in the AlGaN layer 51 is likely to increase.

  The lattice mismatch rate of AlN and the GaN layer at room temperature is about 2.1%. From this, for example, in the case of forming the three AlGaN layers 51, the Al composition ratio is such that the lattice mismatch ratio of each layer is about 0.5% (for example, 0.4% or more and 0.6% or less). The AlGaN layer 51 can be formed.

  For example, AlGaN layers 51 having an Al composition ratio of about 0.55, 0.3 and 0.15 can be stacked in this order. For example, the Al composition ratio in the first AlGaN layer 51a is about 0.55. The Al composition ratio in the second AlGaN layer 51b is about 0.3. The Al composition ratio in the third AlGaN layer 51c is about 0.15. With respect to the Al composition ratio, if the range of ± 0.05 of the above values (about 0.55, about 0.3, about 0.15), the lattice mismatch ratio of each layer is about 0.5% (eg, 0) .4% or more and 0.6% or less).

  For example, in the case of forming two AlGaN layers 51, an AlGaN layer 51 having an Al composition ratio such that the lattice mismatch rate of each layer is about 0.7% (eg, 0.6% or more and 0.8% or less) is used. It can be formed.

  For example, AlGaN layers 51 having an Al composition ratio of about 0.45 and 0.18 can be stacked in this order. For example, the Al composition ratio in the first AlGaN layer 51a is about 0.45. The Al composition ratio in the second AlGaN layer 51b is about 0.18.

  The reason why the difference in the Al composition ratio of each AlGaN layer 51 (in this example, the first AlGaN layer 51a, the second AlGaN layer 51b, and the third AlGaN layer 51c) is not constant is because strain (stress) is formed in the AlGaN layer 51 It is because The lattice mismatch rate of the AlGaN layer 51 can be calculated by X-ray diffraction measurement at room temperature.

  In the case of forming a plurality of layers as the AlGaN layer 51, it is preferable to stack them so that the film thickness becomes larger in the upward direction from the buffer layer 60 (for example, in the direction from the buffer layer 60 to the functional layer 10). That is, the film thickness of the second AlGaN layer 51b is preferably larger than the film thickness of the first AlGaN layer 51a, and the film thickness of the third AlGaN layer 51c is preferably larger than the film thickness of the second AlGaN layer 51b. As a result, compressive stress (strain) formed in the AlGaN layer 51 is likely to increase.

  The third layer 52 is provided on the AlGaN layer 51. The first GaN layer 53 is provided on the third layer 52. The first layer 54 is provided on the first GaN layer 53. The second GaN layer 55 is provided on the first layer 54. The second layer 56 is provided on the second GaN layer 55. For example, when the third GaN layer 57 is provided, the third GaN layer 57 is provided on the second layer 56. Below, the case where the 3rd GaN layer 57 is provided is mentioned as an example, and is explained.

Each of the first layer 54, the second layer 56 and the third layer 52 in the present embodiment contains at least one of silicon (Si) and magnesium (Mg). Each of the first layer 54, the second layer 56 and the third layer 52 in this embodiment may contain both Si and Mg. Each of the first layer 54, the second layer 56, and the third layer 52 may include at least one of SiN and MgN. Each of the first layer 54, the second layer 56 and the third layer 52 may include both SiN and MgN. Each of the first layer 54, the second layer 56 and the third layer 52 may be a GaN layer (δ-doped layer) heavily doped with at least one of Si and Mg. Each of the first layer 54, the second layer 56 and the third layer 52 may be a GaN layer (δ-doped layer) heavily doped with both Si and Mg.
The element contained in each of the first layer 54, the second layer 56, and the third layer 52 is desirable because Si does not impair the conductivity of the n-type semiconductor layer 11 formed as a part of the functional layer 10. Below, the case where each of the 1st layer 54, the 2nd layer 56, and the 3rd layer 52 contains Si is mentioned as an example, and is explained.

  The third layer 52 produces an effect of three-dimensionally growing the first GaN layer 53 when the first GaN layer 53 is formed on the third layer 52. This is because the third layer 52 has fluctuations in the Si concentration and thickness in the plane (in the XY plane) perpendicular to the stacking direction, and in the portion where the Si concentration is low and the portion where the thickness is thin. This is because the first GaN layer 53 is selectively grown on at least one of them. The three-dimensional growth of the first GaN layer 53 allows the dislocation generated in the buffer layer 60 to be bent in the direction perpendicular to the stacking direction (Z-axis direction). Thereby, dislocations reaching the functional layer 10 can be reduced. In a region where the growth of the first GaN layer 53 is inhibited by the third layer 52, dislocations generated in the buffer layer 60 are shielded by the third layer 52. This inhibits the propagation of dislocations to the top. The higher the coverage of the third layer 52 with respect to the AlGaN layer 51, the higher the dislocation reduction effect.

  In this example, the third layer 52 is in contact with the AlGaN layer 51. When the third layer 52 is in contact with the AlGaN layer 51, the first GaN layer 53 is grown while being affected by the lattice mismatch with the AlGaN layer 51. By providing the lattice mismatch, the first GaN layer 53 can be more easily grown in three dimensions, and the dislocation reduction effect can be increased. Dislocations occurring at the interface between the AlGaN layer 51 and the first GaN layer 53 can be reduced by providing a lattice mismatch.

In the first GaN layer 53, a compressive stress (strain) is preferably formed. By forming compressive stress (strain) in the first GaN layer 53, warpage of the substrate 40 after epitaxial growth can be reduced. By forming the compressive strain, the first GaN layer 53 is likely to be grown like an island.
In the present specification, island-like films are also referred to as "layers".

  By setting at least a part of the AlGaN layer 51 to be single crystal AlGaN, compressive stress (strain) can be formed in the first GaN layer 53. In the case of an amorphous AlGaN layer, the lattice spacing of the AlGaN layer 51 tends to be large, and it is difficult to form a compressive stress (strain) in the first GaN layer 53.

The thickness of the third layer 52 is, for example, one atomic layer, and preferably 0.4 atomic layer or more and 2.1 atomic layers or less. If the thickness of the third layer 52 is thinner than 0.4 atomic layer, three-dimensional growth of the first GaN layer 53 is difficult to occur, and it is difficult to obtain the effect of reducing dislocations. On the other hand, if the thickness of the third layer 52 is thicker than 2.1 atoms, the area where the first GaN layer 53 does not grow increases, and the flatness of the third GaN layer 57 tends to be degraded.
The third layer 52 may not be a uniform layer, but may be a discontinuous island layer or the like. The third layer 52 may be a layer provided with an opening.

The thickness of the third layer 52 can be obtained, for example, by direct observation with a transmission electron microscope (TEM) or a scanning electron microscope (SEM). When performing observation by SEM, a cross section cut at the cleavage plane of the nitride semiconductor layer or the substrate is used. The thickness of the third layer 52 is obtained from Secondary Ion-microprobe Mass Spectrometer (SIMS). In the secondary ion mass spectrometry, when the Si concentration in the layer is about 2 × 10 ²⁰ cm ³ , the thickness of the third layer 52 corresponds to one atomic layer. The Si concentration corresponds to a Si surface density of about 1 × 10 ¹⁵ cm ² when converted to a surface density.

  The first GaN layer 53 includes irregularities. The unevenness has a surface (first slope) 53s inclined with respect to a plane (within the XY plane) perpendicular to the stacking direction (Z-axis direction). The first GaN layer 53 may be a crystalline island layer discontinuous in the XY plane. The first inclined surface 53s inclined with respect to a plane (within the XY plane) perpendicular to the stacking direction (Z-axis direction) is, for example, a facet such as a (10-11) plane or a (11-22) plane. . The first slope 53s may not be a specific crystal plane. The first GaN layer 53 may have a dome shape. The first GaN layer 53 may have a plane perpendicular to the XY plane instead of the inclined surface.

FIGS. 2A to 2C are examples of SEM images representing the first GaN layer according to the embodiment. In the first example S01 shown in FIG. 2A, silane (SiH ₄ ) having a concentration of 10 ppm is flowed at 350 cc / min at a substrate temperature of 1040 ° C. and ammonia at a flow rate of 20 L / min on the AlGaN layer 51. Supplied for 3 minutes. Thereby, the third layer 52 is formed. Thereafter, at a substrate temperature of 1090 ° C., TMG is supplied at a flow rate of 56 cc / min, and ammonia is supplied at a flow rate of 40 L / min for 5 minutes. Thereby, the first GaN layer 53 is formed. The V / III ratio in the formation of the first GaN layer 53 corresponds to 6500. The thickness of the third layer 52 is about 0.4 atomic layer.

In the second example S02 shown in FIG. 2B, the growth time for forming the third layer 52 is set to 8 minutes. The thickness of the third layer 52 is about one atomic layer.
In the third example S03 shown in FIG. 2C, the ammonia flow rate at the time of formation of the first GaN layer 53 is 2.5 L / min. That is, the V / III ratio at the time of formation of the first GaN layer 53 is reduced to 490.

  As can be seen from FIG. 2A, the first GaN layer 53 is an island-like crystal layer. The thickness (height) of the convex portion 53 c (first convex portion) of the first GaN layer 53 is 150 nm to 200 nm. The diameter (width) 53 v of the bottom 53 u (see FIG. 1A) of the convex 53 c of the first GaN layer 53 (that is, the length of the bottom of the convex parallel to the XY plane) is about 1 .5 μm. Many microcrystals having a height of 50 nm or less are formed.

  As shown in FIG. 2B, when the formation time of the third layer 52 is increased to 8 minutes, the thickness (height) of the convex portion 53c of the first GaN layer 53 is increased to 200 nm to 500 nm. On the other hand, the diameter (width) 53 v of the bottom portion 53 u of the convex portion 53 c of the first GaN layer 53 is reduced to about 0.8 μm. The microcrystal having a height of 50 nm or less seen in FIG. 2A is not substantially formed. Thus, depending on the thickness of the third layer 52, the height (thickness) of the convex portion 53c of the first GaN layer 53 and the diameter (width) 53v of the bottom portion 53u of the convex portion 53c of the first GaN layer 53 are changed. be able to. When the thickness of the third layer 52 is large, the height (thickness) of the convex portion 53 c of the first GaN layer 53 tends to be high.

  On the other hand, as shown in FIG. 2C, when the V / III ratio of the first GaN layer 53 is decreased to 490, the height (thickness) of the convex portion 53c of the first GaN layer 53 is increased to 400 nm to 700 nm. Do. The area of the first inclined surface 53s is increased to be in a conical or dome shape. On the other hand, the diameter (width) 53v of the bottom portion 53u of the convex portion 53c of the first GaN layer 53 does not change by about 1.5 μm. Thus, the height (thickness) of the convex portion 53c of the first GaN layer 53 and the shape of the first slope 53s can be changed according to the V / III ratio of the first GaN layer 53. When the V / III ratio of the first GaN layer 53 is low, the height (thickness) of the convex portion 53c of the first GaN layer 53 tends to be high (thick), and the ratio of the first slope 53s tends to increase.

  The height (thickness) t1 (see FIG. 1B) of the convex portion 53c of the first GaN layer 53 is, for example, 100 nm or more and 1200 nm or less. When the first GaN layer 53 is provided on part of the third layer 52 as in the example shown in FIGS. 2A to 2C, the height of the convex portion 53c of the first GaN layer 53 is high. The thickness (thickness) t1 is a distance between the upper surface of the third layer 52 and the upper end of the convex portion 53c of the first GaN layer 53. When the first GaN layer 53 has a top surface (first top surface 53t), the height t1 is the distance between the top surface of the third layer 52 and the top surface (first top surface 53t). The height t1 of the first GaN layer 53 is determined by the upper surface of the third layer 52 and the convex of the first GaN layer 53 in the convex 53c having the highest height among the convexes (first convex) 53c of the first GaN layer 53. It is the distance between the upper end of the portion 53c.

  If another layer is provided between the first GaN layer 53 and the third layer 52, or if the third layer 52 is not provided, the height (thickness) of the convex portion 53c of the first GaN layer 53 t1 is the bottom 53u of the convex portion 53c of the first GaN layer 53 and the upper end of the convex portion 53c of the first GaN layer 53 (if the first GaN layer 53 has the first top surface 53t, the first top surface 53t) , Is the distance between.

  The first GaN layer 53 may cover the third layer 52. In this case, the height (thickness) of the convex portion 53c in the first GaN layer 53 is the height (depth) of the unevenness of the first GaN layer 53, that is, the Z axis between the convex portion and the concave portion of the unevenness. Corresponds to the distance along the direction. When the first GaN layer 53 covers the third layer 52, the diameter (width) 53v of the bottom portion 53u of the convex portion 53c of the first GaN layer 53 is the first concave portion of the concave and convex and the second concave portion adjacent to the first concave And correspond to the distance between.

  The first GaN layer 53 is provided with a protrusion 53 c. The thickness of the first GaN layer 53 is not uniform. The thickness of the first GaN layer 53 is different from the height of the convex portion 53 c of the first GaN layer 53. The thickness of the first GaN layer 53 is the average thickness of the first GaN layer 53.

FIG. 3A to FIG. 3D are graphs illustrating the characteristics of the nitride semiconductor device.
FIGS. 3A to 3D show the growth time (thickness) TM of the third layer 52, and the V / III ratio (V / III) at the time of forming the first GaN layer 53, the growth temperature. This shows an example of the change of the height (thickness) t1 of the first GaN layer 53 when the (substrate temperature) GT and the growth rate GR are changed.
In this example, the conditions not described below for the third layer 52 and the first GaN layer 53 are the same as those described above for FIGS. 2 (a) to 2 (c).

  FIG. 3A shows a change in height (thickness) t1 of the first GaN layer 53 when the growth time (thickness) TM of the third layer 52 is changed. As shown in FIG. 3A, for example, when the growth time TM of the third layer 52 is 5 minutes, the height (thickness) t1 of the first GaN layer 53 is 300 nm. When the growth time TM is 11 minutes, the height (thickness) t1 of the third layer 52 is 600 nm. As described above, when the growth time TM of the third layer 52 is long, the height (thickness) t1 of the first GaN layer 53 becomes high (thick). When the growth time TM of the third layer 52 is long, the island density of the first GaN layer 53 is reduced, and the distance between the first GaN layers 53 is increased.

  FIG. 3B shows a change in height (thickness) t1 of the first GaN layer 53 when the V / III ratio (V / III) is changed when the first GaN layer 53 is formed. . In this example, the supply amount of TMGa which is a Group III source gas is fixed at 56 cc / min, and the supply amount of ammonia is changed.

  As shown in FIG. 3B, for example, when the V / III ratio of the first GaN layer 53 is "3250", the height (thickness) t1 of the first GaN layer 53 is 450 nm. When the V / III ratio of the first GaN layer 53 is "410", the height (thickness) t1 of the first GaN layer 53 is 1000 nm. Thus, when the V / III ratio of the first GaN layer 53 is small, the height (thickness) t1 of the first GaN layer 53 is high (thick). When the V / III ratio of the first GaN layer 53 is small, the island density of the first GaN layer 53 is low, and the distance between the first GaN layers 53 is large.

  FIG. 3C shows a change in height (thickness) t1 of the first GaN layer 53 when the growth temperature (substrate temperature) GT is changed when the first GaN layer 53 is formed. As shown in FIG. 3C, for example, when the growth temperature GT of the first GaN layer 53 is 1050 ° C., the height (thickness) t1 of the first GaN layer 53 is 550 nm. When the growth temperature GT of the first GaN layer 53 is 1120 ° C., the height (thickness) t1 of the first GaN layer 53 is 210 nm. Thus, when the growth temperature GT of the first GaN layer 53 is low, the height (thickness) t1 of the first GaN layer 53 is high (thick). When the growth temperature GT of the first GaN layer 53 is higher than 1120 ° C., melt back etching is likely to occur and the crystal is likely to be degraded. When the growth temperature GT of the first GaN layer 53 is lower than 1000 ° C., pits are easily generated, and the crystal is easily deteriorated. Therefore, the growth temperature GT of the first GaN layer 53 is preferably 1000 ° C. or more and 1120 ° C. or less. When the growth temperature GT of the first GaN layer 53 is high, the desorption reaction of the Ga source on the crystal surface increases, and the island density of the first GaN layer 53 decreases. The size of the convex portion 53c of the first GaN layer 53 is reduced.

  FIG. 3D shows a change in the height (thickness) t1 of the first GaN layer 53 when the growth rate GR is changed when the first GaN layer 53 is formed. In this experiment, the supply amount of TMGa is changed. At this time, the growth time is changed so that the total supply amount of the source gas at the time of formation of the first GaN layer 53 becomes constant. For example, when the flow rate of TMGa is doubled to 112 cc / min, the growth time is halved to 2.5 minutes.

  As shown in FIG. 3D, for example, when the growth rate GR of the first GaN layer 53 is 19 nm / min, the height (thickness) t1 of the first GaN layer 53 is 550 nm. When the growth rate GR of the first GaN layer 53 is 48 nm / min, the height (thickness) t1 of the first GaN layer 53 is 250 nm. As described above, when the growth rate GR of the first GaN layer 53 is slow, the height (thickness) t1 of the first GaN layer 53 becomes high (thick). When the growth rate GR of the first GaN layer 53 is slow, the desorption reaction of the Ga source on the crystal surface increases, and the island density of the first GaN layer 53 decreases. That is, as the growth rate GR of the first GaN layer 53 is faster, the island-shaped first GaN layer 53 can be formed at a higher density.

  In FIGS. 2A to 2C and FIGS. 3A to 3D, undoped GaN is used for the first GaN layer 53. The first GaN layer 53 may be made of n-GaN doped with n-type impurities. When n-GaN is used, the size of the convex portion 53c of the first GaN layer 53 is smaller, the density of asperities is high, and the area of the slope is likely to increase, as compared to the case where n-type impurity (Si) is not doped. This is because the formation of facets is facilitated by doping the n-type impurity. As the area of the first layer 54 formed on the first slope 53s of the convex portion 53c of the first GaN layer 53 is increased, the effect of shielding or bending dislocations is increased, and the dislocations are easily reduced.

The concentration of the n-type impurity in the first GaN layer 53 is preferably 1.0 × 10 ¹⁷ (/ cm ³ ) or more and 1.0 × 10 ²⁰ (/ cm ³ ) or less. The concentration of the n-type impurity in the first GaN layer 53 is more preferably 1.0 × 10 ¹⁸ (/ cm ³ ) or more and 5.0 × 10 ¹⁹ (/ cm ³ ) or less. When the concentration of the n-type impurity in the first GaN layer 53 is 1.0 × 10 ¹⁷ (/ cm ³ ), it substantially corresponds to the concentration of the n-type impurity in the case of the undoped GaN layer. When the concentration of the n-type impurity in the first GaN layer 53 is higher than 1.0 × 10 ²⁰ (/ cm ³ ), the growth of the first GaN layer 53 is inhibited by the n-type impurity, and the convex portion 53 c of the first GaN layer 53 is The area of the slope (first slope 53s) decreases, and the reduction effect of dislocation density decreases.

  The concentration of n-type impurities in the first GaN layer 53 can be evaluated, for example, by secondary ion mass spectrometry (SIMS).

  As shown in FIG. 1A, the first layer 54 is formed on the first GaN layer 53. In this example, the first GaN layer 53 has a discontinuous island shape in the XY plane. A part of the first layer 54 is in contact with the first GaN layer 53. Another part of the first layer 54 contacts the third layer 52. By forming the first layer 54 on the inclined surface (first inclined surface 53s) of the first GaN layer 53, dislocation shielding or bending is caused at the interface between the first GaN layer 53 and the first layer 54, and the functional layer is formed. Dislocations propagating to 10 can be reduced. When the first layer 54 is in contact with the third layer 52, the dislocation shielding or bending effect of the first layer 54 is increased, and the propagation of dislocations generated in the buffer layer 60 is suppressed to the functional layer 10. Increase.

The thickness of the first layer 54 is, for example, 0.5 atomic layer, preferably 0.2 atomic layer or more and 2 atomic layers or less. If the thickness of the first layer 54 is thinner than 0.2 atomic layers, the dislocation bending effect at the first slope 53s can not be obtained, and dislocations are likely to increase. On the other hand, when the thickness of the first layer 54 is thicker than two atomic layers, the first GaN layer 53 substantially does not grow, and the flatness of the third GaN layer 57 is reduced.
The first layer 54 may not be a uniform layer, but may be a discontinuous island layer or the like. The first layer 54 may be a layer provided with an opening.

  The thickness of the first layer 54 is preferably thinner than the thickness of the third layer 52. When the thickness of the first layer 54 is larger than the thickness of the third layer 52, the growth of GaN on the inclined surface (first slope 53s) of the first GaN layer 53 is inhibited. Thereby, the surface flatness is reduced and the characteristics of the functional layer 10 are reduced.

  The second GaN layer 55 is formed on the first layer 54. The second GaN layer 55 includes an island-like crystal including asperities having a surface (second slope 55s) inclined with respect to a plane (within the XY plane) perpendicular to the stacking direction (Z-axis direction). The surface (second slope 55s) inclined with respect to a plane (within the XY plane) perpendicular to the stacking direction (Z-axis direction) has facets such as (10-11) plane and (11-22) plane, for example. It is a face. The second slope 55s may not be a specific crystal plane. The second GaN layer 55 may have a dome shape. The second GaN layer 55 may have a plane perpendicular to the XY plane rather than a sloped surface.

  For example, the second GaN layer 55 is formed on the top surface (first top surface 53t) of the first GaN layer 53. For example, the second GaN layer 55 is formed on the slope (first slope 53s) of the first GaN layer 53. In the specification of the present application, in the “the second GaN layer 55 is provided on the first GaN layer 53”, the second GaN layer 55 is on the top surface (first top surface 53 t) of the first GaN layer 53 and the first GaN layer. The state provided on at least one of the 53 slopes (first slope 53s) is included.

  The height (thickness) t2 (see FIG. 1A) of the convex portion (second convex portion) 55c of the second GaN layer 55 is, for example, 10 nm or more and 1000 nm or less. The height (thickness) t2 of the convex portion 55c of the second GaN layer 55 is the distance between the upper surface of the first layer 54 and the upper end of the convex portion 55c of the second GaN layer 55. When the second GaN layer 55 has a top surface (second top surface) 55t, the height t2 is the distance between the top surface of the first layer 54 and the second top surface 55t. In the second GaN layer 55 provided on the slope (first slope 53s) of the first GaN layer 53, the height t2 is the upper surface of the first layer 54 and the top of the convex portion 55c of the second GaN layer 55; The distance in the direction perpendicular to the slope (first slope 53s) of the first GaN layer 53 between them. The height t2 of the second GaN layer 55 is the upper surface of the first layer 54 and the upper end of the convex portion 55c of the second GaN layer 55 in the convex portion 55c having the highest height among the convex portions 55c of the second GaN layer 55; Distance between

  When the height (thickness) t2 of the convex portion 55c of the second GaN layer 55 is smaller than 10 nm (thin), the formation of the second slope 55s is insufficient, and the bending or shielding of dislocation in the first layer 54 I can not get enough effect. In this case, since the volume (surface area) of the crystal of the first GaN layer 53 is small (narrow), bending of dislocations is hard to occur in the crystal, and the dislocation reduction effect in the first GaN layer 53 is small.

  On the other hand, when the height (thickness) t2 is larger than 1000 nm, crystals of the adjacent second GaN layers 55 tend to be united together, and the second GaN layer 55 tends to be a continuous layer. As a result, the shielding effect at the second slope 55s is reduced, and dislocations tend to increase.

  Undoped GaN may be used for the second GaN layer 55. In the second GaN layer 55, n-GaN doped with n-type impurities may be provided. When n-GaN is used, the size of the convex portion is smaller, the density of the unevenness is higher, and the area of the slope is likely to be increased, as compared to the case where n-type impurity (Si) is not doped. This is because the formation of facets is facilitated by doping the n-type impurity. That is, the second GaN layer 55 having a small size is easily formed on the first GaN layer 53. The area of the second layer 56 formed on the second slope 55s of the convex portion 55c of the second GaN layer 55 is increased. Thereby, for example, the effect of shielding or bending dislocations is increased, and dislocations are easily reduced.

The concentration of the n-type impurity in the second GaN layer 55 is preferably, for example, 1.0 × 10 ¹⁷ (/ cm ³ ) or more and 1.0 × 10 ²⁰ (/ cm ³ ) or less. The concentration of the n-type impurity in the second GaN layer 55 is more preferably 1.0 × 10 ¹⁸ (/ cm ³ ) or more and 5.0 × 10 ¹⁹ (/ cm ³ ) or less. When the concentration of the n-type impurity in the second GaN layer 55 is 1.0 × 10 ¹⁷ (/ cm ³ ), it substantially corresponds to the concentration of the n-type impurity in the case of the undoped GaN layer. When the concentration of the n-type impurity in the second GaN layer 55 is higher than 1.0 × 10 ²⁰ (/ cm ³ ), the growth of the second GaN layer 55 is inhibited by the n-type impurity, and the convex portion of the second GaN layer 55 The area of the slope 55c (the second slope 55s) is reduced, and the reduction effect of the dislocation density is reduced.

  The concentration of n-type impurities in the second GaN layer 55 can be evaluated, for example, by secondary ion mass spectrometry (SIMS).

  The second layer 56 is formed on the second GaN layer 55. In this example, the second GaN layer 55 is in the form of discrete islands in the XY plane. A part of the second layer 56 is in contact with the second GaN layer 55. Another part of the second layer 56 is in contact with the first layer 54.

The AlGaN layer 51 has an upper surface 51 au. The direction perpendicular to the upper surface 51 au corresponds to the Z-axis direction. The upper surface 51 au of the AlGaN layer 51 is parallel to the XY plane. As shown in FIGS. 1A and 1B, the length (width) of the bottom 55u of the convex portion 55c of the second GaN layer 55 in the parallel direction (first direction) with respect to the upper surface 51au of the AlGaN layer 51 55 v is shorter than the length (width 53 v) of the bottom portion 53 u of the convex portion 53 c of the first GaN layer 53 in the first direction. The length 55 w of the convex portion 55 c of the second GaN layer 55 in any tangential direction (second direction) of the slopes (first slope 53 s) of the first GaN layer 53 is the same as that of the first GaN layer 53 in the second direction. The length of the projection 53c is shorter than the length 53w.
In other words, the size of the convex portion 55 c of the second GaN layer 55 is smaller than the size of the convex portion 53 c of the first GaN layer 53.
The number of second slopes 55s of the second GaN layer 55 per unit area on a plane (X-Y plane) perpendicular to the Z-axis direction (stacking direction) is the first number of first GaN layers 53 per unit area. More than the number of slopes 53s.

  Here, in the present specification, “layer size” refers to the width of a layer (including “island layer”). The “layer width” is the length of the layer in the direction parallel to the top surface 51 au of the AlGaN layer 51 (first direction). As the “layer width”, the length of the layer in any tangential direction (second direction) of the slopes (first slope 53s) of the first GaN 53 may be used.

  The ratio (length 55v / length 53v) of the length 55v of the bottom 55u of the convex portion 55c of the second GaN layer 55 to the length 53v of the bottom 53u of the convex 53c of the first GaN layer 53 is, for example, about 0.005 or more It is less than one. More preferably, for example, about 0.005 or more and 0.95 or less. Furthermore, more preferably, it is 0.01 or more and 0.7 or less.

  By forming the second GaN layer 55 having a size smaller than the size of the first GaN layer 53 on the first GaN layer 53, dislocation penetrating the first GaN layer 53 and the first layer 54 is bent in the second GaN layer 55. It can be done. The first GaN layer 53 may have a top surface (first top surface 53t). In the top surface (first top surface 53t) of the first GaN layer 53, the dislocation shielding or bending effect is small, and most of the dislocations extend to the functional layer 10 side. By forming the island-shaped second GaN layer 55 having the second slope 55s on the top surface (first top surface 53t) of the first GaN layer 53, it is possible to cause dislocation bending in the second GaN layer 55. . Thereby, dislocations reaching the functional layer 10 can be reduced.

  The bottom 55 u of the convex portion 55 c of the second GaN layer 55 has a length 55 v of the bottom 55 u of the convex 55 c of the second GaN layer 55 longer than the length 53 v of the bottom 53 u of the convex 53 c of the first GaN layer 53. May be included. Of the structure in which the convex portion 53c of the first GaN layer 53 and the convex portion 55c of the second GaN layer 55 are stacked, the structure of the second GaN layer 55 is preferably 10% or more, more preferably 50% or more. It is desirable for reducing the dislocation density that the length 55 v of the bottom 55 u of the protrusion 55 c is shorter than the length 53 v of the bottom 53 u of the protrusion 53 c of the first GaN layer 53.

  For example, when the growth temperature (substrate temperature) of the second GaN layer 55 is higher than the growth temperature of the first GaN layer 53, the second GaN layer 55 having a smaller size than the first GaN layer 53 is formed on the first GaN layer 53. It is easy to be done. For example, the growth temperature (substrate temperature) of the second GaN layer 55 is set higher than the growth temperature of the first GaN layer 53 by about 20 ° C. to 60 ° C.

  For example, when the growth rate of the second GaN layer 55 is slower than the growth rate of the first GaN layer 53, the second GaN layer 55 smaller in size than the first GaN layer 53 is likely to be formed on the first GaN layer 53. For example, the growth rate in the second GaN layer 55 is reduced to about 1⁄4 to 1⁄2 times the growth rate of the first GaN layer 53.

For example, when the growth time of the second GaN layer 55 is shorter than the growth time of the first GaN layer 53, the second GaN layer 55 smaller in size than the first GaN layer 53 is likely to be formed on the first GaN layer 53.
For example, when the growth pressure in the second GaN layer 55 is higher than the growth pressure in the first GaN layer 53, the second GaN layer 55 smaller in size than the first GaN layer 53 is likely to be formed on the first GaN layer 53. For example, the growth pressure in the first GaN layer 53 is 400 hectopascal (hPa), and the growth pressure in the second GaN layer 55 is 1013 hPa.

The thickness of the second layer 56 is, for example, 0.5 atomic layer, preferably 0.2 atomic layer or more and 2 atomic layers or less. If the thickness of the second layer 56 is thinner than 0.2 atomic layer, it is difficult to obtain the dislocation bending effect at the second slope 55s, and dislocations are likely to increase. On the other hand, if the thickness of the second layer 56 is thicker than 2 atoms, the second GaN layer 55 substantially becomes difficult to grow, and the flattening of the third GaN layer 57 becomes difficult.
The second layer 56 may not be a uniform layer, but may be a discontinuous island layer or the like. The second layer 56 may be a layer provided with an opening.

  The thickness of the second layer 56 is preferably thinner than the thickness of the third layer 52. When the thickness of the second layer 56 is larger than the thickness of the third layer 52, the growth of GaN on the inclined surface (the second slope 55s) of the second GaN layer 55 is inhibited. Thereby, the surface flatness is reduced and the characteristics of the functional layer 10 are reduced.

  The third GaN layer 57 is formed on the second layer 56. The upper surface of the third GaN layer 57 is, for example, flat. The functional layer 10 is formed on the third GaN layer 57. The thickness t3 of the third GaN layer 57 is, for example, 100 nm or more and 5000 nm or less. The thickness t3 of the third GaN layer 57 is the Z axis between the upper end of the second layer 56 and the upper surface of the third GaN layer 57 (in this example, the interface 10l between the stack 50 and the functional layer 10). It is the distance along the direction.

FIG. 4 is a schematic cross-sectional view illustrating a part of the nitride semiconductor device according to the first embodiment.
FIG. 4 shows an example of the functional layer 10. When the nitride semiconductor device 110 is a light emitting device, the functional layer 10 may be, for example, an n-type semiconductor layer 11 formed on the stacked body 50 and a light emitting layer formed on the n-type semiconductor layer 11 13 and a p-type semiconductor layer 12 formed on the light emitting layer 13. The light emitting layer 13 includes a plurality of barrier layers 13a of GaN and a well layer 13b provided between the barrier layers 13a. The number of well layers 13b may be one or more. That is, the light emitting layer 13 has, for example, a single-quantum well (SQW) structure or a multi-quantum well (MQW) structure.

The band gap energy of the barrier layer 13a is larger than the band gap energy of the well layer 13b. For example, GaN is used for the barrier layer 13a. The well layer 13b, for example, InGaN _(e.g., In _{0.15 Ga 0.85} N) is used. When InGaN is used for the barrier layer 13a, the In composition ratio in the barrier layer 13a is lower than the In composition ratio in the well layer 13b. The peak wavelength of the light emitted from the light emitting layer 13 is, for example, 200 nm or more and 1900 nm or less. The thickness of the functional layer 10 is preferably, for example, 5 nm or more and 5 μm or less, and for example, about 3.5 μm.

  The functional layer 10 may further include a low impurity concentration layer 11i. The impurity concentration in the low impurity concentration layer 11 i is lower than the impurity concentration in the n-type semiconductor layer 11. The low impurity concentration layer 11i may be provided or omitted as necessary. The low impurity concentration layer 11i is provided, for example, between the stacked body 50 and the n-type semiconductor layer 11.

The nitride semiconductor device 110 is used, for example, as a nitride semiconductor device of gallium nitride (GaN) -based HEMT (High Electron Mobility Transistor). At this time, the functional layer 10 includes, for example, an undoped Al _z1 Ga _1-z1 N (0 ≦ z1 ≦ 1) layer containing no impurity, and an undoped or n-type Al _z2 Ga _1-z2 N (0 ≦ z 2 ≦ 0). It has a laminated structure of 1, and z1 <z2) layer.

Thus, in the nitride semiconductor device 110 according to the present embodiment, the buffer layer 60, the functional layer 10 containing a nitride semiconductor, and the stacked body 50 provided between the buffer layer 60 and the functional layer 10 , Is provided. The stacked body 50 includes an Al _x Ga _1-x N (0 <x ≦ 1) layer 51 provided on the buffer layer 60, a third layer 52, a first GaN layer 53, and a first layer 54; It includes a structure in which the second GaN layer 55, the second layer 56, and the third GaN layer 57 are stacked in this order. The third layer 52 is in contact with the Al _x Ga _1-x N (0 <x ≦ 1) layer 51. The first GaN layer 53 includes asperities (first convex portions 53c) having a first inclined surface 53s inclined with respect to the main surface perpendicular to the stacking direction. The second GaN layer 55 includes an unevenness (second convex portion 55c) having a second inclined surface 55s inclined with respect to the main surface perpendicular to the stacking direction. At least a portion of the first layer 54 contacts the first GaN layer 53 and the third layer 52. At least a portion of the second layer 56 contacts the second GaN layer 55 and the first layer 54. The length of the second convex portion 55c in the first direction parallel to the upper surface of the second GaN layer 55 is shorter than the length of the first convex portion 53c in the first direction. Thereby, the effect of reducing dislocations is obtained, and the dislocations reaching the functional layer 10 are reduced.

  1A and 1B also illustrate the configuration of the nitride semiconductor wafer 210 according to the present embodiment. The nitride semiconductor wafer 210 includes a substrate 40, a buffer layer 60, and a stacked body 50. The nitride semiconductor wafer 210 may further include the functional layer 10. Each of the configurations described for the nitride semiconductor device 110 can be applied to the substrate 40, the buffer layer 60, the stacked body 50, and the functional layer 10.

Next, the characteristics of the nitride semiconductor device of the present embodiment will be described with reference to the drawings.
FIG. 5A to FIG. 5D are schematic cross-sectional views illustrating a sample.
FIG. 6A to FIG. 6D are cross-sectional SEM images showing examples of the buffer layer and the laminate. FIGS. 7A to 7C are transmission electron microscope images showing examples of the nitride semiconductor device according to the reference example.
FIG. 8A and FIG. 8B illustrate the nitride semiconductor device according to the first embodiment.

The nitride semiconductor device of the first example according to the present embodiment will be described.
The nitride semiconductor device 120 of the first embodiment shown in FIG. 5A has the same configuration as that of the nitride semiconductor device 110 illustrated in FIGS. 1A and 1B. The nitride semiconductor device 120 is manufactured as follows.

  First, the substrate 40 made of silicon whose main surface is a (111) plane is cleaned using a mixed chemical solution of sulfuric acid and hydrogen peroxide and dilute hydrofluoric acid. Thereafter, the substrate 40 is introduced into the reaction chamber of the MOCVD apparatus.

The substrate 40 is heated to 1070.degree. Trimethylaluminum (TMAl) is supplied at a flow rate of 50 cc / min and ammonia (NH ₃ ) is supplied at a flow rate of 0.8 L / min for 20 minutes in a reduced pressure atmosphere of 400 hPa with a hydrogen to nitrogen ratio of 2: 1. Thereby, the buffer layer 60 (AlN buffer layer 62) of AlN is formed. The thickness of the AlN buffer layer 62 is about 200 nm.

  Next, the substrate temperature (the temperature of the substrate 40) is set to 1020 ° C. (fourth temperature). The fourth temperature is equal to or less than a second temperature described later. Trimethylgallium (TMGa) is supplied at a flow rate of 10 cc / min, TMAl at a flow rate of 50 cc / min, and ammonia at a flow rate of 2.5 L / min for 5 minutes. Thus, the first AlGaN layer 51a having an Al composition ratio of 0.55 is formed. The thickness of the first AlGaN layer 51a is about 100 nm.

  Subsequently, the flow rate of TMG is changed to 17 cc / min, the flow rate of TMA to 30 cc / min, and supplied for 10 minutes. Thereby, the second AlGaN layer 51b having an Al composition ratio of 0.3 is formed. The thickness of the second AlGaN layer 51b is about 200 nm.

  Furthermore, the flow rate of TMG is changed to 20 cc / min, the flow rate of TMA to 15 cc / min, and supplied for 11 minutes. Thus, the third AlGaN layer 51c having an Al composition ratio of 0.15 is formed. The thickness of the third AlGaN layer 51c is about 250 nm.

Next, the substrate temperature is set to 1040 ° C., the growth pressure is changed to atmospheric pressure of 10 13 hPa, silane (SiH ₄ ) having a concentration of 10 ppm is supplied at a flow rate of 350 cc / min and ammonia at a flow rate of 20 L / min for 8 minutes. Thereby, the third layer 52 is formed. The thickness of the third layer 52 is about one atomic layer. When the third layer 52 contains Mg, for example, biscyclopentadienyl magnesium (Cp ₂ Mg) is contained in the second gas. For example, when the second gas containing silane, biscyclopentadienyl magnesium and ammonia is supplied, the third layer 52 containing Si and Mg can be formed.

Next, the substrate temperature is set to 1090 ° C. (first temperature), and for example, a first gas containing TMG, silane and ammonia is used at a flow rate of 112 cc / min for TMG and 11 cc / min for silane (SiH ₄ ) at a concentration of 10 ppm. Ammonia is supplied at a flow rate of 40 L / min for 2.5 minutes. The silane may be supplied by another route than TMG and ammonia. The silane may not be contained in the first gas. Thereby, the first GaN layer 53 is formed. The first GaN layer 53 includes an island-like crystal having a surface (first slope 53s) inclined with respect to the main surface perpendicular to the stacking direction. The thickness (height) of the first GaN layer 53 is about 300 nm.

Next, the substrate temperature is again set to 1040 ° C. (second temperature) equal to or lower than the first temperature, the second gas containing silane and ammonia, the flow rate of silane (SiH ₄ ) at a concentration of 10 ppm, 350 cc / min, the flow rate of ammonia Supply at 20 L / min for 3 minutes. Thereby, the first layer 54 is formed. The thickness of the first layer 54 is about 0.5 atomic layer. When the first layer 54 contains Mg, for example, biscyclopentadienyl magnesium (Cp ₂ Mg) is contained in the second gas. For example, when the second gas containing silane, biscyclopentadienyl magnesium and ammonia is supplied, the first layer 54 containing Si and Mg can be formed.

Next, the substrate temperature is set to 1120 ° C. (third temperature) equal to or higher than the first temperature. For example, the first gas containing TMG, silane and ammonia is used at a flow rate of 56 cc / min for TMG and a flow rate of silane (SiH ₄ ). Ammonia is supplied at a flow rate of 40 L / min for 2.5 minutes at 6 cc / min. The silane may be supplied by another route than TMG and ammonia. The silane may not be contained in the first gas. Thereby, the second GaN layer 55 is formed on the first GaN layer 53. The second GaN layer 55 includes an island-like crystal having a surface (second slope 55s) inclined with respect to the main surface perpendicular to the stacking direction. The thickness (height) of the second GaN layer 55 is about 100 nm.

  The growth temperature is raised by 30 ° C. and the TMG flow rate is halved compared to the growth time of the first GaN layer 53. Thereby, the adhesion of Ga is suppressed, and the second GaN layer 55 including island-like crystals smaller in size (size) than the first GaN layer 53 is selectively formed on the first GaN layer 53. The growth rate of the second GaN layer 55 is about 1/2 times slower than the growth rate of the first GaN layer 53.

Next, the substrate temperature is again adjusted to 1040 ° C., and a second gas containing silane and ammonia is supplied for 3 minutes at a flow rate of 350 cc / min of silane (SiH ₄ ) at a concentration of 10 ppm and ammonia at a flow rate of 20 L / min. . Thereby, the second layer 56 is formed. The thickness of the second layer 56 is about 0.5 atomic layer. When the second layer 56 contains Mg, for example, biscyclopentadienyl magnesium (Cp ₂ Mg) is contained in the second gas. For example, by supplying a second gas containing silane, biscyclopentadienyl magnesium and ammonia, a second layer 56 containing Si and Mg can be formed.

  Subsequently, the substrate temperature is set to 1090 ° C., first, TMG is supplied at a flow rate of 28 cc / min and ammonia is supplied at a flow rate of 40 L / min for 10 minutes. Thereby, part of the second GaN layer 55 is united. The thickness of the third GaN layer 57 formed in 10 minutes is about 80 nm. Thereafter, TMG is increased to a flow rate of 56 cc / min and supplied for 60 minutes. Thereby, the first GaN layer 53 and the second GaN layer 55 are united to form a flat third GaN layer 57. The thickness of the third GaN layer 57 is about 2 μm. At the time of formation of the third GaN layer 57, the TMG flow rate is made smaller than at the time of the growth of the first GaN layer 53 and the time of the growth of the second GaN layer 55 in the third GaN layer 57. Becomes flat and the film thickness tends to be small. By making the growth rate of the third GaN layer 57 slower than the growth rate of the first GaN layer 53 and the growth rate of the second GaN layer 55, the film thickness at which the third GaN layer 57 becomes flat can be reduced. Thereby, the warpage of the substrate 40 can be reduced.

Thereafter, as a formation of the functional layer 10, TMG is supplied at a flow rate of 56 cc / min, ammonia is supplied at a flow rate of 20 L / min, and silane (SiH ₄ ) is supplied at a flow rate of 56 cc for 30 minutes. Thus, an n-GaN layer (n-type GaN layer) having a Si concentration of 5 × 10 ¹⁸ (/ cm ³ ) is formed. The thickness of the functional layer 10 is about 1 μm. The n-type GaN layer becomes the n-type semiconductor layer 11 (at least a part of the functional layer 10). Thereby, the nitride semiconductor device or the nitride semiconductor wafer according to the present embodiment can be formed.

  The growth conditions other than the change point are formed under the same conditions as the previous process. At the time of changing the conditions for forming each layer, the supply of the group III gas and the silane is stopped while the ammonia gas is supplied, and the growth of the nitride semiconductor is interrupted.

FIG. 6A to FIG. 6D are views exemplifying SEM images obtained by observing a cross section cleaved along the (1-100) plane of the nitride semiconductor layer.
FIG. 6A is a view illustrating a cross-sectional SEM image of the nitride semiconductor device 120 according to the first embodiment.
As shown in FIG. 6A, the first GaN layer 53 has an unevenness having a surface (first slope 53s) inclined with respect to a plane (X-Y plane) perpendicular to the stacking direction (Z-axis direction). Including. The first GaN layer 53 includes island-like crystals that are discontinuous in a plane (within the XY plane) perpendicular to the stacking direction (Z-axis direction).

  The first layer 54 is in contact with the first GaN layer 53. A part of the first layer 54 is in contact with the third layer 52. The second GaN layer 55 is formed on the first GaN layer 53. The second GaN layer 55 includes asperities having a surface (second slope 55s) inclined with respect to a plane (X-Y plane) perpendicular to the stacking direction (Z-axis direction). The size of the second GaN layer 55 is smaller than the size of the first GaN layer 53. In this example, the second GaN layer 55 is formed on the first top surface 53t of the first GaN layer 53 and the first sloped surface 53s.

  The second layer 56 is in contact with the second GaN layer 55. A part of the second layer is in contact with the first layer 54. The distance between the first GaN layers 53 is as small as about 100 nm. It can be seen that the first GaN layer 53 is formed at high density. By forming the first GaN layer 53 at a high density, the area of the first sloped surface 53s can be increased and the dislocation reduction effect can be increased, even for a crystal with a low height. Since the height can be reduced, it is possible to reduce the tensile stress (strain) generated when the island-shaped first GaN layers 53 merge with each other. Thereby, a flat GaN layer can be formed while maintaining the compressive stress (strain) formed in the first GaN layer 53. Warpage of the substrate 40 can be reduced.

Hereinafter, a reference example will be described.
(First reference example)
FIG. 5B is a schematic cross-sectional view showing the nitride semiconductor device 131 of the first reference example.
In the nitride semiconductor device 131 of the first reference example, the second GaN layer 55 is formed on the first layer 54 as a continuous film. That is, in the nitride semiconductor device 131 of the first reference example, the second GaN layer 55 does not contain island-like crystals.

  In the first reference example, the supply of silane is stopped when the first GaN layer 53 is formed. At the same time, in forming the second GaN layer 55, the substrate temperature is set to 1090 ° C., the supply of silane is stopped, TMG is supplied at a flow rate of 112 cc / min, and ammonia is supplied at a flow rate of 40 L / min for 2.5 minutes. That is, in the formation of the second GaN layer 55, the same step as the step of forming the first GaN layer 53 is performed again. Other conditions are the same as those of the nitride semiconductor device 120.

FIG. 6B is a view illustrating a cross-sectional SEM image of the nitride semiconductor device 131 of the first reference example.
As can be seen from FIG. 6 (b), the second GaN layer 55 is formed as a continuous film on the first layer 54, and does not include island-like crystals. As described above, when the same steps as the formation of the first GaN layer 53 are repeated, island-like crystals are not formed. In this case, the first GaN layer 53 is likely to expand in a similar manner.

(Second reference example)
FIG. 5C is a schematic cross-sectional view showing a nitride semiconductor device 132 of the second reference example.
In the nitride semiconductor device 132 of the second reference example, the second GaN layer 55 and the second layer 56 are not provided.
FIG. 6C illustrates a cross-sectional SEM image of the nitride semiconductor device 132 according to the second reference example.

(Third reference example)
FIG. 5D is a schematic cross-sectional view showing a nitride semiconductor device 133 of the third reference example.
In the nitride semiconductor device 133 of the third reference example, the first GaN layer 53 and the second GaN layer 55 have surfaces inclined with respect to a plane (X-Y plane) perpendicular to the stacking direction (Z-axis direction). Not. The first GaN layer 53 and the second GaN layer 55 are flat layers.

  In the third reference example, when forming the first GaN layer 53, the supply of silane is stopped, and TMG is supplied at a flow rate of 56 cc / min and ammonia is supplied at a flow rate of 40 L / min for 15 minutes. Thereafter, the steps of forming the first GaN layer 53 and the first layer 54 are repeated twice. Other conditions are the same as those of the nitride semiconductor device 120.

FIG. 6D is a view showing a cross-sectional SEM image of the nitride semiconductor device 133 of the third reference example.
As can be seen from FIG. 6 (d), the first GaN layer 53 and the second GaN layer 55 are flat. The thickness of the first GaN layer 53 is about 600 nm. The thickness of the second GaN layer 55 is about 600 nm.

FIGS. 7A to 7C are diagrams illustrating cross-sectional TEM images of the nitride semiconductor device 132 illustrated in the second reference example.
FIG. 7A is a cross-sectional TEM image of the region from the substrate 40 to the functional layer 10. FIG. 7B is an enlarged cross-sectional TEM image of a region of the first GaN layer 53 similar to the region including the first inclined surface 53s (the region RN1 illustrated in FIG. 7A). FIG. 7C is an enlarged cross-sectional view of a region of the first GaN layer 53 similar to the region including the plane (first top surface 53t) perpendicular to the stacking direction (the region RN2 shown in FIG. 7A). It is an image. The black lines shown in FIGS. 7 (a) to 7 (c) represent dislocations. In FIG. 7A, the first layer 54 is drawn by a dotted line.

  As can be seen from FIG. 7A, the dislocations 20 generated at the interface between the substrate 40 and the AlN buffer layer 62 are significantly reduced in the third layer 52. A part of the dislocation 20 propagating through the third layer 52 to the side of the functional layer 10 is bent inside the first GaN layer 53. Thereby, the propagation in the stacking direction is suppressed. This is because the first GaN layer 53 formed on the single crystal AlGaN layer 51 is subjected to compressive stress (strain) and three-dimensionally grown. This is because the third layer 52 emphasizes selective growth.

  A first layer 54 is formed on the three-dimensionally grown island-shaped first GaN layer 53. A part of the first layer 54 is in contact with the third layer 52. In the region where the first layer 54 is in contact with the third layer 52, the propagation of most of the dislocations 20 generated from the AlN buffer layer 62 is interrupted. Thereby, the dislocation density of the third GaN layer 57 is significantly reduced.

As can be seen from FIG. 7B, the first layer 54 is formed in contact with the first oblique surface 53s of the first GaN layer 53. Thereby, the dislocations 20 propagating to the side of the functional layer 10 are blocked by the first layer 54. Thus, in the first layer 54 formed in contact with the first slope 53s, the dislocations 20 are likely to be reduced. For example, the first GaN layer 53 has a plurality of first dislocations 21 connected to the first slope 53s in the convex portion 53c. The dislocations 20 are continuous with the first dislocations 21 via the first layer 54, and the number of dislocations 20 in the second GaN layer 55 is smaller than the number of the plurality of first dislocations 21.
On the other hand, as shown in FIG. 7C, in the case of the first layer 54 formed on the main surface (first top surface 53t) perpendicular to the stacking direction, the propagation of dislocations 20 changes. I can not. Dislocations 20 propagate to the functional layer 10 side as they are.

FIG. 8A and FIG. 8B illustrate the nitride semiconductor device according to the first embodiment.
FIG. 8A is a cross-sectional TEM image of the nitride semiconductor device 110 and the nitride semiconductor wafer 210. FIG. 8 (b) is a schematic view drawn based on FIG. 8 (a). In FIG. 8B, the configurations of the third layer 52, the first GaN layer 53, the first layer 54, the second GaN layer 55, the second layer 56, and the third GaN layer 57 included in the stacked body 50 are schematically shown. It is drawn. The shape of the third layer 52, the shape of the first layer 54 and the shape of the second layer 56 are drawn in solid lines. Dislocations 20 in the region above the third layer 52 are schematically depicted by dotted lines.

  As can be seen from FIGS. 8A and 8B, the first layer 54 is formed in contact with the first slope 53s of the first GaN layer 53. As a result, dislocations 20 propagating to the side of the functional layer 10 are bent or shielded by the first layer 54. In the region of the first layer 54 formed on the main surface (first top surface 53t) perpendicular to the stacking direction, the change in the propagation of dislocations 20 is small. Dislocations 20 propagate to the inside of the second GaN layer 55. Some of the dislocations 20 propagating in the second GaN layer 55 are interrupted by the bending of dislocations in the second GaN layer 55 and the bending of dislocations in the second layer 56. Thereby, the propagation of dislocations 20 to the side of the functional layer 10 is blocked.

  Dislocation bending in the second GaN layer 55 occurs because, for example, the first layer 54 causes three-dimensional growth of the second GaN layer 55. Similar to the first layer 54 described above, the reduction of dislocations in the second layer 56 is likely to occur at the second slope 55s of the second GaN layer 55. For example, the second GaN layer 55 has a plurality of second dislocations 22 connected to the second slope 55s in the convex portion 55c. The dislocations 20 are continuous with the second dislocations 22 via the second layer 56, and the number of dislocations 20 in the third GaN layer 57 is smaller than the number of the plurality of second dislocations 22.

  Thus, on the island-like crystal formed of the first GaN layer 53 and the first layer 54, the island-like crystal having a size smaller than the size of the first GaN layer 53, the second GaN layer 55 Dislocations 20 can be significantly reduced by forming island-like crystals formed of the second layer 56).

  FIG. 9 is a graph illustrating the characteristics of the nitride semiconductor device according to the first embodiment. FIG. 9 is a graph showing the edge dislocation density De and the warpage WP of the substrate in the nitride semiconductor device according to the first embodiment. The edge dislocation density De is derived from the rocking curve half widths of the (0002) plane, the (0004) plane, the (10-11) plane, and the (20-22) plane in X-ray diffraction measurement. The warpage WP of the substrate is derived by measuring the warpage of the substrate 40 (silicon substrate) with a warpage measuring device.

The edge dislocation density De of the nitride semiconductor device 120 of the first example is 2.9 × 10 ⁻⁸ (/ cm ² ), and the nitride semiconductor devices 131, 132, and 133 of the first to third reference examples Lower than the edge dislocation density De. The warpage WP of the substrate 40 of the nitride semiconductor device 120 of the first embodiment is 29 μm in a concave shape, which is a relatively small amount of warpage. In the nitride semiconductor device 120 of the first embodiment, no crack occurs.

The edge dislocation density De of the nitride semiconductor device 131 of the first reference example is 5.9 × 10 ⁻⁸ (/ cm ² ), which is more than that of the edge dislocation density De of the nitride semiconductor device 120 of the first embodiment. Also high. The warpage WP of the substrate 40 of the nitride semiconductor device 131 of the first reference example is 45 μm in a concave shape, which is larger than the warpage WP of the nitride semiconductor device 131 of the first reference example. A crack was formed in the nitride semiconductor device 131 of the first reference example.

  The edge dislocation density De is high in the first reference example, which is considered to be because the second GaN layer 55 is formed in a layer, and the dislocation bending or shielding at the slope of the island-like crystal does not occur. The edge dislocation density De of the nitride semiconductor device 131 of the first reference example is approximately the same as the edge dislocation density De of the nitride semiconductor device 132 of the second reference example described later. It can be said that the reduction effect of the dislocation can hardly be obtained only by expanding the first GaN layer 53 in the same shape.

The edge dislocation density De of the nitride semiconductor device 132 of the second reference example is 5.5 × 10 ⁻⁸ (/ cm ² ), and the edge dislocation density De of the nitride semiconductor device 120 of the first embodiment is Also high. The warpage WP of the substrate 40 of the nitride semiconductor device 132 of the second reference example is 28 μm in a concave shape, which is a relatively low warpage amount. Cracks are not generated in the nitride semiconductor device 132 of the second reference example. Since the edge dislocation density De is about twice that of the first embodiment, the second GaN layer 55 is formed in an island shape, and the second layer 56 is formed in contact with the first slope 53s. Thus, it can be seen that dislocations can be reduced to about 50%.

The edge dislocation density De of the nitride semiconductor device 133 of the third reference example is 1.1 × 10 ⁻⁹ (/ cm ² ), and the edge dislocation density De of the nitride semiconductor device 120 of the first embodiment is Also high. The warpage of the substrate 40 of the nitride semiconductor device 133 of the third reference example is 55 μm in a concave shape, which is a warpage amount larger than the warpage WP of the nitride semiconductor device 131 of the first reference example. A crack was formed in the nitride semiconductor device 133 of the third reference example.
The edge dislocation density De in the third reference example is considered to be high because the first GaN layer 53 and the second GaN layer 55 are not formed like islands, and the bending effect of dislocation is weak.

  Thus, for example, by providing the third layer 52 in contact with the AlGaN layer 51 having a single crystal at least in part, the first GaN layer 53 is three-dimensionally grown. As a result, dislocations generated in the buffer layer 60 can be bent in a direction parallel to the stacking direction (Z-axis direction), and dislocations reaching the functional layer 10 can be reduced. In a region where the growth of the first GaN layer 53 is inhibited by the third layer 52, dislocations generated in the AlN buffer layer 62 are shielded by the third layer 52. This inhibits the propagation of dislocations to the upper part and can reduce dislocations.

  By forming the first layer 54 in contact with the first inclined surface 53 s of the first GaN layer 53, for example, dislocations 20 propagating to the side of the functional layer 10 are bent or blocked by the first layer 54. As a result, dislocations reaching the functional layer 10 can be significantly reduced.

  The second GaN layer 55 is formed in an island shape on the first GaN layer 53, and the second layer 56 is formed in contact with the second GaN layer 55, for example, dislocations penetrating the first GaN layer 53 and the first layer 54. Can be bent. Thereby, dislocations can be significantly reduced.

Next, an example of the effect of the shape of the first GaN layer 53 will be described.
FIG. 10 is a graph illustrating the characteristics of the nitride semiconductor device according to the first embodiment. FIG. 10 shows a change in edge dislocation density De of the nitride semiconductor device 120 when the height (thickness) t1 of the first GaN layer 53 is changed. The horizontal axis in FIG. 10 is the height (thickness) t1 of the first GaN layer 53. The height is for plotting the height (thickness) of the largest convex portion (island) in the concavo-convex shape seen in the cross-sectional SEM image. The height (thickness) t1 of the first GaN layer 53 is the thickness (growth time TM) of the third layer 52, the growth temperature GT of the first GaN layer 53, the growth rate GR of the first GaN layer 53, or the first GaN layer Vary with an ammonia feed of 53 (V / III ratio). Specifically, the thickness of the third layer 52 is increased (growth time TM is increased), the growth temperature GT of the first GaN layer 53 is decreased, the growth rate GR is increased, and the ammonia supply amount (V / III The height (thickness) of the first GaN layer 53 is increased by decreasing the ratio.

  As shown in FIG. 10, in the case where the first GaN layer 53 with a height (thickness) of 100 nm to 1200 nm is formed with respect to the case where the first GaN layer 53 is flat (the height t1 corresponds to 0 nm). It can be seen that the edge dislocation density De decreases. When the height (thickness) t1 is smaller than 100 nm (thin) or larger than 1200 nm (thick), the edge dislocation density De tends to increase.

  When the height (thickness) t1 is smaller than 100 nm, as illustrated in FIG. 2A, the formation of the first inclined surface 53s is insufficient and a flat surface perpendicular to the stacking direction (first apex) The ratio of the surface 53t) to the crystal surface is large. Therefore, it is considered that the effect of shielding dislocations in the first layer 54 can not be sufficiently obtained. Since the volume (surface area) of the crystal of the first GaN layer 53 is small (narrow), the propagation direction of dislocations in the crystal does not change, and the dislocation reduction effect in the first GaN layer 53 is considered to be small.

  On the other hand, when the height (thickness) t1 is higher than 1200 nm, crystals of adjacent first GaN layers 53 easily merge, and the region where the third layer 52 and the first layer 54 are in contact is narrowed. As a result, it is considered that the effect of shielding dislocations generated in the AlN buffer layer 62 is reduced, and the edge dislocation density De is increased.

  When the height (thickness) t1 forms a concavo-convex having a thickness (thick) higher than 1200 nm, a pit is formed on the surface of the third GaN layer 57. In the present embodiment, the thickness of the third GaN layer 57 is 2 μm, and it is difficult to planarize the island of the first GaN layer 53 having a thickness of half or more of the thickness of the third GaN layer 57. Conceivable. That is, the thickness of the third GaN layer 57 for obtaining the flat third GaN layer 57 is about twice the height (thickness) t1 of the first GaN layer 53. The optimum height t1 is not limited to 1200 nm, and is preferably 1/2 or less of the thickness of the third GaN layer 57. "Flat" means that an area of 90% or more is formed by a crystal plane parallel to the main surface.

  Thus, it can be seen that the edge dislocation density De decreases when the height (thickness) t1 of the first GaN layer 53 is 100 nm or more and 1200 nm or less. More preferably, the height (thickness) t1 of the first GaN layer 53 is 300 nm or more and 1/2 or less of the thickness of the third GaN layer 57. In the present embodiment, 1/2 of the thickness of the third GaN layer 57 is 1000 nm.

Next, an example of the effect of the thickness of the third layer 52 will be described.
FIGS. 11A and 11B are graphs illustrating the characteristics of the nitride semiconductor device according to the first embodiment.
FIG. 11A shows a change in edge dislocation density De of the nitride semiconductor device 120 when the growth time (thickness) TM of the third layer 52 is changed. The horizontal axis in FIG. 11A represents the growth time TM of the third layer 52, which corresponds to the thickness of the third layer 52.

  As shown in FIG. 11A, it is understood that the edge dislocation density De tends to be low when the growth time TM of the third layer 52 is 3 minutes or more and 17 minutes or less. If the growth time TM is shorter than 3 minutes, island-like crystals do not easily grow, and the first GaN layer 53 becomes layered crystals. In the third layer 52, pits were partially opened and closed. In this case, as illustrated in FIG. 2A, the formation of the first inclined surface 53s is insufficient, and the ratio of the flat surface (first top surface 53t) perpendicular to the stacking direction to the crystal surface is large. . Therefore, it is considered that the effect of shielding the dislocations in the first layer 54 is not sufficiently obtained, and the dislocations become high. On the other hand, when the growth time TM is longer than 17 minutes, the height of the first GaN layer 53 is about 1300 nm, and the flat third GaN layer 57 can not be obtained. Pits were formed on the surface of the third GaN layer 57. That is, it is considered that the first GaN layer 53 having a height of 1/2 or more of the thickness of the third GaN layer 57 is formed, and the edge dislocation density De tends to increase.

  In this example, when the growth time TM of the third layer 52 is 8 minutes, it corresponds to one atomic layer. That is, when the thickness of the third layer 52 is 0.4 atomic layer or more and 2.1 atomic layers or less, the edge dislocation density De decreases. The reason why the edge dislocation density De is high when the thickness of the third layer 52 is thinner than 0.4 atomic layer is that three-dimensional growth of the first GaN layer 53 does not occur, and the dislocation reduction effect can not be obtained. It is considered to be. On the other hand, when the thickness of the third layer 52 is thicker than 2.1 atoms, the edge dislocation density De increases because the density of the island-like crystals of the first GaN layer 53 decreases and the edge dislocation density De is formed thereon It is considered that this is because the flatness of the 3GaN layer 57 is reduced.

FIG. 11B shows the change in edge dislocation density De of the nitride semiconductor device 120 when the Si concentration CS in the third layer 52 is changed.
As described above with reference to FIG. 1A, the thickness of the third layer 52 can be estimated by direct observation with a transmission electron microscope image (TEM) or secondary ion mass spectrometry (SIMS). In the SIMS analysis, when the Si concentration in the layer is about 2 × 10 ²⁰ (/ cm ³ ), the thickness of the third layer 52 corresponds to one atomic layer. The Si concentration corresponds to a Si surface density of about 1 × 10 ¹⁵ (/ cm ² ) in terms of the surface density.

  In the case of SIMS analysis, the Si concentration may be observed to have a spread in the thickness (depth) direction depending on measurement conditions such as sputtering rate. In this case, for example, the Si concentration is reduced to a value of 10% with respect to the maximum value (maximum value) of the Si concentration in the region corresponding to each of the first layer 54, the second layer 56, and the third layer 52. The sum of the Si concentration up to the region (the integral value in the thickness direction of the Si atoms) is the number of Si atoms per unit area included in each of the first layer 54, the second layer 56, and the third layer 52 (Si plane Density) can be considered.

  The thickness of each of the first layer 54, the second layer 56, and the third layer 52 can be estimated using the sum of the Si concentrations (Si surface density). That is, when Si atoms in each of the first layer 54, the second layer 56 and the third layer 52 are uniformly substituted with Ga atoms (group III atoms) of the GaN layer, It can be estimated as the thickness of the GaN layer.

  In the present specification, when the number of Si atoms in each of the first layer 54, the second layer 56, and the third layer 52 is a number for replacing Ga atoms corresponding to one layer of the GaN layer, The thickness of each of the first layer 54, the second layer 56 and the third layer 52 is one atomic layer.

For example, the surface density of Ga atoms (III group atoms) in the (0001) plane in the GaN layer is about 1 × 10 ¹⁵ / cm ² . Therefore, when the surface density of Si in the film is about 1 × 10 ¹⁵ / cm ² , the thickness of the first layer 54 and the second layer 56 corresponds to one atomic layer.

In SIMS analysis, for example, when the peak value of Si concentration is 2 × 10 ²⁰ / cm ³ and the spread is 200 nm wide, the Si surface density is about 1 × 10 ¹⁵ / cm ² when converted to area density It corresponds to

That is, when the Si concentration in the layer is about 2 × 10 ²⁰ / cm ³ , the thickness of each of the first layer 54, the second layer 56, and the third layer 52 corresponds to one atomic layer. Therefore, “the dislocation density is reduced when the thickness of the third layer 52 is 0.4 atomic layers or more and 2.1 atomic layers or less” means that “Si concentration in the third layer 52 is 7.0 × 10”. ^The dislocation density decreases in the case of “ ¹⁹ / cm ³ or more and 4.5 × 10 ²⁰ / cm ³ or less”, and the dislocation density becomes low. And, when the Si surface density in the layer is 3.5 × 10 ¹⁴ / cm ² or more and 2.3 × 10 ¹⁵ / cm ² or less, the dislocation density becomes low.

Therefore, when the Si concentration in the third layer 52 is 7.0 × 10 ¹⁹ / cm ³ or more and 4.5 × 10 ²⁰ / cm ³ or less, it can be said that the edge dislocation density De tends to be low. It can be said that the edge dislocation density De tends to be low when the Si surface density in the layer is 3.5 × 10 ¹⁴ / cm ² or more and 2.3 × 10 ¹⁵ / cm ² or less.

FIG. 12A and FIG. 12B are graphs illustrating the nitride semiconductor device according to the first embodiment.
FIG. 12A and FIG. 12B show examples of SIMS analysis results of the nitride semiconductor device 110 (that is, the nitride semiconductor wafer 210) according to the present embodiment. In this example, it is measured at 5 nm intervals along the depth direction (stacking direction). The horizontal axis in FIG. 12A and FIG. 12B is the depth Zd (corresponding to the position in the Z-axis direction). The vertical axes in FIG. 12A and FIG. 12B are the Si concentration CS (atoms / cm ³ ).

In the example of FIG. 12A, the growth time TM of the third layer 52 is 8 minutes. This condition corresponds to the condition that the Si surface density in the third layer 52 is 1.0 × 10 ¹⁵ / cm ² . The growth time of the first layer 54 is 3 minutes. This condition corresponds to the condition that the Si surface density in the first layer 54 is 3.8 × 10 ¹⁴ / cm ² . The growth time of the second layer 56 is 3 minutes. This condition corresponds to the condition that the Si surface density in the second layer 56 is 3.8 × 10 ¹⁴ / cm ² .

In the example of FIG. 12 (b), the growth time TM of the third layer 52 is 10 minutes. This condition corresponds to the condition that the Si surface density in the third layer 52 is 1.2 × 10 ¹⁵ / cm ² . The other conditions are the same as in the example of FIG.

  As can be seen from FIG. 12A, in the area of the laminate 50, three peaks of Si are observed. For example, the Si concentration profile in the stacked body 50 includes first to seventh portions p1 to p7. The first to seventh portions p1 to p7 are stacked along the Z-axis direction.

The first portion p1 has a first Si concentration. The first Si concentration is 7.0 × 10 ¹⁹ / cm ³ or more and 4.5 × 10 ²⁰ / cm ³ or less.

The second portion p2 is provided on the upper side of the first portion p1. That is, the second portion p2 is provided between the first portion p1 and the functional layer 10. The second portion p2 has a second Si concentration. The second Si concentration is lower than the first Si concentration. The second Si concentration is, for example, less than 1 × 10 ¹⁷ / cm ³ . In the second portion p2, the Si concentration is relatively constant.

The third portion p3 is provided between the first portion p1 and the second portion p2. The third portion p3 has a third Si concentration. The third Si concentration is between the first Si concentration and the second Si concentration. The third Si concentration is, for example, 3 × 10 ¹⁸ / cm ³ or more and 5 × 10 ¹⁹ / cm ³ or less. In the third portion p3, the Si concentration is relatively constant.

The fourth portion p4 is provided between the third portion p3 and the second portion p2. The fourth portion p4 has a fourth Si concentration. The fourth Si concentration is between the third Si concentration and the second Si concentration. The fourth Si concentration is, for example, 1 × 10 ¹⁸ / cm ³ or more and 3 × 10 ¹⁹ / cm ³ or less. In the fourth portion p4, the Si concentration is relatively constant.

  The fifth portion p5 is provided between the first portion p1 and the third portion p3. The rate of change of the Si concentration with respect to thickness in the fifth portion p5 is higher than the rate of change with respect to the thickness of Si concentration in the third portion p3. In the fifth portion p5, the Si concentration changes rapidly.

  The sixth portion p6 is provided between the third portion p3 and the fourth portion p4. The rate of change of the Si concentration with respect to thickness in the sixth portion p6 is higher than the rate of change with respect to the thickness of Si concentration in the third portion p3. The rate of change of the Si concentration to thickness in the sixth portion p6 is higher than the rate of change to the Si concentration in the fourth portion p4. In the sixth portion p6, the Si concentration changes rapidly.

  The seventh portion p7 is provided between the fourth portion p4 and the second portion p2. The rate of change of the Si concentration with respect to the thickness in the seventh portion p7 is higher than the rate of change with respect to the thickness of the Si concentration in the fourth portion p4. The rate of change of the Si concentration to thickness in the seventh portion p7 is higher than the rate of change to the Si concentration in the second portion p2.

In the first portion p1, the width (the width in the thickness direction) of the peak of the Si concentration is narrow. The first portion p1 corresponds to the third layer 52.
In this example, the peak (maximum value) of the Si concentration in the first portion p1 is 2.6 × 10 ²⁰ / cm ³ . The width of the peak until the Si concentration is reduced to 10% of the peak value is about 120 nm. The total Si concentration (the integral value of the Si concentration in the thickness direction) in this region is 1.1 × 10 ¹⁵ / cm ² , which corresponds to the Si surface density of the third layer 52.

  The thickness (width) of the first portion p1 is, for example, 1 nm or more and 200 nm or less. If the thickness of the first portion p1 is thinner than 1 nm, three-dimensional growth of the first GaN layer 53 does not occur sufficiently. When the thickness of the first portion p1 is greater than 200 nm, the growth of the first GaN layer 53 is inhibited, the area of the slope is reduced, and the dislocation density reducing effect can not be sufficiently obtained.

The fifth portion p5 corresponds to the first GaN layer 53. The third portion p3 corresponds to the first layer 54. The Si concentration in the first layer 54 is 2.5 × 10 ¹⁹ / cm ³ . The Si concentration in at least a part of the first GaN layer 53 is 1 × 10 ¹⁷ / cm ³ or more and 1 × 10 ²⁰ / cm ³ or less. The first GaN layer 53 includes a protrusion 53 c, and the first layer 54 is provided on the protrusion 53 c. The diameter (width) 53 v (or 55 w) of the convex portion 53 c of the first GaN layer 53 is, for example, 50 nm or more and 1500 nm or less. In SIMS analysis, the area of analysis is larger than the size (area) of the convex portion. Therefore, the Si concentration by SIMS analysis is detected as an average value of the range including the plurality of projections (the range of the second layer 56, the second GaN layer 55, the first layer 54, and the first GaN layer 53). For example, when the third GaN layer 57 is provided, the range of the third GaN layer 57 is included in the range including the plurality of convex portions. Therefore, the Si concentration profile spreads in the thickness (depth) direction, the peak value becomes smaller than the actual Si concentration, and the profiles of the fifth portion p5 and the third portion p3 occur.

In this example, the peak of the Si concentration in the third portion p3 is about 2.5 × 10 ¹⁹ / cm ³ , and the width of the third portion p3 and the fifth portion p5 (the value of the Si concentration is 10% of the peak value (Corresponding to the width of the peak before reduction to about 200 nm). The total Si concentration (an integral value of the Si concentration in the thickness direction) in this region is 5.2 × 10 ¹⁴ / cm ² and corresponds to the Si surface density of the first layer 54.

  The thickness (width) of the fifth portion p5 is, for example, 100 nm or more and 1200 nm or less. The case where the thickness of the fifth portion p5 is thinner than 100 nm corresponds to the case where the height of the first GaN layer 53 is 100 nm or less. At this time, the formation of the first slope 53s is insufficient, and the reduction effect of the dislocation density is reduced. The case where the thickness of the fifth portion p5 is thicker than 1200 nm corresponds to the case where the height of the first GaN layer 53 is 1200 nm or more. For example, when the third GaN layer 57 is provided, the flatness of the third GaN layer 57 is likely to be degraded.

The sixth portion p6 corresponds to the second GaN layer 55. The fourth portion p4 corresponds to the second layer 56. In this example, the Si concentration in the second layer 56 is 1.5 × 10 ¹⁹ / cm ³ . The Si concentration in at least a part of the second GaN layer 55 is 1 × 10 ¹⁷ / cm ³ or more and 1 × 10 ²⁰ / cm ³ or less. The second GaN layer 55 includes a protrusion 55c, and the second layer 56 is provided on the protrusion. The diameter (width) 55 v (or 55 w) of the convex portion of the second GaN layer 55 is, for example, 10 nm or more and 1000 nm or less. The size of the second GaN layer 55 is smaller than the size of the first GaN layer 53.

In this example, the peak of the Si concentration in the fourth portion p4 is about 1.5 × 10 ¹⁹ / cm ³ , and the widths of the fourth portion p4 and the sixth portion p6 (the Si concentration is 10% of the peak value) (Corresponding to the width of the peak until it is reduced to a value of about 220 nm). The total Si concentration (the integral value of the Si concentration in the thickness direction) in this region is 2.5 × 10 ¹⁴ / cm ² , which corresponds to the Si surface density of the second layer 56.

  For example, the seventh portion p7 and the second portion p2 correspond to the third GaN layer 57. For example, it is considered that Si diffuses from at least one of the third layer 52, the first layer 54, and the second layer 56 to a part (a lower part) of the third GaN layer 57. This Si diffusion region is considered to correspond to the seventh portion p7.

  The thickness of the seventh portion p7 is, for example, 10 nm or more and 2500 nm or less. When the thickness of the seventh portion p7 is smaller than 10 nm, the bending or shielding effect of dislocations in the first layer 54 and the second layer 56 is not sufficiently obtained. When the thickness of the seventh portion p7 is greater than 2500 nm, the flatness of the third GaN layer 57 is likely to be degraded.

  For example, in the SIMS analysis, the presence of the third layer 52 can be determined by the presence of the first portion p1. The presence of the first layer 54 can be determined by the presence of the third portion p3. The presence of the second layer 56 can be determined by the presence of the fourth portion p4.

  As can be seen from FIG. 12B, three peaks of Si peaks are observed also in the range of the laminate 50 of this example. For example, the Si concentration profile in the stacked body 50 in the example shown in FIG. 12B is the same as that in the example of FIG.

The first portion p1 has a first concentration in which the Si concentration is 7.0 × 10 ¹⁹ / cm ³ or more and 4.5 × 10 ²⁰ / cm ³ or less. The second portion p2 has a second concentration with a Si concentration of, for example, less than 1 × 10 ¹⁷ / cm ³ . The third portion p3 has a third concentration of, for example, 3 × 10 ¹⁸ / cm ³ or more and 5 × 10 ¹⁹ / cm ³ of Si concentration. The fourth portion p4 has a fourth density of, for example, 1 × 10 ¹⁸ / cm ³ or more and 3 × 10 ¹⁹ / cm ³ or less.

  Similar to the example of FIG. 12A, for example, in the SIMS analysis, the presence of the first layer p1 makes it possible to determine the presence of the third layer 52. The presence of the first layer 54 can be determined by the presence of the third portion p3. The presence of the second layer 56 can be determined by the presence of the fourth portion p4.

FIG. 13A to FIG. 13D are views showing the nitride semiconductor device according to the embodiment.
13 (a) to 13 (c) are graphs showing examples of the results of energy dispersive X-ray spectroscopy (EDS analysis) of the nitride semiconductor device 110 (that is, the nitride semiconductor wafer 210) according to the embodiment. It is. FIG. 13 (d) shows the location of analysis in EDS analysis. FIG. 13 (d) shows the first analysis position Ap1, the second analysis position Ap2, and the third analysis position Ap3 on the cross-sectional TEM image as the EDS analysis locations. The first analysis position Ap1 corresponds to the position of the third layer 52. The second analysis position Ap2 corresponds to the position of the first layer 54. The third analysis position Ap3 corresponds to the position of the second layer 56.

  FIG. 13A shows the analysis result of the first analysis position Ap1. FIG. 13B shows the analysis result of the second analysis position Ap2. FIG. 13 (c) shows the analysis result of the third analysis position Ap3. The horizontal axis of FIG. 13A to FIG. 13C is energy Eg (keV: kilo electron volt). The vertical axes in FIG. 13A to FIG. 13C indicate the intensities Int (counts). The detection limit of Si in this EDS analysis is 1000 ppm.

In this example, the growth time TM of the third layer 52 is 8 minutes. This condition corresponds to the condition that the Si surface density in the third layer 52 is 1.0 × 10 ¹⁵ / cm ² . The growth time of the first layer 54 is 3 minutes. This condition corresponds to the condition that the Si surface density in the first layer 54 is 3.8 × 10 ¹⁴ / cm ² . The growth time TM of the second layer 56 is 3 minutes. This condition corresponds to the condition that the Si surface density in the second layer 56 is 3.8 × 10 ¹⁴ / cm ² .

  As can be understood from FIGS. 13A to 13C, in the present embodiment, Si is detected from the third layer 52, the first layer 54, and the second layer 56. The Si concentration in the third layer 52 is estimated to be about 4.6 (atomic /%). The Si concentration in the first layer 54 is estimated to be about 3.9 (atomic /%). The Si concentration in the second layer 56 is estimated to be about 4.2 (atomic /%). Thus, in the present embodiment, the Si concentration in each of the first layer 54, the second layer 56, and the third layer 52 is equal to or higher than the detection limit (1000 ppm). By setting the Si concentration in each of the first layer 54, the second layer 56, and the third layer 52 to 1000 ppm or more, a large effect of dislocation reduction can be obtained.

In the nitride semiconductor device and the nitride semiconductor wafer according to the present embodiment, dislocations 20 in the convex portion of the first GaN layer 53 are reduced in the first layer 54 provided on the slope (first slope 53s) of the convex portion. Do. In the second GaN layer 55 provided on the convex portion of the first GaN layer 53 and smaller in size than the first GaN layer 53, dislocations 20 in the convex portion of the first GaN layer 53 are further reduced. And as already demonstrated, in this embodiment, Si concentration in each of the 1st layer 54, the 2nd layer 56, and the 3rd layer 52 is more than a detection limit enough. The Si concentration in the third layer 52 is, for example, 7.0 × 10 ¹⁹ / cm ³ or more and 4.5 × 10 ²⁰ / cm ³ or less. The Si concentration in the first layer 54 is, for example, 1.0 × 10 ¹⁷ / cm ³ or more and 1.0 × 10 ²⁰ / cm ³ or less. The Si concentration in the second layer 56 is, for example, 1.0 × 10 ¹⁷ / cm ³ or more and 1.0 × 10 ²⁰ / cm ³ or less.

Second Embodiment
The present embodiment relates to a nitride semiconductor device.
FIG. 14A to FIG. 14D illustrate the nitride semiconductor device and the nitride semiconductor wafer according to the second embodiment.
FIG. 14A is a schematic cross-sectional view. FIG. 14B is a graph illustrating the Al composition ratio (C _Al ) in the stacked intermediate layer. FIG. 14C is a graph illustrating the growth temperature GT (formation temperature) in the stacked intermediate layer. FIG. 14D is a graph illustrating the lattice spacing Ld of the a axis in the laminated intermediate layer.

In FIGS. 14 (b), 14 (c) and 14 (d), the vertical axis is the position in the Z-axis direction. The horizontal axis of FIG. 14 (b) is the Al composition ratio C _Al . As shown in FIG. 14B, in the stacked intermediate layer 70, the Al composition ratio C _Al is substantially zero in the first GaN intermediate layer 71a and the second GaN intermediate layer 71b. Al Composition Ratio C _Al is substantially 1 in the first AlN intermediate layer 72a and the second AlN intermediate layer 72b. Al composition ratio C _Al is higher than 0 and lower than 1 in the first AlGaN intermediate layer 73a and the second AlGaN intermediate layer 73b.

  As shown in FIG. 14A, the nitride semiconductor device 130 and the nitride semiconductor wafer 230 according to the present embodiment include the buffer layer 60, the laminated intermediate layer 70, the laminated body 50, and the functional layer 10. including. The configuration described in regard to the first embodiment can be applied to each of the buffer layer 60, the stacked body 50, and the functional layer 10. Hereinafter, the laminated intermediate layer 70 will be described.

  The buffer layer 60 includes an AlGaN buffer layer 61. The AlGaN buffer layer 61 has the same characteristics as the AlGaN layer 51 in the stacked body 50 described above. The formation conditions and the like of the AlGaN buffer layer 61 are the same as those described for the AlGaN layer 51.

  The stacked intermediate layer 70 includes a first intermediate layer 70a and a second intermediate layer 70b. The first intermediate layer 70a includes a first GaN intermediate layer 71a, a first AlN intermediate layer 72a, and a first AlGaN intermediate layer 73a. The second intermediate layer 70b includes a second GaN intermediate layer 71b, a second AlN intermediate layer 72b, and a second AlGaN intermediate layer 73b. In the present embodiment, the configuration having the GaN intermediate layer 71, the AlN intermediate layer 72, and the AlGaN intermediate layer 73 is repeatedly laminated twice. The number of repetitions is not limited to two and may be repeated three or more times. The stacked intermediate layer 70 may have only the first intermediate layer 70a.

  As shown in FIG. 14D, in the laminated intermediate layer 70 of the embodiment, the lattice spacing Ld of the a axis (the lattice spacing in the direction perpendicular to the lamination direction (Z-axis direction)) is the GaN intermediate layer 71 And the size decreases sharply in the AlN intermediate layer 72.

  That is, the first GaN intermediate layer 71 a having a lattice constant larger than that of the AlGaN buffer layer 61 is formed on the AlGaN buffer layer 61. The formation temperature (substrate temperature) of the first GaN intermediate layer 71 a is, for example, about 1090 ° C., which is higher than the formation temperature of the AlGaN buffer layer 61. By setting the formation temperature of the first GaN intermediate layer 71a higher than the formation temperature of the AlGaN buffer layer 61, compressive strain (stress) is easily accumulated in the first GaN intermediate layer 71a. The thickness of the first GaN intermediate layer 71a is, for example, preferably 100 nm or more and 2000 nm or less, and for example, about 300 nm. The first GaN intermediate layer 71a is formed to be lattice-matched with the lattice constant of the AlGaN buffer layer 61 at the initial stage of growth, and is grown while being subjected to compressive strain (stress). Then, as the growth of GaN proceeds, strain (stress) is gradually relaxed, and the lattice spacing of GaN approaches the lattice constant of GaN in a state of not being strained.

  The first AlN intermediate layer 72a is formed on the first GaN intermediate layer 71a. The thickness of the first AlN intermediate layer 72a is, for example, preferably 5 nm or more and 100 nm or less, and for example, about 12 nm. The crystal growth temperature (substrate temperature) of the first AlN intermediate layer 72a is preferably lower than the temperature of the first GaN intermediate layer 71a, for example, 500 ° C. or more and 1050 ° C. or less, as shown in FIG. . The formation temperature (substrate temperature) of the first AlN intermediate layer 72a is, for example, 800.degree. At least a portion of the first AlN intermediate layer 72a is a single crystal. Therefore, lattice relaxation of the first AlN intermediate layer 72a is facilitated. As a result, it is difficult to receive tensile strain (stress) from the first GaN intermediate layer 71a serving as a base from the early stage of the formation of the first AlN intermediate layer 72a. As a result, the first AlN intermediate layer 72a can be formed so as to reduce the influence of strain (stress) from the first GaN intermediate layer 71a serving as the base. Thus, the lattice-relaxed first AlN intermediate layer 72a is formed on the first GaN intermediate layer 71a.

Subsequently, a first AlGaN intermediate layer 73a is formed on the first AlN intermediate layer 72a. Al composition ratio _{C Al} of the 1AlGaN intermediate layer 73a is lower than the Al composition ratio _{C Al} of the 1AlN intermediate layer 72a. AlGaN is formed to be lattice-matched to the lattice spacing of AlN at a thin state, ie, in the early stage of growth, and is grown under compressive strain. Then, as the growth of AlGaN progresses, the strain gradually relaxes, and the AlGaN approaches the lattice spacing of Al _x Ga _1-x N (0 <x <1) in a state where the strain is not received.

  The formation temperature (substrate temperature) of the first AlGaN intermediate layer 73a is higher than, for example, the formation temperature (substrate temperature) of the first AlN intermediate layer 72a and the formation temperature (substrate temperature) of the first GaN intermediate layer 71a. By setting the formation temperature of the first AlGaN intermediate layer 73a higher than the formation temperature of the first AlN intermediate layer 72a and the formation temperature of the first GaN intermediate layer 71a, it becomes difficult to relax the first AlGaN intermediate layer 73a. The formation temperature (substrate temperature) of the first AlGaN intermediate layer 73a is about 1120 ° C., for example. The composition ratio of Al of the first AlGaN intermediate layer 73a is set to be equal to or less than the relaxation rate α of the first AlN intermediate layer 72a.

  When the Al composition ratio of the first AlGaN intermediate layer 73a is larger than the relaxation rate α of the first AlN intermediate layer 72a, tensile strain (stress) is generated in the first AlGaN intermediate layer 73a, and a crack is easily generated. Lattice relaxation occurs and dislocations tend to increase.

  The relaxation rate α is relative to the absolute value of the difference between the lattice spacing dg of the first axis (eg, a-axis) of unstrained GaN and the lattice spacing da of the first axis (eg, a-axis) of unstrained AlN, A value defined by the ratio of the difference between the lattice spacing dg of the first axis (eg, a-axis) of unstrained GaN and the actual lattice spacing Da of the first axis (eg, a-axis) of the first AlN intermediate layer 72a. is there. The first axis is the stacking direction (one axis perpendicular to the Z-axis direction.

  The thickness of the first AlGaN intermediate layer 73a is preferably, for example, 5 nm or more and 100 nm or less. If the thickness of the first AlGaN intermediate layer 73a is thinner than 5 nm, it is difficult to obtain the effect of reducing dislocations. When the thickness of the first AlGaN intermediate layer 73a is greater than 100 nm, not only the effect of reducing dislocations is saturated but also cracks are likely to occur. The thickness of the first AlGaN intermediate layer 73a is more preferably less than 50 nm. Dislocation can be effectively reduced by setting the thickness of the first AlGaN intermediate layer 73a to less than 50 nm. The thickness of the second AlGaN intermediate layer 73b is, for example, about 25 nm.

  When the formation temperature (substrate temperature) of the first AlGaN intermediate layer 73a is 80 ° C. or more higher than the formation temperature (substrate temperature) of the first AlN intermediate layer 72a, the effect of growing to lattice match with the lattice constant of AlN is obtained more Be The effect of reducing dislocations can be obtained larger. The formation temperature of the first AlGaN intermediate layer 73a is, for example, about 1120.degree.

  Subsequently, a second GaN intermediate layer 71b is formed on the first AlGaN intermediate layer 73a. Furthermore, a second AlN intermediate layer 72b is formed on the second GaN intermediate layer 71b. Furthermore, a second AlGaN intermediate layer 73b is formed on the second AlN intermediate layer 72b. The second GaN intermediate layer 71b, the second AlN intermediate layer 72b, and the second AlGaN intermediate layer 73b can have the same configuration as the first GaN intermediate layer 71a, the first AlN intermediate layer 72a, and the first AlGaN intermediate layer 73a described above. I omit explanation.

  In the present embodiment, the second AlGaN intermediate layer 73 b is used as the AlGaN layer 51 in the stacked body 50. As described above, when the stacked intermediate layer 70 is provided, the AlGaN intermediate layer 73 closest to the functional layer 10 can be used as the AlGaN layer 51 in the stacked body 50.

Next, the characteristics of the nitride semiconductor device of the second example according to the present embodiment will be described.
The nitride semiconductor device 130 is the same as the nitride semiconductor device of the first embodiment described above except for the laminated intermediate layer 70, and therefore the description thereof is omitted. The laminated intermediate layer 70 of the nitride semiconductor device 130 is manufactured as follows.

  An AlN buffer layer 62 is formed, a substrate temperature is 1020 ° C., trimethyl gallium (TMGa) is supplied at a flow rate of 10 cc / min, TMAl is supplied at a flow rate of 50 cc / min, and ammonia is supplied at a flow rate of 2.5 L / min for 8 minutes. Thereby, the first AlGaN buffer layer 61a having an Al composition ratio of 0.55 is formed. The thickness of the first AlGaN buffer layer 61a is about 100 nm. Subsequently, the flow rate of TMG is changed to 17 cc / min, the flow rate of TMA to 30 cc / min, and supplied for 10 minutes. Thereby, the second AlGaN buffer layer 61 b having an Al composition ratio of 0.3 is formed. The thickness of the second AlGaN buffer layer 61 b is about 200 nm. Furthermore, the flow rate of TMG is changed to 20 cc / min, the flow rate of TMA to 15 cc / min, and supplied for 11 minutes. Thereby, the third AlGaN buffer layer 61c having an Al composition ratio of 0.15 is formed. The thickness of the third AlGaN buffer layer 61c is about 250 nm.

  Next, the substrate temperature is set to 1090 ° C., TMG is supplied at a flow rate of 56 cc / min, and ammonia is supplied at a flow rate of 40 L / min for 15 minutes. Thereby, the first GaN intermediate layer 71a is formed. The thickness of the first GaN intermediate layer 71a is about 300 nm.

  Next, the substrate temperature is set to 800 ° C., and TMA is supplied at a flow rate of 17 cc / min, and ammonia is supplied at a flow rate of 10 L / min for 3 minutes. Thereby, the first AlN intermediate layer 72a is formed. The thickness of the first AlN intermediate layer 72a is about 12 nm.

  Next, the substrate temperature is set to 1120 ° C., TMGa at a flow rate of 18 cc / min, TMAl at a flow rate of 6 cc / min, and ammonia at a flow rate of 2.5 L / min for 2.5 minutes. Thereby, the first AlGaN intermediate layer 73a having an Al composition ratio of 0.5 is formed. The thickness of the first AlGaN intermediate layer 73a is about 25 nm.

  Next, the substrate temperature is set to 1090 ° C., TMG is supplied at a flow rate of 56 cc / min, and ammonia is supplied at a flow rate of 40 L / min for 15 minutes. Thereby, the second GaN intermediate layer 71b is formed. The thickness of the second GaN intermediate layer 71b is about 300 nm.

  Next, the substrate temperature is set to 800 ° C., and TMA is supplied at a flow rate of 17 cc / min, and ammonia is supplied at a flow rate of 10 L / min for 3 minutes. Thereby, the second AlN intermediate layer 72b is formed. The thickness of the second AlN intermediate layer 72b is about 12 nm.

  Next, the substrate temperature is set to 1120 ° C., TMGa at a flow rate of 18 cc / min, TMAl at a flow rate of 6 cc / min, and ammonia at a flow rate of 2.5 L / min for 2.5 minutes. Thereby, the second AlGaN intermediate layer 73b having an Al composition ratio of 0.5 is formed. The thickness of the second AlGaN intermediate layer 73b is about 25 nm.

  Thus, the laminated intermediate layer 70 is formed, and the laminated body 50 and the functional layer 10 are formed on the laminated intermediate layer 70. The stacked body 50 and the functional layer 10 are formed under the same conditions as the conditions described above for the nitride semiconductor device 120.

When the edge dislocation density De of the nitride semiconductor element 130 to be produced is evaluated, it shows a low value of 2.1 × 10 ⁸ (/ cm ² ). The edge dislocation density De of the nitride semiconductor device 120 is 2.9 × 10 ⁸ (/ cm ² ), and the provision of the laminated intermediate layer 70 reduces the dislocation density to about 70%.

  When the warpage of the nitride semiconductor device 130 including the substrate 40 at room temperature is evaluated, the warpage is 10 μm in a convex shape. The warpage of the nitride semiconductor device 110 is a concave warpage of 29 μm. By providing the laminated intermediate layer 70, the compressive stress formed inside the nitride semiconductor device is increased, and the warpage is further reduced.

As described above, even if the stacked intermediate layer 70 is provided between the buffer layer 60 and the stacked body 50, a nitride semiconductor device having a low dislocation density can be obtained similarly.
By providing the laminated intermediate layer 70, warpage of the nitride semiconductor device 130 can be reduced, and cracks can be suppressed.

  FIG. 15 is a graph illustrating the characteristics of the nitride semiconductor device according to the second embodiment. FIG. 15 is an example of a reciprocal lattice mapping image of (11-24) plane. Reciprocal grid mapping is measured by x-ray diffraction measurements. The horizontal axis in FIG. 15 is the reciprocal Qx of the lattice spacing of the (11-20) plane in the direction perpendicular to the growth direction (stacking direction). The reciprocal Qx is a value proportional to the reciprocal of the lattice spacing of the a-axis. The vertical axis in FIG. 15 is the reciprocal Qz of the lattice spacing of the (0004) plane in the direction parallel to the growth direction (stacking direction). The reciprocal Qz is a value proportional to the reciprocal of the lattice spacing on the c-axis. In FIG. 15, the point of the diffraction peak Pg of the (11-24) plane of GaN (corresponding to the reciprocal of the lattice spacing of GaN) and the diffraction peak Pa of the (11-24) plane of AlN (the lattice spacing of the AlN buffer layer 62) Points corresponding to the reciprocal of) are shown. A dotted line L1 connecting the point of the diffraction peak Pg and the point of the diffraction peak Pa represents the characteristic of the reciprocal of the lattice spacing corresponding to the Al composition ratio of the AlGaN layer in the case of the Vegard rule.

  15, the diffraction peak point P61 of the (11-24) plane corresponding to the AlGaN buffer layer 61 and the diffraction of the (11-24) plane corresponding to the AlGaN intermediate layer 73 (or the AlGaN layer 51 in the laminated body) are shown. The peak point P73 is shown. Since the peaks of the AlGaN buffer layer 61 and the AlGaN intermediate layer 73 are confirmed, it can be understood that at least a part of the AlGaN buffer layer 61 and the AlGaN intermediate layer 73 is single crystal.

  In FIG. 15, when the peak (point P61 and point P73) of the measurement result of the lattice spacing of the AlGaN layer appears below the dotted line L1, the crystal has a compressive strain (compressive stress is occurring) Corresponding to). If the peaks (point P61 and point P73) of the measurement result appear above the dotted line L1, this corresponds to the crystal having a tensile strain (subject to tensile stress).

  As can be seen from FIG. 15, the point P61 of the peak due to the AlGaN buffer layer 61 appears below the dotted line L1. From this, it can be seen that the AlGaN buffer layer 61 has compressive strain (is under compressive stress).

  The stacked intermediate layer 70 and the stacked body 50 are formed on such an AlGaN buffer layer 61. Forming the stacked intermediate layer 70 and the stacked body 50 on the AlGaN buffer layer 61 increases the compressive stress (strain) formed in the stacked intermediate layer 70 and the stacked body 50. Thereby, the tensile strain produced in the temperature-falling process after crystal growth reduces, and the effect which suppresses a crack increases.

  As shown in FIG. 15, when the composition ratio z of Al of the AlGaN intermediate layer 73 (or the AlGaN layer 51 in the stacked body) is 0.5, a peak appears below the dotted line L1. From this, it can be understood that the AlGaN intermediate layer 73 (or the AlGaN layer 51 in the stacked body) has a compressive strain (is under compressive stress). Dislocation can be reduced by forming such an AlGaN intermediate layer 73 (or the AlGaN layer 51 in the stacked body).

  Thus, the stress (strain) of the AlGaN buffer layer 61, the AlGaN intermediate layer 73, and the AlGaN layer 51 in the stacked body 50 can be evaluated by X-ray diffraction measurement.

  Next, the lattice spacing (corresponding to the lattice spacing in the a-axis in this example) perpendicular to the stacking direction of the first AlN intermediate layer 72a is evaluated by X-ray diffraction measurement. As a result, the lattice spacing Da of the first AlN intermediate layer 72a is 0.3145 nm, which is a value larger than 0.3112 nm of the lattice spacing da of unstrained AlN. It can be seen that compressive stress (strain) is formed in the first AlGaN intermediate layer 73a formed on the first AlN intermediate layer 72a. The lattice spacing dg of the a-axis of unstrained GaN is 3189 nm. Therefore, the relaxation rate α of the first AlN intermediate layer 72a corresponds to 0.57.

  The relaxation rate α of the first AlN intermediate layer 72a is the lattice spacing dg of unstrained GaN with respect to the absolute value of the difference between the lattice spacing dg of unstrained GaN and the lattice spacing da of unstrained AlN, and the first AlN It is the ratio of the absolute value of the difference between the actual lattice spacing Da of the intermediate layer 72a. That is, the relaxation rate α of the first AlN intermediate layer 72a is | dg−Da | / | dg−da |. The lattice spacing dg of unstrained GaN corresponds to the lattice constant of GaN. The lattice spacing da of unstrained AlN corresponds to the lattice constant of AlN.

  In this example, the Al composition ratio of the first AlGaN intermediate layer 73a is 0.5, which is smaller than the relaxation rate α of the first AlN intermediate layer 72a. Therefore, compressive stress (strain) is formed in the first AlGaN intermediate layer 73a.

  On the other hand, for example, when the first AlGaN intermediate layer 73a having an Al composition ratio of 0.7 is formed, a crack occurs. When the same evaluation as described above is performed on this sample, it is understood that a tensile stress (strain) is formed in the first AlGaN intermediate layer 73a. That is, although an AlGaN layer with an Al composition ratio of 0.7 having a larger lattice spacing without strain than that of AlN is formed on the AlN layer, a tensile stress (strain) is formed in the AlGaN layer. . This is because the first AlN intermediate layer 73a is distorted, and the actual lattice spacing is larger than the undistorted lattice spacing. Thus, compressive stress (strain) can be formed in the AlGaN intermediate layer by forming the AlGaN intermediate layer having an Al composition ratio equal to or less than the relaxation rate α. Thereby, a high quality nitride semiconductor device with few cracks can be obtained.

  Such a nitride semiconductor device 130 can provide a high quality nitride semiconductor device with few dislocations formed on a silicon substrate.

FIG. 16 is a schematic cross-sectional view illustrating another nitride semiconductor device and a nitride semiconductor wafer according to the embodiment.
As shown in FIG. 16, another nitride semiconductor device 140 according to the embodiment includes a buffer layer 60, a stacked body 50, a stacked intermediate layer 70, and a functional layer 10. The stacked body 50 is provided on the buffer layer 60. A stacked intermediate layer 70 is provided on the stacked body 50. The functional layer 10 is provided on the laminated intermediate layer 70. The nitride semiconductor wafer 240 according to the present embodiment includes a substrate 40, a buffer layer 60, a laminated intermediate layer 70 and a laminated body 50. The nitride semiconductor wafer 240 may further include the functional layer 10. The configurations described for the nitride semiconductor device 130 can be applied to each of the substrate 40, the buffer layer 60, the stacked body 50, the stacked intermediate layer 70, and the functional layer 10.

  In the present embodiment, the third AlGaN buffer layer 61 c is used as the AlGaN layer 51 in the stacked body 50. As described above, when the AlGaN buffer layer 61 is provided, the AlGaN buffer layer 61 closest to the functional layer 10 can be used as the AlGaN layer 51 in the stacked body 50.

  In the nitride semiconductor device 140 (and the nitride semiconductor wafer 240), the stacked intermediate layer 70 includes a first intermediate layer 70a and a second intermediate layer 70b. The second intermediate layer 70b is provided on the first intermediate layer 70a.

  The first intermediate layer 70a includes a first GaN intermediate layer 71a, a first AlN intermediate layer 72a, and a first AlGaN intermediate layer 73a. The first AlN intermediate layer 72a is provided on the first GaN intermediate layer 71a. The first AlGaN intermediate layer 73a is provided on the first AlN intermediate layer 72a.

  The second intermediate layer 70b includes a second GaN intermediate layer 71b, a second AlN intermediate layer 72b, and a second AlGaN intermediate layer 73b. The second GaN intermediate layer 71 b is provided on the first AlGaN intermediate layer 73 a. The second AlN intermediate layer 72b is provided on the second GaN intermediate layer 71b. The second AlGaN intermediate layer 73b is provided on the second AlN intermediate layer 72b.

  The manufacturing method of the nitride semiconductor device 140 (and the nitride semiconductor wafer 240) can be applied by appropriately changing the manufacturing method described for the nitride semiconductor device 130.

In the nitride semiconductor element 140 and the nitride semiconductor wafer 240, the edge dislocation density De has a low value of 2.5 × 10 ⁸ (/ cm ² ).

  The warpage of the nitride semiconductor device 140 including the substrate 40 and the nitride semiconductor wafer 240 at room temperature is convex. The magnitude of warpage is 35 μm.

  On the other hand, the warpage in the nitride semiconductor device 110 including the substrate 40 and the nitride semiconductor wafer 210 is concave. The magnitude of warpage is 39 μm. Warpage in the nitride semiconductor device 130 including the substrate 40 and the nitride semiconductor wafer 230 is convex. The magnitude of warpage is 10 μm.

  By providing the laminated intermediate layer 70 on the laminated body 50 as in the nitride semiconductor device 140 and the nitride semiconductor wafer 240, the compressive stress (strain) formed inside the nitride semiconductor device is increased, and a crack is generated. The effect of reducing

FIG. 17A and FIG. 17B are schematic cross-sectional views illustrating other nitride semiconductor devices and nitride semiconductor wafers according to the embodiment.
FIG. 17 (b) is a diagram extracting a part of FIG. 17 (a).
As shown in FIG. 17A, the nitride semiconductor device 180 according to the embodiment includes the buffer layer 60, the stacked body 50a, and the functional layer 10. The stacked body 50a further includes a fourth layer 58, a fourth GaN layer 59, a fifth layer 64, and a fifth GaN layer 65, in addition to the stacked body 50 shown in FIG.

  In the embodiment, the third GaN layer 57 is provided on the second layer 56. The fourth layer 58 is provided on the third GaN layer 57. The fourth GaN layer 59 is provided on the fourth layer 58. The fifth layer 64 is provided on the fourth GaN layer 59. The fifth GaN layer 65 is provided on the fifth layer 64.

Each of the fourth layer 58 and the fifth layer 64 contains at least one of silicon (Si) and magnesium (Mg). Each of the fourth layer 58 and the fifth layer 64 may contain both Si and Mg. Each of the fourth layer 58 and the fifth layer 64 may include at least one of SiN and MgN. Each of the fourth layer 58 and the fifth layer 64 may include both SiN and MgN. Each of the fourth layer 58 and the fifth layer 64 may be a GaN layer (δ-doped layer) heavily doped with at least one of Si and Mg. Each of the fourth layer 58 and the fifth layer 64 may be a GaN layer (δ-doped layer) heavily doped with both Si and Mg.
The element contained in each of the fourth layer 58 and the fifth layer 64 is preferable because Si does not impair the conductivity of the n-type semiconductor layer 11 formed as a part of the functional layer 10. Below, the case where each of 4th layer 58 and 5th layer 64 contains Si is mentioned as an example, and is demonstrated.

  In the nitride semiconductor device 180 according to the embodiment, the third GaN layer 57 has an uneven surface (third slope 57s) inclined with respect to a plane (within the XY plane) perpendicular to the stacking direction (Z-axis direction). Containing island-like crystals. The surface (third slope 57s) inclined with respect to a plane (within the XY plane) perpendicular to the stacking direction (Z-axis direction) has facets such as (10-11) plane and (11-22) plane, for example. It is a face. The third slope 57s may not be a specific crystal plane. The third GaN layer 57 may have a dome shape. The third GaN layer 57 may have a plane perpendicular to the XY plane instead of the inclined surface.

  For example, the third GaN layer 57 is formed on the top surface (second top surface 55t) of the second GaN layer 55. For example, the third GaN layer 57 is formed on the slope (second slope 55s) of the second GaN layer 55. In the present specification, in the “the third GaN layer 57 is provided on the second GaN layer 55”, the third GaN layer 57 is on the top surface (the second top surface 55t) of the second GaN layer 55 and the second GaN layer. The state provided on at least one of the 55 slopes (the second slope 55s) is included.

  The height (thickness) t3 of the convex portion (third convex portion) 57c of the third GaN layer 57 is substantially the same as the height t2 of the convex portion 55c of the second GaN layer 55. Alternatively, the height t3 of the convex portion 57c of the third GaN layer 57 is smaller than the height t2 of the convex portion 55c of the second GaN layer 55. The definition of the height t2 of the convex portion 55c of the second GaN layer 55 can be applied to the definition of the height t3 of the convex portion 57c of the third GaN layer 57.

  As shown in FIGS. 17A and 17B, the length (width) of the bottom portion 57u of the convex portion 57c of the third GaN layer 57 in the parallel direction (first direction) with respect to the upper surface 51au of the AlGaN layer 51 ) 57 v is substantially the same as the length (width 55 v) of the bottom 55 u of the convex portion 55 c of the second GaN layer 55 in the first direction. Alternatively, the length (width) 57v of the bottom 57u of the protrusion 57c of the third GaN layer 57 in the first direction is greater than the length (width 55v) of the bottom 55u of the protrusion 55c of the second GaN layer 55 in the first direction. short. The length 57 w of the convex portion 57 c of the third GaN layer 57 in any tangential direction (second direction) on the slope (second slope 55 s) of the second GaN layer 55 is the same as that of the second GaN layer 55 in the second direction. The length is approximately the same as the length 55 w of the convex portion 55 c. Alternatively, the length 57 w of the convex portion 57 c of the third GaN layer 57 in the second direction is shorter than the length 55 w of the convex portion 55 c of the second GaN layer 55 in the second direction.

In other words, the size of the convex portion 57 c of the third GaN layer 57 is substantially the same as the size of the convex portion 55 c of the second GaN layer 55. Alternatively, the size of the convex portion 57 c of the third GaN layer 57 is smaller than the size of the convex portion 55 c of the second GaN layer 55.
On a plane (X-Y plane) perpendicular to the Z-axis direction (stacking direction), the number of third slopes 57s of the third GaN layer 57 per unit area is equal to the first number of first GaN layers 53 per unit area. More than the number of slopes 53s. On a plane (X-Y plane) perpendicular to the Z-axis direction (stacking direction), the number of third slopes 57s of the third GaN layer 57 per unit area is equal to the number of second GaN layers 55 per unit area. The number is approximately the same as the number of slopes 55s, or more than the number of second slopes 55s of the second GaN layer 55 per unit area.

  In this example, the third GaN layer 57 has a discontinuous island shape in the XY plane. A part of the fourth layer 58 is in contact with the third GaN layer 57. Another part of the fourth layer 58 is in contact with the second layer 56.

  The fourth GaN layer 59 includes an island-like crystal including asperities having a surface (fourth slope 59s) inclined with respect to a plane (within the XY plane) perpendicular to the stacking direction (Z-axis direction). The surface (fourth slope 59s) inclined with respect to the plane (within the XY plane) perpendicular to the stacking direction (Z-axis direction) has facets such as (10-11) plane and (11-22) plane, for example. It is a face. The fourth slope 59s may not be a specific crystal plane. The fourth GaN layer 59 may have a dome shape. The fourth GaN layer 59 may have a plane perpendicular to the XY plane instead of the inclined surface.

  For example, the fourth GaN layer 59 is formed on the top surface (second top surface 57t) of the third GaN layer 57. For example, the fourth GaN layer 59 is formed on the slope (third slope 57s) of the third GaN layer 57. In the specification of the present application, in the “the fourth GaN layer 59 is provided on the third GaN layer 57”, the fourth GaN layer 59 corresponds to the top surface (third top surface 57 t) of the third GaN layer 57 and the third GaN layer. The state provided on at least one of the 57 slopes (third slope 57s) is included.

  The height (thickness) t4 of the convex portion (fourth convex portion) 59c of the fourth GaN layer 59 is substantially the same as the height t3 of the convex portion 57c of the third GaN layer 57. Alternatively, the height t4 of the convex portion 59c of the fourth GaN layer 59 is smaller than the height t3 of the convex portion 57c of the third GaN layer 57. The definition of the height t2 of the convex portion 55c of the GaN layer 55 can be applied to the definition of the height t4 of the convex portion 59c of the fourth GaN layer 59.

  As shown in FIGS. 17A and 17B, the length (width) 59v of the bottom portion 59u of the convex portion 59c of the fourth GaN layer 59 in the first direction is equal to that of the second GaN layer 55 in the first direction. The length (width 55 v) of the bottom 55 u of the protrusion 55 c is substantially the same. Alternatively, the length (width) 59v of the bottom portion 59u of the convex portion 59c of the fourth GaN layer 59 in the first direction is longer than the length (width 55v) of the bottom portion 55u of the convex portion 55c of the second GaN layer 55 in the first direction. short. The length 59 w of the projection 59 c of the fourth GaN layer 59 in the second direction is substantially the same as the length 55 w of the projection 55 c of the second GaN layer 55 in the second direction. Alternatively, the length 59 w of the projection 59 c of the fourth GaN layer 59 in the second direction is shorter than the length 55 w of the projection 55 c of the second GaN layer 55 in the second direction.

In other words, the size of the convex portion 59 c of the fourth GaN layer 59 is substantially the same as the size of the convex portion 55 c of the second GaN layer 55. Alternatively, the size of the convex portion 59 c of the fourth GaN layer 59 is smaller than the size of the convex portion 55 c of the second GaN layer 55.
The number of fourth slopes 59s of the fourth GaN layer 59 per unit area on a plane (X-Y plane) perpendicular to the Z-axis direction (stacking direction) is the first number of first GaN layers 53 per unit area. More than the number of slopes 53s. On a plane (X-Y plane) perpendicular to the Z-axis direction (stacking direction), the number of fourth slopes 59s of the fourth GaN layer 59 per unit area is equal to the number of second GaN layers 55 per unit area. The number is approximately the same as the number of slopes 55s, or more than the number of second slopes 55s of the second GaN layer 55 per unit area.

  In this example, the fourth GaN layer 59 is in the form of discrete islands in the XY plane. A part of the fifth layer 64 is in contact with the fourth GaN layer 59. Another part of the fifth layer 64 is in contact with the fourth layer 58.

  The upper surface of the fifth GaN layer 65 is, for example, flat. The functional layer 10 is formed on the fifth GaN layer 65. The thickness t5 of the fifth GaN layer 65 is, for example, 100 nm or more and 5000 nm or less. The thickness t5 of the fifth GaN layer 65 is the Z-axis between the upper end of the fifth layer 64 and the upper surface of the fifth GaN layer 65 (in this example, the interface 10l between the stack 50a and the functional layer 10) It is the distance along the direction.

  Each of the configurations described for the nitride semiconductor device 110 can be applied to the substrate 40, the buffer layer 60, and the functional layer 10. In addition, the AlGaN layer 51, the third layer 52, the first GaN layer 53, the first layer 54, the second GaN layer 55, and the second layer 56 have the configuration described in regard to the nitride semiconductor device 110. Each can be applied. The configuration of the second GaN layer 55 of the nitride semiconductor device 110 can be applied to the other configurations of the third GaN layer 57 and the fourth GaN layer 59. In addition, the configuration of the second layer 56 of the nitride semiconductor device 110 can be applied to the other configurations of the fourth layer 58 and the fifth layer 64.

  FIGS. 17A and 17B also illustrate the configuration of the nitride semiconductor wafer 240 according to the present embodiment. The nitride semiconductor wafer 240 includes a substrate 40, a buffer layer 60, and a stacked body 50a. The nitride semiconductor wafer 240 may further include the functional layer 10. Each of the configurations described regarding the nitride semiconductor device 180 can be applied to the substrate 40, the buffer layer 60, the stacked body 50a, and the functional layer 10.

Next, an example of a method of manufacturing the nitride semiconductor device 180 and the nitride semiconductor wafer 240 according to the embodiment will be described.
The method of manufacturing the buffer layer 60, the AlGaN layer 51, the third layer 52, the first GaN layer 53, and the first layer 54 is as described for the method of manufacturing the nitride semiconductor device 120.

  Subsequently, TMGa is supplied at a flow rate of 56 cc / min and ammonia at a flow rate of 40 L / min for 37 seconds in a mixed atmosphere in which the substrate temperature is 1090 ° C. and the ratio of hydrogen and nitrogen is 2: 1. Thereby, the second GaN layer 55 is formed. The thickness of the second GaN layer 55 is, for example, about 100 nm.

Furthermore, the substrate temperature is returned to 1040 ° C. and silane (SiH ₄ ) at a concentration of 10 ppm is supplied at a flow rate of 350 cc / min and ammonia at a flow rate of 20 L / min for 3 minutes in a mixed atmosphere of hydrogen and nitrogen at a ratio of 2: 1. Do. Thereby, the second layer 56 is formed.

  By repeating these, the third GaN layer 57, the fourth layer 58, the fourth GaN layer 59, and the fifth layer 64 are formed.

  While maintaining the substrate temperature at 1090 ° C., TMGa is supplied at a flow rate of 56 cc / min and ammonia is supplied at a flow rate of 40 L / min for 60 minutes in a mixed atmosphere of a ratio of hydrogen and nitrogen of 2: 1. Thereby, the fifth GaN layer 65 is formed. The thickness of the fifth GaN layer 65 is, for example, about 2 μm.

Further, TMGa is supplied at a flow rate of 56 cc / min, ammonia is supplied at a flow rate of 40 L / min, and silane having a concentration of 10 ppm (SiH ₄ ) is supplied at a flow rate of 56 cc / min for 30 minutes. Thereby, an n-type GaN layer is formed. The Si concentration in the n-type GaN layer is, for example, 5 × 10 ¹⁸ (/ cm ³ ). The thickness of the n-type GaN layer is, for example, about 1 μm. The n-type GaN layer becomes the n-type semiconductor layer 11 (at least a part of the functional layer 15). Thereby, the nitride semiconductor device 180 or the nitride semiconductor wafer 240 according to the present embodiment can be formed.

Next, the characteristics of the nitride semiconductor device of the embodiment will be described with reference to the drawings.
FIG. 18A to FIG. 18D are schematic cross-sectional views illustrating a sample.
FIGS. 19A to 19D are cross-sectional SEM images showing examples of the buffer layer and the laminate.
FIG. 20 is a graph illustrating the characteristics of the nitride semiconductor device according to the embodiment.
FIG. 20 is a graph showing the edge dislocation density De in the nitride semiconductor device according to the embodiment. The edge dislocation density De is derived from the rocking curve half widths of the (0002) plane, the (0004) plane, the (10-11) plane, and the (20-22) plane in X-ray diffraction measurement.

  The nitride semiconductor devices 110, 111a, 180a, and 180 according to the embodiment are manufactured. The AlN buffer (buffer layer 60) and the AlGaN buffer (AlGaN layer 51) on the Si substrate are manufactured as described above. The nitride semiconductor devices 110, 111a, 180a, and 180 have different methods of forming the SiN-containing layer and the GaN layer. Hereinafter, a method of manufacturing the nitride semiconductor elements 110, 111a, 180a, and 180 will be described.

  The nitride semiconductor device 110 shown in FIG. 18A is formed to the AlGaN buffer and then to the third layer 52. Thereafter, the growth temperature is raised, and then the raw material is supplied for 1 minute to form the first GaN layer 53. After the temperature is lowered to form the first layer 54, the growth temperature is raised again and the raw material is supplied for 1 minute 15 seconds to form the second GaN layer 55. After the temperature is lowered to form the second layer 56, the temperature is raised to form the third GaN layer 57 by 2 μm, whereby the nitride semiconductor device 110 is obtained.

  The nitride semiconductor device 110a shown in FIG. 18B is formed up to the AlGaN buffer and then to the third layer 52. Thereafter, the growth temperature is raised, and then the raw material is supplied for 2 minutes and 30 seconds to form the first GaN layer 53. After the temperature is lowered to form the first layer 54, the growth temperature is raised again and the raw material is supplied for 37 seconds to form the second GaN layer 55. After the temperature is lowered to form the second layer 56, the temperature is raised to form the third GaN layer 2 μm to obtain the nitride semiconductor device 110a.

  As shown in FIGS. 18A and 18B, the size of the convex portion 53c of the first GaN layer 53 of the nitride semiconductor device 110 is the same as that of the convex portion 53c of the first GaN layer 53 of the nitride semiconductor device 110a. Smaller than the size. The size of the convex portion 55c of the second GaN layer 55 of the nitride semiconductor device 110 is larger than the size of the convex portion 55c of the second GaN layer 55 of the nitride semiconductor device 110a. The nitride semiconductor device 110 a is one of the examples of the nitride semiconductor device 110. That is, in the nitride semiconductor device 110 a, the size of the convex portion 55 c of the second GaN layer 55 is smaller than the size of the convex portion 53 c of the first GaN layer 53.

  The nitride semiconductor device 180 a shown in FIG. 18C is formed up to the AlGaN buffer, and then formed up to the third layer 52. Thereafter, the growth temperature is raised, and then the raw material is supplied for 2 minutes and 30 seconds to form the first GaN layer 53. After the temperature is lowered to form the first layer 54, the growth temperature is raised again and the raw material is supplied for 1 minute 15 seconds to form the second GaN layer 55. This is repeated four times to form the second layer 56, the third GaN layer 57, the fourth layer 58, and the fourth GaN layer 59. After the temperature is lowered to form the fifth layer 64, the temperature is raised to form the fifth GaN layer 2 μm, whereby the nitride semiconductor device 180a is obtained.

  The method of manufacturing the nitride semiconductor device 180 shown in FIG. 18 (d) is as described above with reference to FIGS. 17 (a) and 17 (b).

  As shown in FIGS. 18C and 18D, the size of the convex portion 53c of the first GaN layer 53 of the nitride semiconductor device 180 is the same as that of the convex portion 53c of the first GaN layer 53 of the nitride semiconductor device 180a. Smaller than the size. The size of the convex portion 55c of the second GaN layer 55 of the nitride semiconductor device 180 is smaller than the size of the convex portion 55c of the second GaN layer 55 of the nitride semiconductor device 180a. The size of the convex portion 57c of the third GaN layer 57 of the nitride semiconductor device 180 is smaller than the size of the convex portion 57c of the third GaN layer 57 of the nitride semiconductor device 180a. The size of the convex portion 59c of the fourth GaN layer 59 of the nitride semiconductor device 180 is smaller than the size of the convex portion 59c of the fourth GaN layer 59 of the nitride semiconductor device 180a. The nitride semiconductor device 180 a is one of the examples of the nitride semiconductor device 180. That is, in the nitride semiconductor device 180 a, the size of the convex portion 55 c of the second GaN layer 55 is smaller than the size of the convex portion 53 c of the first GaN layer 53. In the nitride semiconductor device 180a, the size of the convex portion 57c of the third GaN layer 57 is substantially the same as the size of the convex portion 55c of the second GaN layer 55, or smaller than the size of the convex portion 55c of the second GaN layer 55. The size of the convex portion 59 c of the fourth GaN layer 59 is substantially the same as the size of the convex portion 55 c of the second GaN layer 55 or smaller than the size of the convex portion 55 c of the second GaN layer 55.

FIG. 19A to FIG. 19D are views exemplifying SEM images obtained by observing a cross section cleaved along the (1-100) plane of the nitride semiconductor layer.
FIG. 19A is a view illustrating a cross-sectional SEM image of the nitride semiconductor device 110. FIG. 19B is a view illustrating a cross-sectional SEM image of the nitride semiconductor device 110a. FIG. 19C is a view illustrating a cross-sectional SEM image of the nitride semiconductor device 180a. FIG. 19D is a view illustrating a cross-sectional SEM image of the nitride semiconductor device 180.

As shown in FIG. 19D, in the nitride semiconductor device 180, the third layer 52, the first layer 54, the second layer 56, the fourth layer 58, and the fifth layer 64 are formed.
The first GaN layer 53 includes an unevenness having a surface (first inclined surface 53s) inclined with respect to a plane (X-Y plane) perpendicular to the stacking direction (Z-axis direction). The first GaN layer 53 includes island-like crystals that are discontinuous in a plane (within the XY plane) perpendicular to the stacking direction (Z-axis direction).
The second GaN layer 55 includes asperities having a surface (second slope 55s) inclined with respect to a plane (X-Y plane) perpendicular to the stacking direction (Z-axis direction). The second GaN layer 55 includes discontinuous island crystals in a plane (within the XY plane) perpendicular to the stacking direction (Z-axis direction).
The third GaN layer 57 includes asperities having a surface (third slope 57s) inclined with respect to a plane (X-Y plane) perpendicular to the stacking direction (Z-axis direction). The third GaN layer 57 includes an island-like crystal which is discontinuous in a plane (within the XY plane) perpendicular to the stacking direction (Z-axis direction).
The fourth GaN layer 59 includes an unevenness having a surface (fourth slope 59s) inclined with respect to a plane (X-Y plane) perpendicular to the stacking direction (Z-axis direction). The fourth GaN layer 59 includes discontinuous island crystals in a plane (within the XY plane) perpendicular to the stacking direction (Z-axis direction).

As shown in FIG. 20, the edge dislocation density De of the nitride semiconductor device 110 is 4.3 × 10 ⁻⁸ (/ cm ² ). The edge dislocation density De of the nitride semiconductor device 110 is lower than the edge dislocation density De of the nitride semiconductor devices 131, 132, and 133 of the first to third reference examples shown in FIG. The edge dislocation density De of the nitride semiconductor device 110 a is 4.6 × 10 ⁻⁸ (/ cm ² ). The edge dislocation density De of the nitride semiconductor device 110a is lower than the edge dislocation density De of the nitride semiconductor devices 131, 132, and 133 of the first to third reference examples.

The edge dislocation density De of the nitride semiconductor device 180 a is 2.8 × 10 ⁻⁸ (/ cm ² ). The edge dislocation density De of the nitride semiconductor device 180a is lower than the edge dislocation densities De of the nitride semiconductor devices 131, 132, and 133 of the first to third reference examples shown in FIG. The edge dislocation density De is lower than the edge dislocation density De of the nitride semiconductor device 110a.

The edge dislocation density De of the nitride semiconductor device 180 is 2.3 × 10 ⁻⁸ (/ cm ² ). The edge dislocation density De of the nitride semiconductor device 180 is lower than the edge dislocation density De of the nitride semiconductor devices 131, 132, and 133 of the first to third reference examples shown in FIG. The density is further lower than the edge dislocation density De, the edge dislocation density De of the nitride semiconductor device 110a, and the edge dislocation density De of the nitride semiconductor device 180a.

  This is considered to be large in the effect of shielding dislocation propagation because the number of repetitions of formation of the SiN-containing layer and the GaN layer is larger than that of the nitride semiconductor devices 110 and 110a. Further, in the nitride semiconductor device 180, not only the formation of the SiN-containing layer and the GaN layer is simply repeated, but also the first GaN layer 53 after the formation of the third layer 52 has a smaller shape, and the island-like upper C-plane region Is made smaller. Thereby, the GaN layer is disposed so that the shielding effect can be maximally exhibited by densely arranging and repeating island-shaped GaN while suppressing the dislocation which penetrates. This makes it possible to reduce the edge dislocation density De of the nitride semiconductor element 180 to about half of the edge dislocation density De of the nitride semiconductor elements 110 and 110a.

The edge dislocation density De of the nitride semiconductor device 180 will be further described.
In the nitride semiconductor device 180, the edge dislocation density De is considered to be reduced by the following.

  The first GaN layer 53 can be three-dimensionally grown, and the dislocations 80 generated in the buffer layer 60 can be bent in the first GaN layer 53 in a direction parallel to the stacking direction (Z-axis direction). Thereby, dislocations 80 reaching the upper layer (functional layer 15) can be reduced.

  In the region in which the growth of the first GaN layer 53 is suppressed by the third layer 52 (the region between the convex portions 53 c), the dislocation 80 generated in the buffer layer 60 is shielded by the third layer 52. Thereby, the propagation of dislocation 80 to the upper layer is suppressed, and dislocation 80 can be reduced.

  Furthermore, in the slope 53s of the convex portion 53c of the first GaN layer 53, the number of dislocations 80 propagating to the upper layer side is reduced. The dislocation 80 bends at the slope 53s. That is, in the first layer 54 provided on the inclined surface 53s, the dislocation 80 is bent. The propagation of dislocation 80 is interrupted at slope 53s. As a result, dislocations 80 reaching the upper layer can be significantly reduced.

  Thus, providing the first GaN layer 53 including the AlGaN layer 51, the third layer 52, and the convex portion 53c having the inclined surface 53s, the first layer 54, and the second GaN layer 55 in the stacked body 50. Dislocation density can be reduced. A nitride semiconductor device and a nitride semiconductor wafer with few dislocations can be obtained.

FIG. 21A to FIG. 21D are graphs illustrating the nitride semiconductor device according to the embodiment.
FIG. 22A and FIG. 22B are views illustrating the nitride semiconductor device according to the embodiment.

FIG. 21A shows an example of the SIMS analysis result of the nitride semiconductor device 110 (that is, the nitride semiconductor device wafer 210) according to the embodiment. FIG. 21 (b) shows an example of SIMS analysis result of the nitride semiconductor device 110 a according to the embodiment. FIG. 21C shows an example of the SIMS analysis result of the nitride semiconductor device 180a according to the embodiment. FIG. 21D shows an example of SIMS analysis results of the nitride semiconductor device 180 (that is, the nitride semiconductor device wafer 240) according to the embodiment.
In this example, it is measured at 5 nm intervals along the depth direction (stacking direction). The horizontal axes in FIG. 21A to FIG. 21D are the depth Zd (corresponding to the position in the Z-axis direction). The vertical axis on the left side of FIGS. 21A to 21D is the Si concentration CS (atoms / cm ³ ). The vertical axis on the left side of FIGS. 21A to 21D is the Al secondary ion intensity IA.

FIG. 22A and FIG. 22B are views showing the nitride semiconductor device according to the embodiment.
FIG. 22A is a graph showing an example of the result of energy dispersive X-ray spectroscopy (EDS analysis) of the nitride semiconductor device 180 (that is, the nitride semiconductor wafer 240) according to the embodiment. FIG. 22B shows the place of analysis in EDS analysis of the nitride semiconductor device 180 (that is, the nitride semiconductor wafer 240) according to the embodiment. FIG. 22 (b) shows the first analysis position Ap 11, the second analysis position Ap 12, the third analysis position Ap 13, and the fourth analysis position Ap 14 on the cross-sectional TEM image as the EDS analysis locations. The first analysis position Ap11 corresponds to the position of the third layer 52. The second analysis position Ap12 corresponds to the position of the first layer 54. The third analysis position Ap13 corresponds to the position of the second layer 56. The fourth analysis position Ap14 corresponds to the position of the fourth layer 58.

  FIG. 22A shows the analysis result of the first analysis position Ap11. The horizontal axis of FIG. 22 (a) is energy Eg (keV: kilo electron volt). The vertical axis in FIG. 22A is the intensity Int (counts). The detection limit of Si in this EDS analysis is 1000 ppm.

  As can be seen from FIGS. 21A and 21B, three peaks of Si peaks are observed in the range of the stacked body 50 in the nitride semiconductor devices 110 and 110a. For example, the Si concentration profile in the stacked body 50 includes first to seventh portions p1 to p7. The first to seventh portions p1 to p7 are stacked along the Z-axis direction. The first to seventh portions p1 to p7 are as described above with reference to FIGS. 12 (a) and 12 (b). For example, in the SIMS analysis, the presence of the third layer 52 can be determined by the presence of the first portion p1. The presence of the first layer 54 can be determined by the presence of the third portion p3. The presence of the second layer 56 can be determined by the presence of the fourth portion p4.

  On the other hand, as shown in FIGS. 21C and 21D, in the nitride semiconductor devices 180a and 180, five Si peaks are not observed in the range of the stacked body 50a. As can be seen from FIG. 21C, in the nitride semiconductor device 180a, it is possible to observe the Si peak of the first portion p1 and the Si peak of the third portion p3, while observing the other Si peaks. Can not. As can be seen from FIG. 21D, in the nitride semiconductor device 180, while the Si peak of the first portion p1 can be observed, the other Si peaks can not be observed.

As described above, in the SIMS analysis results of the nitride semiconductor devices 180a and 180 according to the embodiment, it may not be possible to observe the Si peak of five stages.
Even in such a case, as shown in FIG. 22B, the third layer 52, the first layer 54, the second layer 56, the fourth layer 58, and the fifth layer 64 are formed.

  As can be seen from FIG. 22 (a), in the embodiment, Si is detected from the third layer 52, the first layer 54, the second layer 56, and the fourth layer 58. The Si concentration in the third layer 52 is estimated to be about 4.8 (atomic /%). The Si concentration in the first layer 54 is estimated to be about 5.0 (atomic /%). The Si concentration in the second layer 56 is estimated to be about 5.3 (atomic /%). The Si concentration in the fourth layer is estimated to be about 5.6 (atomic /%). As described above, in the present embodiment, the Si concentration in each of the first layer 54, the second layer 56, the third layer 52, and the fourth layer 58 is equal to or higher than the detection limit (1000 ppm). By setting the Si concentration in each of the first layer 54, the second layer 56, the third layer 52, and the fourth layer 58 to 1000 ppm or more, a large effect of dislocation reduction can be obtained.

FIG. 23 is a schematic cross-sectional view illustrating another nitride semiconductor device according to the embodiment.
As shown in FIG. 23, the nitride semiconductor device 150 according to the embodiment further includes a first electrode 81 e and a second electrode 82 e. In the functional layer 10, an n-type semiconductor layer 11, a p-type semiconductor layer 12, and a light emitting layer 13 are provided. In this example, a low impurity concentration layer 11i is also provided. The nitride semiconductor device 150 is a semiconductor light emitting device.

  In this example, the n-type semiconductor layer 11 includes a first portion 11a and a second portion 11b. The second portion 11 b is aligned with the first portion 11 a in the XY plane. The light emitting layer 13 is provided between the second portion 11 b and the p-type semiconductor layer 12.

  The first electrode 81 e is electrically connected to the first portion 11 a of the n-type semiconductor layer 11. The second electrode 82 e is electrically connected to the p-type semiconductor layer 12. A current is supplied to the functional layer 10 through the first electrode 81 e and the second electrode 82 e, and light is emitted from the light emitting layer 13.

  In the nitride semiconductor device 150, by providing the stacked body 50 according to the embodiment, the dislocation density is low, and as a result, for example, high light emission efficiency can be obtained.

FIG. 24 is a schematic cross-sectional view illustrating another nitride semiconductor device according to the embodiment.
As shown in FIG. 24, also in the nitride semiconductor device 160 according to the embodiment, the first electrode 81 e and the second electrode 82 e are provided. In this example, after the functional layer 10 is formed on the stack 50, the substrate 40, the buffer layer 60, and the stack 50 are removed. For example, after the n-type semiconductor layer 11, the light emitting layer 13, and the p-type semiconductor layer 12 of the functional layer 10 are formed, the second electrode 82e is formed on the p-type semiconductor layer 12. Then, the first bonding metal layer 46 is formed on the second electrode 82 e. On the other hand, a support substrate 45 (for example, a silicon plate or a metal substrate) having the second bonding metal layer 47 formed on the main surface is prepared. The first bonding metal layer 46 and the second bonding metal layer 47 are bonded to each other. Thereafter, at least a portion of the substrate 40 used for crystal growth, the buffer layer 60, the laminated intermediate layer 70, and the laminated body 50 is removed. As the support substrate 45, for example, a metal layer (formed by plating or the like) may be used.

  In the nitride semiconductor device 160, the dislocation density is low by using the functional layer 10 formed on the stacked body 50 according to the embodiment, and as a result, for example, high light emission efficiency can be obtained.

FIG. 25 is a schematic cross-sectional view illustrating another nitride semiconductor device according to the embodiment.
As shown in FIG. 25, the nitride semiconductor device 170 according to the embodiment is a HEMT (High Electron Mobility Transistor) device. In the nitride semiconductor device 170, a first layer 16 and a second layer 17 are provided as the functional layer 10. Furthermore, a gate electrode 18g, a source electrode 18s, and a drain electrode 18d are provided.

The first layer 16 is provided on the stack 50. The second layer 17 is provided on the first layer 16. For the first layer 16, for example, undoped Al _α Ga _{1 -α} N (0 ≦ α ≦ 1) containing no impurity is used. For the second layer 17, for example, undoped or n-type Al _β Ga _1-β N (0 ≦ β ≦ 1, α <β) is used. For example, an undoped GaN layer is used for the first layer 16, and an undoped or n-type AlGaN layer is used for the second layer 17.

  The gate electrode 18 g, the source electrode 18 s, and the drain electrode 18 d are provided on the second layer 17. The source electrode 18s is separated from the drain electrode 18d in the X-Y plane. The source electrode 18 s and the drain electrode 18 d are in ohmic contact with the second layer 17. The gate electrode 18g is disposed on the second layer 17 between the source electrode 18s and the drain electrode 18d. The gate electrode 18 g is in Schottky contact with the second layer 17.

  The lattice constant of the second layer 17 is smaller than the lattice constant of the first layer 16. As a result, distortion occurs in the second layer 17 and piezoelectric polarization occurs in the second layer 17 due to the piezoelectric effect. Near the interface with the second layer 17 of the first layer 16, a two-dimensional electron gas 17 g is formed. In the nitride semiconductor device 170, by controlling the voltage applied to the gate electrode 18g, the two-dimensional electron gas concentration under the gate electrode 18g increases or decreases, and the current flowing between the source electrode 18s and the drain electrode 18d is controlled. Be done.

  In the nitride semiconductor device 180, by using the functional layer 10 formed on the stacked body 50 according to the embodiment, the dislocation density is low, and as a result, good electrical characteristics can be obtained.

  In the present embodiment, the stacked body 50 may be provided on the buffer layer 60, the stacked intermediate layer 70 may be provided on the stacked body 50, and the functional layer 10 may be provided on the stacked intermediate layer 70.

  In the present embodiment, the laminated intermediate layer 70 can be omitted as appropriate.

Third Embodiment
FIG. 26 is a flowchart illustrating the method for forming the nitride semiconductor layer according to the third embodiment.
As shown in FIG. 26, in the method for forming a nitride semiconductor layer according to the present embodiment, for example, the temperature of the substrate 40 is 1020 ° C. (fourth temperature), and a buffer including a nitride semiconductor provided on the substrate 40. A third gas including a gallium source (for example, TMGa), an aluminum source (for example, TMAl), and a nitrogen source (for example, ammonia) is supplied onto the layer 60, and Al _x Ga _1-x N (0 <x The AlGaN layer 51 of ≦ 1) is formed (step S105). For example, the fourth temperature is equal to or lower than the second temperature.

Furthermore, for example, the temperature of the substrate 40 is set to 1040 ° C. (second temperature) equal to or lower than the first temperature, and a silicon source (eg, silane) and a nitrogen source (eg, ammonia) are included on the upper surface 51au of the AlGaN layer 51 The second gas is supplied to form a third layer 52 containing Si at a concentration of 7.0 × 10 ¹⁹ / cm ³ or more and 4.5 × 10 ²⁰ / cm ³ or less (step S107).

  Further, for example, the temperature of the substrate 40 is 1090 ° C. (first temperature), and a first gas containing a gallium source (for example, TMG) and a nitrogen source (for example, ammonia) is supplied on the third layer 52, The first GaN layer 53 including the convex portion having the first inclined surface 53s inclined with respect to the upper surface 51au is formed (step S109).

  Further, for example, the temperature of the substrate 40 is set to 1040 ° C. (second temperature) equal to or lower than the first temperature, and the second GaN material including the silicon source (eg, silane) and the nitrogen source (eg, ammonia) on the first GaN layer 53 A gas is supplied to form a first layer 54 containing Si (step S111). For example, the second temperature is equal to or less than the first temperature. By setting the second temperature to the first temperature or less, shielding or bending of dislocations in the first layer is increased, and dislocations are easily reduced.

  Furthermore, for example, the temperature of the substrate 40 is set to 1120 ° C. (third temperature) equal to or higher than the first temperature, and the first source 54 contains a gallium source (eg, TMG) and a nitrogen source (eg, ammonia). A gas is supplied to form a second GaN layer 55 having a size smaller than the size of the first GaN layer 53, which is a second GaN layer 55 including a convex portion having a second slope 55s inclined with respect to the upper surface 51u S113).

  Further, for example, the temperature of the substrate 40 is set to 1040 ° C. (second temperature) equal to or lower than the first temperature, and the second GaN layer 55 contains a silicon source (for example, silane) and a nitrogen source (for example, ammonia) A gas is supplied to form a second layer 56 containing Si (step S115).

  Further, the third GaN layer 57 is formed on the second layer 56 (step S117).

Thus, a stacked body 50 including the AlGaN layer 51, the third layer 52, the first GaN layer 53, the first layer 54, the second GaN layer 55, the second layer 56, and the third GaN layer 57 is obtained. It forms (step S110).
According to the present formation method, it is possible to provide a method of forming a nitride semiconductor layer with less dislocations.

In the step of forming the third layer 52, the first layer 54, and the second layer 56 (step S107, step S111, and step S115), the second gas is used as a magnesium source (for example, Cp ₂ Mg: biscyclopentadi The third layer 52, the first layer 54, and the second layer 56 containing Mg can be formed by using a gas containing enil magnesium) and a nitrogen source (for example, ammonia).
In addition, the third layer 52, the first layer 54, and the second layer 56 containing both Si and Mg by using the second gas as a gas containing a silicon source, a magnesium source, and a nitrogen source (for example, ammonia). Can be formed respectively.

  In the method of forming a nitride semiconductor layer according to the present embodiment, the step of forming the first GaN layer 53 (step S109) to the step of forming the second layer 56 (step S115) are referred to as a set of steps. The steps may be repeated. According to this, the first GaN layer 53, the first layer 54, the second GaN layer 55, and the second layer 56 are repeatedly formed on the second layer 56.

  As shown in FIG. 26, the present formation method may further include a process (step S119) of forming the functional layer 10 on the third GaN layer 57. The present formation method may further include a process (step S101) of forming the buffer layer 60 on the substrate 40. The present formation method may further include a process (step S103) of forming the laminated intermediate layer 70 on the buffer layer 60. In this case, the AlGaN layer 51 is formed on the stacked intermediate layer 70 in the formation of the AlGaN layer 51 (step S105).

  In the embodiment, for the growth of the nitride semiconductor layer, for example, metal-organic chemical vapor deposition (MOCVD) method, metal-organic vapor phase epitaxy (MOVPE) method, molecular A molecular beam epitaxy (MBE) method, a halide vapor phase epitaxy (HVPE) method or the like can be used.

For example, in the case of using the MOCVD method or the MOVPE method, the following can be used as a raw material for forming each semiconductor layer. As a source of Ga, for example, TMGa (trimethylgallium) and TEGa (triethylgallium) can be used. As a source of In, for example, TMIn (trimethylindium) and TEIn (triethylindium) can be used. As a raw material of Al, for example, TMAl (trimethylaluminum) can be used. As a raw material of N, for example, NH ₃ (ammonia), MMHy (monomethylhydrazine), DMHy (dimethylhydrazine) and the like can be used. As a raw material of Si, SiH ₄ (monosilane), Si ₂ H ₆ (disilane) or the like can be used. As a raw material of Mg, Cp ₂ Mg (biscyclopentadienyl magnesium), EtCp ₂ Mg (bis ethyl cyclopentadienyl magnesium) or the like can be used.

FIG. 27 is a flowchart illustrating another forming method of the nitride semiconductor layer according to the third embodiment.
The steps from the step of forming the AlGaN layer 51 to the step of forming the first layer 54 are the same as the steps from step S105 to step S111 described above with reference to FIG. 26 (step S155 to step S161).

  Subsequently, for example, the temperature of the substrate 40 is set to 1090 ° C., and in a mixed atmosphere of a ratio of hydrogen and nitrogen of 2: 1, TMGa is supplied at a flow rate of 56 cc / min and ammonia at a flow rate of 40 L / min for 37 seconds. Thereby, the second GaN layer 55 is formed (step S163). The thickness of the second GaN layer 55 is, for example, about 100 nm.

Furthermore, the substrate temperature is returned to 1040 ° C. and silane (SiH ₄ ) at a concentration of 10 ppm is supplied at a flow rate of 350 cc / min and ammonia at a flow rate of 20 L / min for 3 minutes in a mixed atmosphere of hydrogen and nitrogen at a ratio of 2: 1. Do. Thereby, the second layer 56 is formed (step S165).

  Furthermore, the step of forming the second GaN layer 55 (step S163) and the step of forming the second layer 56 (step S165) are combined into one set of steps, and the set of steps is repeated. According to this, the second GaN layer 55 and the second layer 56 are repeatedly formed on the first layer 54. That is, the third GaN layer 57, the fourth layer 58, the fourth GaN layer 59, and the fifth layer 64 are formed (steps S167 to S173).

  Further, the fifth GaN layer 65 is formed on the fifth layer 64 (step S175).

  Thus, in another method of forming a nitride semiconductor layer according to the present embodiment, the step of forming the second GaN layer 55 (step S163) and the step of forming the second layer 56 (step S165) are a set of steps. And repeat the set of steps. According to this, the second GaN layer 55 and the second layer 56 are repeatedly formed on the first layer 54.

Thereby, the AlGaN layer 51, the third layer 52, the first GaN layer 53, the first layer 54, the second GaN layer 55, the second layer 56, the third GaN layer 57, and the fourth layer 58, A stacked body 50a including the fourth GaN layer 59, the fifth layer 64, and the fifth GaN layer 65 is formed (step S160).
According to the present formation method, it is possible to provide a method of forming a nitride semiconductor layer with less dislocation.

In the step of forming the third layer 52, the first layer 54, the second layer 56, the fourth layer 58, and the fifth layer 64 (steps S157, S161, S165, S169, and S173), The third layer 52 containing Mg, the first layer 54 by using a second gas as a gas containing a magnesium source (for example, Cp ₂ Mg: biscyclopentadienyl magnesium) and a nitrogen source (for example, ammonia) , The second layer 56, the fourth layer 58, and the fifth layer 64, respectively.
In addition, the third layer 52, the first layer 54, and the second layer 56 containing both Si and Mg by using the second gas as a gas containing a silicon source, a magnesium source, and a nitrogen source (for example, ammonia). , The fourth layer 58, and the fifth layer 64, respectively.

  As shown in FIG. 27, the formation method may further include a process (step S177) of forming the functional layer 10 on the fifth GaN layer 65. The present formation method may further include a process (step S151) of forming the buffer layer 60 on the substrate 40. The present formation method may further include a process (step S153) of forming the laminated intermediate layer 70 on the buffer layer 60. In this case, the AlGaN layer 51 is formed on the stacked intermediate layer 70 in the formation of the AlGaN layer 51 (step S155).

  According to the embodiment, it is possible to provide a nitride semiconductor device, a nitride semiconductor wafer, and a method of forming a nitride semiconductor layer with less dislocations.

In the present specification, “nitride semiconductor” means B _x In _y Al _z Ga _{1-xy z} N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z ≦ In the chemical formula 1), semiconductors of all compositions in which the composition ratios x, y and z are changed within the respective ranges are included. Furthermore, in the above chemical formula, one further containing a group V element other than N (nitrogen), one further containing various elements added for controlling various physical properties such as conductivity type, and unintentionally Those further containing various elements contained are also included in the “nitride semiconductor”.

  In the present specification, "vertical" and "parallel" include not only strictly vertical and strictly parallel but also include, for example, variations in manufacturing processes, etc., and they may be substantially vertical and substantially parallel. Just do it.

  The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, a substrate included in a nitride semiconductor device and a nitride semiconductor wafer, a buffer layer, a laminated intermediate layer, a laminated body, an AlGaN layer, a GaN layer, a first layer 54, a second layer 56, a third layer 52, a functional layer, etc. With regard to the specific configuration of each element of the present invention, the present invention is similarly included in the scope of the present invention as long as the same effect can be obtained by those skilled in the art appropriately selecting from known ranges.

  Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, based on the nitride semiconductor device, the nitride semiconductor wafer, and the method of forming a nitride semiconductor layer described above as the embodiment of the present invention, all nitride semiconductor devices that can be appropriately designed and implemented by those skilled in the art. Also, a nitride semiconductor wafer and a method of forming a nitride semiconductor layer are within the scope of the present invention as long as the scope of the present invention is included.

  Besides, within the scope of the concept of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that the changes and modifications are also within the scope of the present invention. .

  While certain embodiments of the present invention have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and the gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

DESCRIPTION OF SYMBOLS 10 ... Functional layer, 10 l ... Interface, 11 ... n-type semiconductor layer, 11a ... 1st part, 11b ... 2nd part, 11i ... Low impurity concentration layer, 12 ... p-type semiconductor layer, 13 ... Light emitting layer, 13a ... barrier layer, 13b ... well layer, 16 ... first layer, 17 ... second layer, 17g ... two-dimensional electron gas, 18d ... drain electrode, 18g ... gate electrode, 18s ... source electrode, 20, 21, 22 ... dislocation 40: substrate 45: supporting substrate 46: first bonding metal layer 47: second bonding metal layer 50: stacked body 51: AlGaN layer 51a: first AlGaN layer 51au: upper surface 51b: second AlGaN Layers 51c third AlGaN layer 52 third layer 53 first GaN layer 53c first convex portion 53s first slope 53t first top surface 53u bottom 53v diameter (width) , 53w ... length 54 54 first layer 55 second GaN layer 55 c second convex portion 55 s second slope 55 t second top surface 55 u bottom 55 v length (width) 55 w Length 56 second layer 57 third GaN layer 60 buffer layer 61 AlGaN buffer layer 61 a first AlGaN buffer layer 61 b second AlGaN buffer layer 61 c third AlGaN buffer layer 62 AlN Buffer layer 70 laminated intermediate layer 70 a first intermediate layer 70 b second intermediate layer 71 GaN intermediate layer 71 a first GaN intermediate layer 71 b second GaN intermediate layer 72 AlN intermediate layer 72 a ... first AlN intermediate layer, 72b ... second AlN intermediate layer, 73 ... AlGaN intermediate layer, 73a ... first AlGaN intermediate layer, 73b ... second AlGaN intermediate layer, 81e ... first Electrode 82e: Second electrode 110, 120, 130, 131, 132, 133, 150, 160, 170: Nitride semiconductor device, 210, 230: Nitride semiconductor wafer, Ap1: first analysis position, Ap2: second 2 analysis position, Ap3 ... 3rd analysis position, C _Al ... Al composition ratio, CS ... concentration ... Da ... lattice spacing, De ... edge dislocation density, GR ... growth rate, GT ... growth temperature, Int ... strength, L1 ... Dotted line, P61 ... point, P73 ... point, Pa ... diffracted peak, Pg ... diffracted peak, Qx ... inverse number, Qz ... inverse number, RN1, RN2 ... area, S01 ... first example, S02 ... second example, S03 ... third Example: TM growth time WP warping Zd depth lattice spacing dg lattice spacing p1 first portion p2 second portion p3 third portion p4 fourth portion p5 ... No. 5 parts, p6 ... 6th part, p 7 ... 7th part, t1, t2, t3 ... height

Claims (10)

A first GaN layer including a first convex portion, a first layer provided on the first GaN layer and containing Si, and a second GaN layer provided on the first layer and including a second convex portion, the second layer The length of the bottom of the convex portion is shorter than the length of the bottom of the first convex portion, the second layer provided on the second GaN layer and containing Si, and the third layer containing Si When, only contains the first 1GaN layer is provided between the first layer and the third layer, and the laminate,
A functional layer including a nitride semiconductor provided in the laminate;
Equipped with
Si concentration profile in the laminate, viewed contains three peaks,
The Si concentration profile is
A first portion of the first concentration having a Si concentration of 7 × 10 ¹⁹ / cm ³ or more and 4.5 × 10 ²⁰ / cm ³ or less;
A second portion of a second concentration in which the Si concentration is lower than the first concentration;
A third portion of a third concentration provided between the first portion and the second portion and having a Si concentration between the first concentration and the second concentration;
A fourth portion of a fourth concentration provided between the third portion and the second portion, the Si concentration being between the third concentration and the second concentration;
A fifth portion provided between the first portion and the third portion, wherein a rate of change of the Si concentration to the thickness is higher than a rate of change of the Si concentration to the thickness of the third portion;
The rate of change of the Si concentration to the thickness is higher than the rate of change of the Si concentration to the thickness of the third portion, provided between the third portion and the fourth portion. The sixth part, which is higher than the change rate,
A seventh portion provided between the fourth portion and the second portion, wherein a rate of change of the Si concentration to the thickness is higher than the rate of change of the Si concentration to the thickness of the fourth portion;
Have
A nitride semiconductor device , wherein in the energy dispersive X-ray spectrometry, the first layer, the second layer and the third layer have peaks of Si and N. The laminate further comprises an AlGaN layer of _{A l x Ga 1-x N} (0 <x ≦ 1),
Wherein the 1GaN layer is provided, et al is between the first layer and the AlGaN layer,
The third layer, the provided between the AlGaN layer and the first 1GaN layer, a nitride semiconductor device of 請 Motomeko 1 wherein. One of the three peaks comprises the first portion,
Another one of the three peaks comprises the third portion,
The nitride semiconductor device according to claim 1, wherein another one of the three peaks includes the fourth portion. The nitride semiconductor device according to any one of claims 1 to 3 , wherein the first layer and the second layer include SiN. A substrate,
A stacked body provided on the substrate, the first GaN layer including a first convex portion, the first layer provided on the first GaN layer and containing Si, and the second convex portion provided on the first layer A second GaN layer including the second GaN layer, wherein the length of the bottom of the second convex portion is shorter than the length of the bottom of the first convex portion, and is provided in the second GaN layer and contains Si. a second layer, seen including a third layer containing Si, a, the second 1GaN layer is provided between the first layer and the third layer, and the laminate,
Equipped with
Si concentration profile in the laminate, viewed contains three peaks,
The Si concentration profile is
A first portion of the first concentration having a Si concentration of 7 × 10 ¹⁹ / cm ³ or more and 4.5 × 10 ²⁰ / cm ³ or less;
A second portion of a second concentration in which the Si concentration is lower than the first concentration;
A third portion of a third concentration provided between the first portion and the second portion and having a Si concentration between the first concentration and the second concentration;
A fourth portion of a fourth concentration provided between the third portion and the second portion, the Si concentration being between the third concentration and the second concentration;
A fifth portion provided between the first portion and the third portion, wherein a rate of change of the Si concentration to the thickness is higher than a rate of change of the Si concentration to the thickness of the third portion;
The rate of change of the Si concentration to the thickness is higher than the rate of change of the Si concentration to the thickness of the third portion, provided between the third portion and the fourth portion. The sixth part, which is higher than the change rate,
A seventh portion provided between the fourth portion and the second portion, wherein a rate of change of the Si concentration to the thickness is higher than the rate of change of the Si concentration to the thickness of the fourth portion;
Have
A nitride semiconductor wafer , wherein in the energy dispersive X-ray spectrometry, the first layer, the second layer and the third layer have peaks of Si and N. The laminate further comprises an AlGaN layer of _{A l x Ga 1-x N} (0 <x ≦ 1),
Wherein the 1GaN layer is provided, et al is between the first layer and the AlGaN layer,
The third layer, the nitride semiconductor wafer which is provided,請 Motomeko 5 wherein between said first 1GaN layer and the AlGaN layer. One of the three peaks comprises the first portion,
Another one of the three peaks comprises the third portion,
The nitride semiconductor wafer according to claim 5 , wherein still another one of the three peaks includes the fourth portion. The nitride semiconductor wafer according to any one of claims 5 to 7 , wherein the first layer and the second layer include SiN. Forming a laminate on a substrate;
Forming a functional layer containing a nitride semiconductor in the laminate;
Equipped with
The step of forming the laminate comprises
Forming a first GaN layer including a first convex portion;
Forming a first layer containing Si on the first GaN layer;
Forming a second GaN layer including a second convex portion in the first layer, wherein a length of a bottom portion of the second convex portion is shorter than a length of a bottom portion of the first convex portion Process,
Forming a second layer containing Si on the second GaN layer;
Forming a third layer containing Si;
Including
The step of forming the first GaN layer includes forming the first GaN layer in the third layer,
Si concentration profile in the laminate, viewed contains three peaks,
The Si concentration profile is
A first portion of the first concentration having a Si concentration of 7 × 10 ¹⁹ / cm ³ or more and 4.5 × 10 ²⁰ / cm ³ or less;
A second portion of a second concentration in which the Si concentration is lower than the first concentration;
A third portion of a third concentration provided between the first portion and the second portion and having a Si concentration between the first concentration and the second concentration;
A fourth portion of a fourth concentration provided between the third portion and the second portion, the Si concentration being between the third concentration and the second concentration;
A fifth portion provided between the first portion and the third portion, wherein a rate of change of the Si concentration to the thickness is higher than a rate of change of the Si concentration to the thickness of the third portion;
The rate of change of the Si concentration to the thickness is higher than the rate of change of the Si concentration to the thickness of the third portion, provided between the third portion and the fourth portion. The sixth part, which is higher than the change rate,
A seventh portion provided between the fourth portion and the second portion, wherein a rate of change of the Si concentration to the thickness is higher than the rate of change of the Si concentration to the thickness of the fourth portion;
Have
A method of forming a nitride semiconductor layer , wherein in the energy dispersive X-ray spectrometry, the first layer, the second layer, and the third layer have peaks of Si and N. The step of forming the laminate, prior Symbol substrate _further comprises as engineering forming the AlGaN layer of _{Al x Ga 1-x N (} 0 <x ≦ 1),
The method of forming a nitride semiconductor layer according to claim 9 , wherein the step of forming the third layer includes forming a third layer in the AlGaN layer .