CN107978628B - GaN transistor covering nano-pillar potential barrier and preparation method thereof - Google Patents
GaN transistor covering nano-pillar potential barrier and preparation method thereof Download PDFInfo
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- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
The invention discloses a GaN transistor covering a nanometer column potential barrier and a preparation method thereof, wherein Al is distributed on the surface of the potential barrier layer of the transistorxGa1‑xAnd the N alloy nano columns correspond to the screw dislocations in the barrier layer one by one. The invention controls AlxGa1‑xThe TMGa flow and the V/III ratio in the process of N barrier growth can not only avoid the formation of V-shaped defects at the termination of screw dislocation, but also form 1-3nm Al at the termination of screw dislocationxGa1‑xN alloy nano-column. Because the alloy nano column fills the V-shaped defect at the threading dislocation termination position on the surface of the potential barrier, the effective potential barrier thickness at the threading dislocation termination position is increased, thereby effectively inhibiting the gate leakage current and improving the voltage-resistant characteristic of the transistor.
Description
Technical Field
The invention relates to semiconductor material growth and semiconductor device manufacturing, in particular to a GaN-based transistor covered with a nano-pillar and a potential barrier growth method thereof.
Background
The gallium nitride-based High Electron Mobility Transistor (HEMT) is made of AlxGa1-xN and GaN forming a heterojunction, AlxGa1-xThe spontaneous polarization of the interface of the N/GaN heterojunction and the discontinuity of the piezoelectric polarization form residual polarization charges so as to form a high-concentration two-dimensional electron gas at the interface. High quality AlxGa1-xThe growth technology of the N barrier layer is one of the key epitaxial technologies of the gallium nitride-based transistor. The GaN-based HEMT has the advantages of high concentration of two-dimensional electron gas (2DEG), high mobility, strong breakdown electric field and the like, and is widely applied to high-frequency and high-voltage microwave devices.
At present, the GaN substrate with high quality and large size is difficult to obtain and very expensive, so the growth of the GaN epitaxial material is generally realized by heteroepitaxy on silicon carbide, sapphire and silicon substrates. There is a large amount of GaN heteroepitaxial material due to the existence of lattice mismatchThreading dislocation (10)6-109/cm2) These dislocation defects also affect the electrical characteristics of the gan transistors and device reliability. Threading dislocations in heteroepitaxially grown gallium nitride materials are three types, edge dislocations, partial dislocations, and threading dislocations, with the threading dislocation device having the greatest effect on electrical properties. The threading dislocation usually forms V-shaped defects on the surface of the barrier to reduce the effective thickness of the barrier, and the center of the threading dislocation usually has a large number of defect vacancies to form a leakage channel and an electrical breakdown channel under high voltage under a gate electrode.
In order to reduce the influence of threading dislocation defects on the performance of the device, methods such as growing on a SiC substrate with small lattice mismatch, using a complex buffer layer structure, filtering threading dislocation by adopting a lateral epitaxial growth method to reduce the threading dislocation density of a barrier layer are generally adopted, and the methods are high in cost, complex in process and poor in controllability.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a transistor which enables a potential barrier to cover a nano-pillar by optimizing the growth condition of the potential barrier and a preparation method thereof.
The technical scheme adopted by the invention for solving the technical problems is as follows:
a GaN transistor covering a barrier of a nano-pillar comprises a substrate, a buffer layer, a channel layer and the barrier layer covering the nano-pillar from bottom to top, wherein a source electrode, a drain electrode and a grid electrode are arranged on the barrier layer, and the grid electrode is positioned between the source electrode and the drain electrode; the channel layer is formed by GaN heteroepitaxial growth, and the barrier layer is made of AlxGa1-xN heteroepitaxial growth, and Al distributed on the surface of the barrier layerxGa1-xN alloy nanopillar of which 0<x<1; the nano columns correspond to screw dislocation in the barrier layer one by one.
Optionally, the height of the nanopillars is 1-3 nm.
Optionally, the density of the nano-pillars is 106Per cm2-109Per cm2。
Optionally, the AlxGa1-xThe Al component of the N barrier layer is 15-22%.
Optionally, the source, the drain and the gate are made of metal, the source and the drain form ohmic contact with the barrier layer, and the gate forms schottky contact with the barrier layer.
A preparation method of the GaN transistor covering the nano-pillar barrier comprises the following steps:
(1) forming a buffer layer on a substrate;
(2) heteroepitaxially growing a GaN channel layer on the buffer layer;
(3) heteroepitaxially growing Al covering the nano-pillars on the channel layer by MOCVD methodxGa1-xThe growth conditions of the N barrier layer are as follows: TMGa is 180-300sccm, TMAl is 350-800sccm, NH3The flow rate is 8000-12000sccm, the surface temperature of epitaxial growth is 1000-1150 ℃, so that nano-columns are formed at the screw dislocation termination positions on the surface of the barrier layer in a one-to-one correspondence manner;
(4) forming a source electrode and a drain electrode on the surface of the barrier layer covering the nano column;
(5) a gate region is defined between the source and the drain to form a gate.
Optionally, in step (3), the barrier layer growth conditions are as follows: the surface temperature was 1070 ℃, TMAl flow rate was 400sccm, TMGa flow rate was 230sccm, and NH3 flow rate was 9000 sccm.
Optionally, the growth speed of the barrier layer is 1.8 μm/h-3 μm/h.
Optionally, the step (2) specifically includes the following sub-steps: respectively evaporating Ti/Al/Ni/Au multi-metal layers on two areas of the surface of the barrier layer by an electron beam evaporation method, wherein the thicknesses of the Ti/Al/Ni/Au layers are 20/150/70/100nm respectively; and annealing at 850-950 ℃ for 25-50 seconds to form ohmic contacts, thereby forming the source and the drain.
Optionally, in step (5), the gate is made of metal, and is deposited on the surface of the barrier layer covering the nano-pillars by magnetron sputtering, ion evaporation or electron beam evaporation, and forms schottky contact with the barrier layer.
The invention has the beneficial effects that:
1. the invention controls AlxGa1-xThe growth condition of the N barrier layer forms an alloy nano-pillar structure at the stop position of the screw dislocation on the surface of the barrier, and the alloy nano-pillar fills the vacancy of the screw dislocation center to inhibit the diffusion of electrode materials in the dislocation center in the annealing process of the gate electrode, thereby reducing the gate leakage channel.
2. The alloy nano-pillar structure is formed by stopping the screw dislocation on the surface of the potential barrier, so that the effective potential barrier thickness at the screw dislocation stopping position is effectively increased, the breakdown of the device at the screw dislocation position under high voltage is avoided, and the high-voltage working characteristic of the device is improved.
3. The manufacturing method is simple, has no special process requirements, has strong controllability, can effectively reduce the epitaxial cost and improve the high-voltage characteristic of the device, and is suitable for practical production and application.
Drawings
FIG. 1 is a schematic cross-sectional view of an embodiment of the present invention;
FIG. 2 is a schematic top view of the present invention;
FIG. 3 is a schematic cross-sectional view of a barrier with capped nano-pillars according to an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view of an uncovered nanopillar barrier according to an embodiment of the present invention;
FIG. 5 is an AFM view of a barrier surface with capped nanopillars according to an embodiment of the present invention;
FIG. 6 is an AFM image of an uncovered nanopillar barrier surface according to an embodiment of the present invention.
Detailed Description
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. All the figures of the present invention are merely schematic for easier understanding of the present invention, and the specific scale thereof can be adjusted according to design requirements. The conditions for barrier growth covering the nano-pillars are described herein as examples, and it is possible to form a barrier structure covering the nano-pillars by changing a single condition, all within the scope of the present disclosure. The sizes and numbers of the elements in the device fabrication process described herein are merely examples, which may be adjusted according to design requirements.
Referring to fig. 1 and 2, a GaN transistor covering a nano-pillar barrier comprises a substrate 1, a buffer layer 2 and a channel from bottom to topA layer 3 and a barrier layer 4 covering the nano-pillar 5, wherein the barrier layer 4 is provided with a source electrode 6, a drain electrode 7 and a grid electrode 8, and the grid electrode 8 is positioned between the source electrode 6 and the drain electrode 7; the channel layer 3 is formed by GaN hetero-epitaxial growth, and the barrier layer 4 is formed of AlxGa1-xN heteroepitaxial growth and Al distributed on the surface of the barrier layer 4xGa1-x N alloy nanopillar 5, wherein 0<x<1; the nano-pillars 5 correspond to the screw dislocations in the barrier layer 4 one to one. The preparation method comprises the following steps:
1) growing the GaN channel layer and the buffer layer: growing a buffer layer 2 (a nucleation layer and a transition layer) on the selected hetero-epitaxial substrate 1 (sapphire, SiC, Si) by using Metal Organic Chemical Vapor Deposition (MOCVD), and growing a 200nm GaN channel layer 3 on the buffer layer 2 at a high temperature (surface temperature 1040 ℃), as shown in FIG. 1;
2) continuing to epitaxially grow Al on the substrate 1)xGa1-xAn N barrier layer 4, wherein a higher MO flow rate is used to form alloy nano-pillars 5 at the screw dislocation termination positions on the surface of the barrier layer 4, wherein TMGa (Ttrymethylgalli μm) is 180-800 sccm (standard cubic meter per minute), TMAl (Trimethylmelamine μm) is 350-800sccm, and NH is added3The flow rate is 8000-12000sccm, and the surface temperature of epitaxial growth is 1000-1150 ℃; the barrier growth speed is about 1.8 mu m/h-3 mu m/h under the conditions of high MO flow and low V/III ratio, and AlxGa1-xThe Al content of the N barrier layer is 15-22%, and nano-pillars 5 with a thickness of 1-3nm are formed at the termination of threading dislocation under the condition of high growth rate, as shown in FIG. 1 and FIG. 2, wherein the density of nano-pillars is 106Per cm2-109Per cm2；
3) Preparing source and drain electrodes 6 and 7: preparing a photoresist pattern required by a source electrode and a drain electrode on a barrier layer by a photoetching method (electron beam Exposure (EBL) and ultraviolet exposure (UVL)), evaporating source and drain electrode metal (Ti/Al/Ni/Au, the thickness is 20nm/150nm/70nm/100nm) on the surface of a covering photoresist epitaxial wafer, stripping the metal in stripping liquid to obtain a source and drain electrode, and annealing the source and drain electrode by using a rapid annealing furnace (the annealing temperature is 850-; as shown in fig. 1 and 2, a source electrode 6, a drain electrode 7;
4) preparing gate metal: preparing a photoresist pattern required by a gate electrode on the surface of the barrier layer by a photoetching method (electron beam Exposure (EBL) and ultraviolet exposure (UVL)), evaporating a gate electrode (TiN with the thickness of 150-; as shown in fig. 1 and 2, a gate electrode 8.
The implementation of the invention is further described below, by way of example, in specific application examples:
examples of the invention
(1) The channel and buffer layers were grown on a 1mm 6 "silicon substrate using MOCVD. The buffer layer comprises a 200nm high temperature (surface temperature 1100 deg.C) AlN nucleation layer, 1.5 μm graded AlxGa1-xN transition layer (Al)0.75Ga0.25N-200nm，Al0.55Ga0.45N-400nm，Al0.25Ga0.75N-900nm, surface temperature 1060 deg.C) and then a 2.0 μm GaN high-resistance layer was grown (surface temperature 980 deg.C). The channel layer is a 200nm high-temperature (surface temperature 1060 ℃) GaN layer;
(2) and (3) continuously epitaxially growing an AlxGa1-xN barrier layer on the surface of the GaN channel layer in the step (1) by utilizing MOCVD. Adopting a higher MO flow rate, wherein TMGa is 220sccm, TMAl is 400sccm and NH is added3The flow rate of (2) is 9000 sccm; the barrier growth speed is about 2.2 mu m/h under the conditions of high MO flow and 270V/III ratio, and AlxGa1-xThe Al component of the N barrier layer is about 20 percent, and a 1-2nm nano-column with the diameter of 120-200nm is formed at the stop position of the screw dislocation under the condition of high growth rate, as shown in figure 5;
(3) indicating photoresist patterns (the edge distance of a source electrode and a drain electrode is 25 mu m, the electrode length is 20 mu m, and the electrode width is 100 mu m) needed by a source electrode and a drain electrode on the surface of an epitaxial wafer covering a nano column potential barrier by an ultraviolet photoetching method, and evaporating Ti/Al/Ni/Au (20nm/150nm/70nm/100nm) on the surface of the photoresist by using electron beam evaporation equipment; stripping metal in the stripping solution to obtain a source drain electrode, and annealing the source drain electrode at 900 ℃ for 50s (nitrogen flow of 6L/min)) by using a rapid annealing furnace to enable the source drain electrode and a potential barrier to form ohmic contact;
(4) preparing a photoresist pattern (with the gate length of 2 microns, the distance from a source electrode to the source electrode of 3 microns, the distance from a drain electrode to the drain electrode of 15 microns and the gate width of 100 microns) required by a gate electrode between a source electrode and a drain electrode on the surface of a potential barrier layer by an ultraviolet exposure method, evaporating the gate electrode (TiN, the thickness of 180nm) on the surface of a photoresist-covered epitaxial wafer by magnetron sputtering equipment, stripping metal in stripping liquid to obtain the gate electrode, and annealing the gate electrode for 40min at 650 ℃ in a nitrogen atmosphere by using a tubular annealing furnace to enable the gate electrode and the potential barrier to form Schottky contact;
v-type defects 5 'are formed at the threading dislocation termination of the surface of the barrier layer 4' under the conditions of generally low growth rate and high V/III ratio, as shown in fig. 4 and 6 (where fig. 4 is a schematic structural view and fig. 6 is an atomic force micrograph of the surface of the epitaxial wafer). Alloy nano-pillars can be formed at the screw dislocation termination of the barrier surface by using a low V/III ratio and high-speed barrier growth method as shown in fig. 3 and 5 (where fig. 3 is a schematic structural view and fig. 5 is an atomic force micrograph of the surface of an epitaxial wafer). The nano-column structure formed at the stopping position of the screw dislocation on the surface of the potential barrier can effectively inhibit the formation of a leakage channel under the gate electrode, and meanwhile, the effective potential barrier thickness of the screw dislocation accessory is increased by the nano-column, so that the barrier breakdown characteristic between the drain and the gate can be improved to a certain extent.
The disclosed method can also be used for growing Al in self-organizationxGa1-xThe N alloy nano column is used for inhibiting the upward propagation of GaN epitaxial thread dislocation and improving the epitaxial quality.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like, which are made within the spirit and principle of the present invention, such as simple changes to the process parameters in the examples, are included in the protection scope of the present invention.
Claims (9)
1. A GaN transistor covered with a nanopillar barrier, characterized in that: the transistor comprises a substrate, a buffer layer, a channel layer and a gate electrode from bottom to topThe barrier layer covers the nano column, a source electrode, a drain electrode and a grid electrode are arranged on the barrier layer, and the grid electrode is positioned between the source electrode and the drain electrode; the channel layer is formed by GaN heteroepitaxial growth, and the barrier layer is made of AlxGa1-xN heteroepitaxial growth and Al controlxGa1-xGrowth conditions of N barrier layer Al is formed at the stop of screw dislocation on the surface of the barrier layerxGa1-xN alloy nanopillar of which 0<x<1; the height of the nano-column is 1-3 nm.
2. The GaN transistor of claim 1 wherein: the density of the nano-column is 106Per cm2-109Per cm2。
3. The GaN transistor of claim 1 wherein: the Al isxGa1-xThe Al component of the N barrier layer is 15-22%.
4. The GaN transistor of claim 1 wherein: the source electrode, the drain electrode and the grid electrode are made of metal, the source electrode and the drain electrode form ohmic contact with the barrier layer, and the grid electrode and the barrier layer form Schottky contact.
5. A method for manufacturing a GaN transistor covering a nanopillar barrier according to any of claims 1 to 4, comprising the steps of:
(1) forming a buffer layer on a substrate;
(2) heteroepitaxially growing a GaN channel layer on the buffer layer;
(3) heteroepitaxially growing Al covering the nano-pillars on the channel layer by MOCVD methodxGa1-xThe growth conditions of the N barrier layer are as follows: TMGa is 180-300sccm, TMAl is 350-800sccm, NH3The flow rate is 8000-12000sccm, the surface temperature of epitaxial growth is 1000-1150 ℃, so that nano-columns are formed at the screw dislocation termination positions on the surface of the barrier layer in a one-to-one correspondence manner;
(4) forming a source electrode and a drain electrode on the surface of the barrier layer covering the nano column;
(5) a gate region is defined between the source and the drain to form a gate.
6. The method of claim 5, wherein: in the step (3), the growth conditions of the barrier layer are as follows: the surface temperature is 1070 ℃, the TMAl flow rate is 400sccm, the TMGa flow rate is 230sccm, NH3The flow rate 9000 sccm.
7. The method of claim 5, wherein: the growth speed of the barrier layer is 1.8-3 mu m/h.
8. The method of claim 5, wherein: the step (2) specifically comprises the following substeps:
respectively evaporating Ti/Al/Ni/Au multi-metal layers on two areas of the surface of the barrier layer by an electron beam evaporation method, wherein the thicknesses of the Ti/Al/Ni/Au layers are 20/150/70/100nm respectively;
and annealing at 850-950 ℃ for 25-50 seconds to form ohmic contacts, thereby forming the source and the drain.
9. The method of claim 5, wherein: in the step (5), the grid electrode is made of metal, is deposited on the surface of the barrier layer covering the nano column by a magnetron sputtering method, an ion evaporation method or an electron beam evaporation method, and forms Schottky contact with the barrier layer.
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| CN201711122190.4A CN107978628B (en) | 2017-11-14 | 2017-11-14 | GaN transistor covering nano-pillar potential barrier and preparation method thereof |
| PCT/CN2018/110707 WO2019095923A1 (en) | 2017-11-14 | 2018-10-17 | Gan transistor having barrier covered by nanopillars and preparation method therefor |
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| CN102263166A (en) * | 2011-07-27 | 2011-11-30 | 中国科学院长春光学精密机械与物理研究所 | Method for improving performances of AlGaN-based detector by using nano particles |
| JP6117010B2 (en) * | 2013-06-14 | 2017-04-19 | 株式会社東芝 | Nitride semiconductor device, nitride semiconductor wafer, and method of forming nitride semiconductor layer |
| CN106981506A (en) * | 2017-04-19 | 2017-07-25 | 华南理工大学 | Nano wire GaN HEMTs |
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| CN105322009A (en) * | 2015-11-09 | 2016-02-10 | 江西省昌大光电科技有限公司 | Gallium nitride based high electronic mobility transistor epitaxial structure and manufacturing method therefor |
| CN107978628B (en) * | 2017-11-14 | 2020-11-06 | 厦门市三安集成电路有限公司 | GaN transistor covering nano-pillar potential barrier and preparation method thereof |
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| CN102263166A (en) * | 2011-07-27 | 2011-11-30 | 中国科学院长春光学精密机械与物理研究所 | Method for improving performances of AlGaN-based detector by using nano particles |
| JP6117010B2 (en) * | 2013-06-14 | 2017-04-19 | 株式会社東芝 | Nitride semiconductor device, nitride semiconductor wafer, and method of forming nitride semiconductor layer |
| CN106981506A (en) * | 2017-04-19 | 2017-07-25 | 华南理工大学 | Nano wire GaN HEMTs |
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