WO2019095923A1 - Gan transistor having barrier covered by nanopillars and preparation method therefor - Google Patents

Gan transistor having barrier covered by nanopillars and preparation method therefor Download PDF

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WO2019095923A1
WO2019095923A1 PCT/CN2018/110707 CN2018110707W WO2019095923A1 WO 2019095923 A1 WO2019095923 A1 WO 2019095923A1 CN 2018110707 W CN2018110707 W CN 2018110707W WO 2019095923 A1 WO2019095923 A1 WO 2019095923A1
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barrier
barrier layer
nano
pillar
layer
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PCT/CN2018/110707
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French (fr)
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房育涛
叶念慈
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厦门市三安集成电路有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Definitions

  • the present invention relates to semiconductor material growth and semiconductor device fabrication, and more particularly to a GaN-based transistor covering a nanocolumn and a barrier growth method thereof.
  • Gallium nitride based high electron mobility transistor is a heterojunction formed by Al x Ga 1-x N and GaN, and the interface spontaneous polarization and piezoelectric polarization of the Al x Ga 1-x N/GaN heterojunction The discontinuity forms a residual polarization charge to form a high concentration of two-dimensional electron gas at the interface.
  • the growth technique of the high quality Al x Ga 1-x N barrier layer is one of the key epitaxial technologies of the gallium nitride based transistor.
  • GaN-based HEMTs are widely used in high-frequency and high-voltage microwave devices because of their high concentration of two-dimensional electrons (2DEG), high mobility, and strong breakdown electric field.
  • GaN epitaxial materials are very difficult to obtain and very expensive, so the growth of GaN epitaxial materials is generally achieved by heteroepitaxial growth on silicon carbide, sapphire and silicon substrates. Due to the existence of lattice mismatch, there are a large number of threading dislocations (10 6 -10 9 /cm 2 ) in the GaN heteroepitaxial material, and these dislocation defects also affect the electrical characteristics and device reliability of the gallium nitride transistor.
  • the threading dislocations in the heteroepitaxially grown gallium nitride material are three kinds of edge dislocations, partial dislocations and screw dislocations, and the electrical characteristics of the screw dislocation devices are the most affected. Screw dislocations typically form a V-type defect reduction barrier effective thickness on the surface of the barrier while the center of the screw dislocation typically has a large number of defect vacancies that form a leakage channel and a high voltage electrical breakdown channel under the gate electrode.
  • the threading dislocation reducing barrier In order to reduce the influence of screw dislocation defects on device performance, it is generally used to filter the threading dislocation reducing barrier by growing on a SiC substrate with a small lattice mismatch, using a complicated buffer layer structure, and using a lateral epitaxial growth method.
  • the method has the advantages of high cost, complicated process and poor controllability of the method such as the screw dislocation density of the layer.
  • An object of the present invention is to overcome the deficiencies of the prior art and to provide a transistor in which a barrier is covered by a barrier by optimizing barrier growth conditions and a method of fabricating the same.
  • a GaN transistor covering a nano-pillar barrier includes a substrate, a buffer layer, a channel layer, and a barrier layer covering the nano-pillar from bottom to top, and a source, a drain, and a gate are disposed on the barrier layer And a gate is located between the source and the drain;
  • the channel layer is formed by heteroepitaxial growth of GaN
  • the barrier layer is formed by Al x Ga 1-x N heteroepitaxial growth
  • An Al x Ga 1-x N alloy nanocolumn is distributed, wherein 0 ⁇ x ⁇ 1; the nanocolumn corresponds to the screw dislocations in the barrier layer.
  • the height of the nano-pillar is 1-3 nm.
  • the nano-column has a density of 10 6 /cm 2 -10 9 /cm 2 .
  • the Al component of the Al x Ga 1-x N barrier layer is 15%-22%.
  • the source, the drain and the gate are made of metal and the source and the drain form an ohmic contact with the barrier layer, and the gate and the barrier layer form a Schottky contact.
  • a method for fabricating a GaN transistor covering the nano-pillar barrier includes the following steps:
  • the growth conditions are: TMGa is 180-300 sccm, TMAl is 350-800 sccm, NH 3 The flow rate is 8000-12000 sccm, and the surface temperature of the epitaxial growth is 1000-1150 ° C, so that the nano-columns are formed one by one at the end of the screw dislocation on the surface of the barrier layer;
  • a gate region is defined between the source and the drain to form a gate.
  • the barrier layer growth conditions are: a surface temperature of 1070 ° C, a TMAl flow rate of 400 sccm, a TMGa flow rate of 230 sccm, and a NH 3 flow rate of 9000 sccm.
  • the barrier layer growth rate is 1.8 ⁇ m/h-3 ⁇ m/h.
  • the step (2) specifically includes the following sub-steps: depositing a Ti/Al/Ni/Au multi-metal layer on two regions of the surface of the barrier layer by electron beam evaporation, wherein The thickness of Ti/Al/Ni/Au is 20/150/70/100 nm, respectively; annealing at 850-950 ° C for 25-50 seconds forms an ohmic contact, forming the source and drain.
  • the gate is a metal, and is deposited on the surface of the barrier layer covering the nano-pillar and formed by the barrier layer by magnetron sputtering, ion evaporation or electron beam evaporation. Schottky contact.
  • the invention forms an alloy nano-pillar structure at the end of the screw dislocation at the surface of the barrier by controlling the growth conditions of the Al x Ga 1-x N barrier layer, because the alloy nano-pillar fills the vacancy hetero-grid at the center of the screw dislocation During electrode annealing, the electrode material diffuses at the center of the dislocation to reduce the gate leakage path.
  • the alloy nano-column structure is formed by the termination of the screw dislocation on the surface of the barrier, which effectively increases the effective barrier thickness at the end of the screw dislocation to avoid the breakdown of the device through the screw dislocation under high voltage, thereby improving the high-voltage operating characteristics of the device.
  • the production method is simple, no special process requirements, strong controllability, can effectively reduce the epitaxial cost and improve the high-voltage characteristics of the device, and is suitable for practical production applications.
  • FIG. 1 is a schematic cross-sectional view of an embodiment of the present invention
  • FIG. 2 is a schematic top plan view of an embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional view showing a barrier of a covered nano-pillar according to an embodiment of the present invention
  • FIG. 4 is a schematic cross-sectional view showing a barrier of a non-covered nano-pillar according to an embodiment of the present invention
  • FIG. 5 is an AFM diagram of a barrier surface of a covered nano-pillar according to an embodiment of the present invention.
  • FIG. 6 is an AFM diagram of a non-covered nanocolumn barrier surface according to an embodiment of the present invention.
  • a GaN transistor covering a nano-pillar barrier includes a substrate layer 1, a buffer layer 2, a channel layer 3, and a barrier layer 4 covering the nano-pillars 5 from bottom to top, and a barrier layer 4
  • the source electrode 6, the drain electrode 7 and the gate electrode 8 are disposed, and the gate electrode 8 is located between the source electrode 6 and the drain electrode 7; the channel layer 3 is formed by heteroepitaxial growth of GaN, and the barrier layer 4 is formed.
  • the preparation method comprises the following steps:
  • Buffer layer 2 (nucleation layer and transition layer) is grown on selected heteroepitaxial substrate 1 (sapphire, SiC, Si) by metal organic chemical vapor deposition (MOCVD) a 200 nm GaN channel layer 3 is grown on the buffer layer 2 at a high temperature (surface temperature 1040 ° C), as shown in FIG. 1;
  • the epitaxial growth of the Al x Ga 1-x N barrier layer 4 is continued on 1), in order to form the alloy nanocolumn 5 at the end of the screw dislocation of the barrier layer 4, a higher MO flow rate is employed, wherein TMGa (Ttrimethylgalli ⁇ m) ) is 180-300sccm (standard cubic meters per minute), TMAl (Trimethylal ⁇ mini ⁇ m) is 350-800sccm, while the flow rate of NH 3 is 8000-12000sccm, the surface temperature of epitaxial growth is 1000-1150 ° C; at high MO flow rate and low V / Under the condition of III ratio, the barrier growth rate is about 1.8 ⁇ m/h-3 ⁇ m/h, and the Al component of the Al x Ga 1-x N barrier layer is about 15%-22%. Under the condition of high growth rate, the screw position The nano-column 5 of 1-3 nm is formed at the wrong end, as shown in FIG. 1 and FIG. 2, wherein the density of the nano-pillar is 106/cm
  • Source-drain electrodes 6, 7 Photolithographic methods (electron beam exposure (EBL), ultraviolet exposure (UVL)) are used to prepare the photoresist pattern required for the source-drain electrodes in the barrier layer table, in the overlying photoresist extension
  • EBL electron beam exposure
  • UVL ultraviolet exposure
  • the surface of the sheet is evaporated to the source and drain electrode metal (Ti/Al/Ni/Au, thickness 20nm/150nm/70nm/100nm), the metal is stripped in the stripping solution to obtain the source and drain electrodes, and the source and drain electrodes are annealed by a rapid annealing furnace (annealing temperature) 850-950 ° C, annealing time 35-60s, annealing is atmospheric nitrogen (nitrogen flow rate 6L / min); as shown in Figures 1 and 2, source electrode 6, drain electrode 7;
  • annealing temperature 850-950 ° C
  • annealing time 35-60s annealing is atmospheric nitrogen (nitrogen flow
  • Preparing the gate metal preparing a photoresist pattern required for the gate electrode on the surface of the barrier layer by a photolithography method (electron beam exposure (EBL), ultraviolet exposure (UVL)), and covering the photoresist with a magnetron sputtering device Epitaxial wafer evaporation electrode (TiN, thickness 150-200nm), stripping the metal in the stripping solution to obtain the gate electrode, annealing the gate electrode by annealing furnace (annealing temperature 600-800 ° C, annealing time 20-60 min, annealing atmosphere is Nitrogen (nitrogen flow rate 20 L/min)); as shown in Figs. 1 and 2, the gate electrode 8.
  • a photolithography method electron beam exposure (EBL), ultraviolet exposure (UVL)
  • Epitaxial wafer evaporation electrode Epitaxial wafer evaporation electrode (TiN, thickness 150-200nm)
  • annealing the gate electrode by annealing furnace (annealing temperature 600-800 °
  • the buffer layer includes a high temperature (surface temperature of 1100 ° C) AlN nucleation layer of 200 nm, a 1.5 ⁇ m compositionally tapered Al x Ga 1-x N transition layer (Al 0.75 Ga 0.25 N-200 nm, Al 0.55 Ga 0.45 N-400 nm , Al 0.25 Ga 0.75 N-900 nm, surface temperature 1060 ° C) and then a 2.0 ⁇ m GaN high resistance layer (surface temperature 980 ° C) was grown.
  • the channel layer is a high temperature (surface temperature of 1060 ° C) GaN layer of 200 nm;
  • the Al x Ga 1-x N barrier layer is epitaxially grown on the surface of the GaN channel layer of (1) by MOCVD.
  • a higher MO flow rate is used, wherein TMGa is 220 sccm, TMAl is 400 sccm, and NH 3 flow rate is 9000 sccm; at high MO flow rate, V/III ratio is 270, the barrier growth rate is about 2.2 ⁇ m/h, and Al x Ga 1
  • the Al composition of the -x N barrier layer is about 20%, and a nano-column of 1-2 nm is formed at the end of the screw dislocation at a high growth rate, and the diameter is 120-200 nm, as shown in FIG. 5;
  • the photoresist pattern required for preparing the gate electrode between the source and drain electrodes on the surface of the barrier layer by ultraviolet exposure method (gate length 2 ⁇ m, distance from source to source 3 ⁇ m, distance from drain to 15 ⁇ m, gate width 100 ⁇ m), using magnetic control
  • the sputtering apparatus covers the photoresist epitaxial wafer vapor-deposited gate electrode (TiN, thickness: 180 nm), strips the metal in the stripping solution to obtain a gate electrode, and anneals the gate electrode in a tubular annealing furnace at 650 ° C for 40 min in a nitrogen atmosphere.
  • the gate electrode and the barrier form a Schottky contact;
  • FIG. 4 is a schematic structural view
  • Figure 6 is an atomic force micrograph of the surface of the epitaxial wafer. Alloy nanopillars can be formed at the end of the screw dislocation at the barrier surface by using a low V/III ratio and high-speed barrier growth method as shown in FIGS. 3 and 5 (wherein FIG. 3 is a schematic structural view, and FIG. 5 is an epitaxial wafer surface). Atomic force micrograph).
  • the formation of the leakage channel under the gate electrode can be effectively suppressed.
  • the effective barrier thickness of the screw dislocation attachment is increased due to the nano-column, and the barrier breakdown between the drain and the gate is obtained. Will also get a certain increase.
  • the method disclosed in the present invention can also be used to grow Al x Ga 1-x N alloy nanocolumns in self-organizing and to suppress GaN epitaxial thread misalignment to improve epitaxial quality.

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Abstract

Disclosed are a GaN transistor having a barrier covered by nanopillars and a preparation method therefor. AlxGa1-xN alloy nanopillars are distributed on the surface of a barrier layer of the transistor, and the nanopillars have one-to-one correspondence to screw dislocations in the barrier layer. According to the present invention, by controlling the TMGa flow rate and the V/III ratio in the growth process of an AlxGa1-xN barrier, the formation of V-shaped defects at termination positions of the screw dislocations can be avoided, and 1-3 nm AlxGa1-xN alloy nanopillars can be formed at the termination positions of the screw dislocations. As the V-shaped defects at the termination positions of the screw dislocations on the barrier surface are filled by the alloy nanopillars, the effective barrier thickness at the termination positions of the screw dislocations is increased, so that the gate leakage current is effectively suppressed and the withstand voltage characteristic of the transistor is improved.

Description

一种覆盖纳米柱势垒的GaN晶体管及其制备方法GaN transistor covering nano-pillar barrier and preparation method thereof 技术领域Technical field
本发明涉及半导体材料生长和半导体器件制作，特别是涉及一种覆盖纳米柱的GaN基晶体管及其势垒生长方法。The present invention relates to semiconductor material growth and semiconductor device fabrication, and more particularly to a GaN-based transistor covering a nanocolumn and a barrier growth method thereof.
背景技术Background technique
氮化镓基高电子迁移率晶体管(HEMT)是由Al xGa 1-xN和GaN形成异质结，Al xGa 1-xN/GaN异质结的界面自发极化和压电极化不连续性形成剩余极化电荷从而在界面形成高浓度的二维电子气。高质量的Al xGa 1-xN势垒层的生长技术是氮化镓基晶体管的关键外延技术之一。GaN基HEMT具有二维电子(2DEG)浓度高，迁移率高，击穿电场强等优点被广泛用于高频和高压微波器件。 Gallium nitride based high electron mobility transistor (HEMT) is a heterojunction formed by Al x Ga 1-x N and GaN, and the interface spontaneous polarization and piezoelectric polarization of the Al x Ga 1-x N/GaN heterojunction The discontinuity forms a residual polarization charge to form a high concentration of two-dimensional electron gas at the interface. The growth technique of the high quality Al x Ga 1-x N barrier layer is one of the key epitaxial technologies of the gallium nitride based transistor. GaN-based HEMTs are widely used in high-frequency and high-voltage microwave devices because of their high concentration of two-dimensional electrons (2DEG), high mobility, and strong breakdown electric field.
目前高质量大尺寸的GaN衬底获得十分困难而且价格非常昂贵，因此GaN外延材料的生长一般都是通过在碳化硅，蓝宝石以及硅衬底上的异质外延实现。由于晶格失配的存在GaN异质外延材料中存在大量的穿透位错(10 6-10 9/cm 2)而这些位错缺陷也影响着氮化镓晶体管的电学特性以及器件可靠性。异质外延生长的氮化镓材料中的穿透位错有刃位错，部分位错和螺位错三种，其中螺位错器件电学特性的影响最大。螺位错通常会在势垒表面形成V型缺陷减小势垒有效厚度同时螺位错的中心通常存在大量缺陷空位会在栅电极下形成漏电通道和高压下电击穿通道。 At present, high quality and large size GaN substrates are very difficult to obtain and very expensive, so the growth of GaN epitaxial materials is generally achieved by heteroepitaxial growth on silicon carbide, sapphire and silicon substrates. Due to the existence of lattice mismatch, there are a large number of threading dislocations (10 6 -10 9 /cm 2 ) in the GaN heteroepitaxial material, and these dislocation defects also affect the electrical characteristics and device reliability of the gallium nitride transistor. The threading dislocations in the heteroepitaxially grown gallium nitride material are three kinds of edge dislocations, partial dislocations and screw dislocations, and the electrical characteristics of the screw dislocation devices are the most affected. Screw dislocations typically form a V-type defect reduction barrier effective thickness on the surface of the barrier while the center of the screw dislocation typically has a large number of defect vacancies that form a leakage channel and a high voltage electrical breakdown channel under the gate electrode.
为了减小螺位错缺陷对器件性能影响，一般是通过生长在晶格失配较小的SiC衬底、使用复杂的缓冲层结构以及采用侧向外延生长方法过滤穿透位错减小势垒层的螺位错密度等方法，上述方法成本高、工艺复杂且可控性较差。In order to reduce the influence of screw dislocation defects on device performance, it is generally used to filter the threading dislocation reducing barrier by growing on a SiC substrate with a small lattice mismatch, using a complicated buffer layer structure, and using a lateral epitaxial growth method. The method has the advantages of high cost, complicated process and poor controllability of the method such as the screw dislocation density of the layer.
发明概述Summary of invention
技术问题technical problem
问题的解决方案Problem solution
技术解决方案Technical solution
本发明的目的在于克服现有技术之不足，提供一种通过优化势垒生长条件使势 垒覆盖纳米柱的晶体管及其制备方法。SUMMARY OF THE INVENTION An object of the present invention is to overcome the deficiencies of the prior art and to provide a transistor in which a barrier is covered by a barrier by optimizing barrier growth conditions and a method of fabricating the same.
本发明解决其技术问题所采用的技术方案是：The technical solution adopted by the present invention to solve the technical problem thereof is:
一种覆盖纳米柱势垒的GaN晶体管，所述晶体管由下至上包括衬底、缓冲层、沟道层及覆盖纳米柱的势垒层，势垒层上设置有源极、漏极及栅极，且栅极位于源极和漏极之间；所述沟道层由GaN异质外延生长形成，所述势垒层由Al xGa 1-xN异质外延生长形成，且势垒层表面分布有Al xGa 1-xN合金纳米柱，其中0＜x＜1；所述纳米柱与势垒层中的螺位错一一对应。 A GaN transistor covering a nano-pillar barrier, the transistor includes a substrate, a buffer layer, a channel layer, and a barrier layer covering the nano-pillar from bottom to top, and a source, a drain, and a gate are disposed on the barrier layer And a gate is located between the source and the drain; the channel layer is formed by heteroepitaxial growth of GaN, the barrier layer is formed by Al x Ga 1-x N heteroepitaxial growth, and the surface of the barrier layer An Al x Ga 1-x N alloy nanocolumn is distributed, wherein 0<x<1; the nanocolumn corresponds to the screw dislocations in the barrier layer.
可选的，所述纳米柱的高度为1-3nm。Optionally, the height of the nano-pillar is 1-3 nm.
可选的，所述纳米柱的密度为10 6个/cm 2-10 9个/cm 2。 Optionally, the nano-column has a density of 10 6 /cm 2 -10 9 /cm 2 .
可选的，所述Al xGa 1-xN势垒层的Al组分为15％-22％。 Optionally, the Al component of the Al x Ga 1-x N barrier layer is 15%-22%.
可选的，所述源极、漏极及栅极由金属制成且源极和漏极与势垒层形成欧姆接触，栅极与势垒层形成肖特基接触。Optionally, the source, the drain and the gate are made of metal and the source and the drain form an ohmic contact with the barrier layer, and the gate and the barrier layer form a Schottky contact.
一种上述覆盖纳米柱势垒的GaN晶体管的制备方法包括以下步骤：A method for fabricating a GaN transistor covering the nano-pillar barrier includes the following steps:
(1)于一衬底上形成缓冲层；(1) forming a buffer layer on a substrate;
(2)于所述缓冲层上异质外延生长GaN沟道层；(2) heteroepitaxially growing a GaN channel layer on the buffer layer;
(3)通过MOCVD方法于所述沟道层上异质外延生长覆盖纳米柱的Al xGa 1-xN势垒层，生长条件为：TMGa为180-300sccm，TMAl为350-800sccm，NH 3的流量为8000-12000sccm，外延生长的表面温度1000-1150℃，从而于势垒层表面的螺位错终止处一一对应的形成纳米柱； (3) hetero-epitaxially growing the Al x Ga 1-x N barrier layer covering the nano-pillar on the channel layer by MOCVD method, the growth conditions are: TMGa is 180-300 sccm, TMAl is 350-800 sccm, NH 3 The flow rate is 8000-12000 sccm, and the surface temperature of the epitaxial growth is 1000-1150 ° C, so that the nano-columns are formed one by one at the end of the screw dislocation on the surface of the barrier layer;
(4)于覆盖纳米柱势垒层表面上形成源极和漏极；(4) forming a source and a drain on the surface of the barrier layer covering the nano-pillar;
(5)于源极和漏极之间定义一栅极区域形成栅极。(5) A gate region is defined between the source and the drain to form a gate.
可选的，步骤(3)中，所述势垒层生长条件为：表面温度为1070℃，TMAl流量400sccm，TMGa流量230sccm，NH 3流量9000sccm。 Optionally, in step (3), the barrier layer growth conditions are: a surface temperature of 1070 ° C, a TMAl flow rate of 400 sccm, a TMGa flow rate of 230 sccm, and a NH 3 flow rate of 9000 sccm.
可选的，所述势垒层生长速度为1.8μm/h-3μm/h。Optionally, the barrier layer growth rate is 1.8 μm/h-3 μm/h.
可选的，步骤(2)具体包括以下子步骤：通过电子束蒸镀的方法于所述势垒层表面的两个区域分别蒸镀上Ti/Al/Ni/Au多金属层，其中所述Ti/Al/Ni/Au的厚度分别是20/150/70/100nm；于850-950℃下退火25-50秒形成欧姆接触，形成所述源极和漏极。Optionally, the step (2) specifically includes the following sub-steps: depositing a Ti/Al/Ni/Au multi-metal layer on two regions of the surface of the barrier layer by electron beam evaporation, wherein The thickness of Ti/Al/Ni/Au is 20/150/70/100 nm, respectively; annealing at 850-950 ° C for 25-50 seconds forms an ohmic contact, forming the source and drain.
可选的，步骤(4)中，所述栅极是金属，通过磁控溅镀、离子蒸镀或电子束蒸发的方法沉积于所述覆盖纳米柱的势垒层表面并与势垒层形成肖特基接触。Optionally, in step (4), the gate is a metal, and is deposited on the surface of the barrier layer covering the nano-pillar and formed by the barrier layer by magnetron sputtering, ion evaporation or electron beam evaporation. Schottky contact.
发明的有益效果Advantageous effects of the invention
有益效果Beneficial effect
本发明的有益效果是：The beneficial effects of the invention are:
1.本发明通过控制Al xGa 1-xN势垒层的生长条件，在势垒表面的螺位错终止处形成合金纳米柱结构，由于合金纳米柱填充螺位错中心的空位异质栅电极退火过程中电极材料在位错中心扩散从而减少栅漏电通道。 1. The invention forms an alloy nano-pillar structure at the end of the screw dislocation at the surface of the barrier by controlling the growth conditions of the Al x Ga 1-x N barrier layer, because the alloy nano-pillar fills the vacancy hetero-grid at the center of the screw dislocation During electrode annealing, the electrode material diffuses at the center of the dislocation to reduce the gate leakage path.
2.通过在势垒表面的螺位错终止形成合金纳米柱结构，有效增加了螺位错终止处的有效势垒厚度避免高压下器件通过螺位错处的击穿从而改善器件高压工作特性。2. The alloy nano-column structure is formed by the termination of the screw dislocation on the surface of the barrier, which effectively increases the effective barrier thickness at the end of the screw dislocation to avoid the breakdown of the device through the screw dislocation under high voltage, thereby improving the high-voltage operating characteristics of the device.
3.制作方法简单，无特殊工艺要求，可控性强，可以有效减少外延成本和改善器件高压特性，适合实际生产应用。3. The production method is simple, no special process requirements, strong controllability, can effectively reduce the epitaxial cost and improve the high-voltage characteristics of the device, and is suitable for practical production applications.
对附图的简要说明Brief description of the drawing
附图说明DRAWINGS
图1为本发明实施例之截面结构示意图；1 is a schematic cross-sectional view of an embodiment of the present invention;
图2为本发明实施例之俯视结构示意图；2 is a schematic top plan view of an embodiment of the present invention;
图3为本发明实施例的有覆盖纳米柱势垒截面示意图；3 is a schematic cross-sectional view showing a barrier of a covered nano-pillar according to an embodiment of the present invention;
图4为本发明实施例的无覆盖纳米柱势垒截面示意图；4 is a schematic cross-sectional view showing a barrier of a non-covered nano-pillar according to an embodiment of the present invention;
图5为本发明实施例的有覆盖纳米柱势垒表面AFM图；5 is an AFM diagram of a barrier surface of a covered nano-pillar according to an embodiment of the present invention;
图6为本发明实施例的无覆盖纳米柱势垒表面AFM图。6 is an AFM diagram of a non-covered nanocolumn barrier surface according to an embodiment of the present invention.
发明实施例Invention embodiment
本发明的实施方式Embodiments of the invention
下文中将结合附图对本发明的实施例进行详细说明。本发明的所有附图仅为示意以便更容易理解本发明，其具体比例可依照设计需求进行调整。文中描述覆盖纳米柱的势垒生长条件仅为示例，改变其中单一条件仍有可能形成覆盖纳米柱的势垒结构，此皆本说明书揭露范围。本文中描述的器件制作过程中的元件 的尺寸和个数仅为示例，实际可以根据设计需要对其进行调整。Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. All drawings of the invention are merely schematic for easier understanding of the invention, and the specific proportions may be adjusted according to design requirements. The description of the barrier growth conditions for covering the nanocolumns is merely an example, and it is still possible to form a barrier structure covering the nanocolumns under a single condition, which is disclosed in the specification. The size and number of components in the device fabrication process described in this article are examples only, and can be adjusted to suit the design needs.
参考图1和图2，一种覆盖纳米柱势垒的GaN晶体管，包括由下至上包括衬底1、缓冲层2、沟道层3及覆盖纳米柱5的势垒层4，势垒层4上设置有源极6、漏极7及栅极8，且栅极8位于源极6和漏极7之间；所述沟道层3由GaN异质外延生长形成，所述势垒层4由Al xGa 1-xN异质外延生长形成，且势垒层4表面分布有Al xGa 1-xN合金纳米柱5，其中0＜x＜1；所述纳米柱5与势垒层4中的螺位错一一对应。其制备方法包括如下步骤： Referring to FIGS. 1 and 2, a GaN transistor covering a nano-pillar barrier includes a substrate layer 1, a buffer layer 2, a channel layer 3, and a barrier layer 4 covering the nano-pillars 5 from bottom to top, and a barrier layer 4 The source electrode 6, the drain electrode 7 and the gate electrode 8 are disposed, and the gate electrode 8 is located between the source electrode 6 and the drain electrode 7; the channel layer 3 is formed by heteroepitaxial growth of GaN, and the barrier layer 4 is formed. Formed by Al x Ga 1-x N heteroepitaxial growth, and the surface of the barrier layer 4 is distributed with an Al x Ga 1-x N alloy nanocolumn 5, where 0 < x <1; the nanocolumn 5 and the barrier layer The screw dislocations in 4 correspond one-to-one. The preparation method comprises the following steps:
1)GaN沟道层及缓冲层生长：利用金属有机化学气相沉积设备(MOCVD)在所选用的异质外延衬底1(蓝宝石，SiC，Si)上生长缓冲层2(成核层和过渡层)，在缓冲层2上高温(表面温度1040℃)生长200nm GaN沟道层3，如图1所示；1) Growth of GaN channel layer and buffer layer: Buffer layer 2 (nucleation layer and transition layer) is grown on selected heteroepitaxial substrate 1 (sapphire, SiC, Si) by metal organic chemical vapor deposition (MOCVD) a 200 nm GaN channel layer 3 is grown on the buffer layer 2 at a high temperature (surface temperature 1040 ° C), as shown in FIG. 1;
2)在1)上面继续外延生长Al xGa 1-xN势垒层4，为了使势垒层4表的螺位错终止处形成合金纳米柱5，采用较高MO流量，其中TMGa(Ttrimethylgalliμm)为180-300sccm(标准立方米每分钟)，TMAl(Trimethylalμminiμm)为350-800sccm，同时NH 3的流量为8000-12000sccm，外延生长的表面温度1000-1150℃；在高MO流量和低V/III比的条件下势垒生长速度为1.8μm/h-3μm/h左右，Al xGa 1-xN势垒层的Al组分为15％-22％左右，在高生长速率条件下螺位错终止处形成了1-3nm的纳米柱5，如图1和图2所示，其中纳米柱的密度为106个/cm2-109个/cm2； 2) The epitaxial growth of the Al x Ga 1-x N barrier layer 4 is continued on 1), in order to form the alloy nanocolumn 5 at the end of the screw dislocation of the barrier layer 4, a higher MO flow rate is employed, wherein TMGa (Ttrimethylgalliμm) ) is 180-300sccm (standard cubic meters per minute), TMAl (Trimethylalμminiμm) is 350-800sccm, while the flow rate of NH 3 is 8000-12000sccm, the surface temperature of epitaxial growth is 1000-1150 ° C; at high MO flow rate and low V / Under the condition of III ratio, the barrier growth rate is about 1.8μm/h-3μm/h, and the Al component of the Al x Ga 1-x N barrier layer is about 15%-22%. Under the condition of high growth rate, the screw position The nano-column 5 of 1-3 nm is formed at the wrong end, as shown in FIG. 1 and FIG. 2, wherein the density of the nano-pillar is 106/cm2-109/cm2;
3)制备源漏电极6、7：通过光刻方法(电子束曝光(EBL)、紫外曝光(UVL))在势垒层表制备源漏电极需要的光刻胶图形，在覆盖光刻胶外延片表蒸镀源漏电极金属(Ti/Al/Ni/Au，厚度20nm/150nm/70nm/100nm)，在剥离液中剥离金属得到源漏电极，利用快速退火炉将源漏电极退火(退火温度850-950℃，退火时间35-60s，退火是气氛是氮气(氮气流量6L/min)；如图1和2所示，源电极6，漏电极7；3) Preparation of source-drain electrodes 6, 7: Photolithographic methods (electron beam exposure (EBL), ultraviolet exposure (UVL)) are used to prepare the photoresist pattern required for the source-drain electrodes in the barrier layer table, in the overlying photoresist extension The surface of the sheet is evaporated to the source and drain electrode metal (Ti/Al/Ni/Au, thickness 20nm/150nm/70nm/100nm), the metal is stripped in the stripping solution to obtain the source and drain electrodes, and the source and drain electrodes are annealed by a rapid annealing furnace (annealing temperature) 850-950 ° C, annealing time 35-60s, annealing is atmospheric nitrogen (nitrogen flow rate 6L / min); as shown in Figures 1 and 2, source electrode 6, drain electrode 7;
4)制备栅金属：通过光刻方法(电子束曝光(EBL)、紫外曝光(UVL))在势垒层表面制备栅电极需要的光刻胶图形，用磁控溅射设备在覆盖光刻胶外延片表蒸镀栅电极(TiN，厚度150-200nm)，在剥离液中剥离金属得到栅电极，利用退火炉将栅电极退火(退火温度600-800℃，退火时间20-60min，退火气 氛是氮气(氮气流量20L/min))；如图1和2所示，栅电极8。4) Preparing the gate metal: preparing a photoresist pattern required for the gate electrode on the surface of the barrier layer by a photolithography method (electron beam exposure (EBL), ultraviolet exposure (UVL)), and covering the photoresist with a magnetron sputtering device Epitaxial wafer evaporation electrode (TiN, thickness 150-200nm), stripping the metal in the stripping solution to obtain the gate electrode, annealing the gate electrode by annealing furnace (annealing temperature 600-800 ° C, annealing time 20-60 min, annealing atmosphere is Nitrogen (nitrogen flow rate 20 L/min)); as shown in Figs. 1 and 2, the gate electrode 8.
下面以具体应用示例对本发明的实施以实例方式作进一步描述：The following is a further description of the implementation of the invention by way of specific application examples:
示例Example
(1)利用MOCVD在1mm的6寸硅衬底上生长沟道层和缓冲层。缓冲层包括200nm的高温(表面温度1100℃)AlN成核层，1.5μm的组分递变的Al xGa 1-xN过渡层(Al 0.75Ga 0.25N-200nm，Al 0.55Ga 0.45N-400nm，Al 0.25Ga 0.75N-900nm，表面温度1060℃)和接着生长2.0μm的GaN高阻层(表面温度980℃)。沟道层为200nm的高温(表面温度为1060℃)GaN层； (1) A channel layer and a buffer layer were grown on a 1 mm 6-inch silicon substrate by MOCVD. The buffer layer includes a high temperature (surface temperature of 1100 ° C) AlN nucleation layer of 200 nm, a 1.5 μm compositionally tapered Al x Ga 1-x N transition layer (Al 0.75 Ga 0.25 N-200 nm, Al 0.55 Ga 0.45 N-400 nm , Al 0.25 Ga 0.75 N-900 nm, surface temperature 1060 ° C) and then a 2.0 μm GaN high resistance layer (surface temperature 980 ° C) was grown. The channel layer is a high temperature (surface temperature of 1060 ° C) GaN layer of 200 nm;
(2)利用MOCVD继续在(1)的GaN沟道层表面外延生长Al xGa 1-xN势垒层。采用较高MO流量其中TMGa为220sccm，TMAl为400sccm同时NH 3的流量为9000sccm；在高MO流量，V/III比为270的条件下势垒生长速度为2.2μm/h左右，Al xGa 1-xN势垒层的Al组分为20％左右，在高生长速率条件下螺位错终止处形成了1-2nm的纳米柱，直径为120-200nm，如图5所示； (2) The Al x Ga 1-x N barrier layer is epitaxially grown on the surface of the GaN channel layer of (1) by MOCVD. A higher MO flow rate is used, wherein TMGa is 220 sccm, TMAl is 400 sccm, and NH 3 flow rate is 9000 sccm; at high MO flow rate, V/III ratio is 270, the barrier growth rate is about 2.2 μm/h, and Al x Ga 1 The Al composition of the -x N barrier layer is about 20%, and a nano-column of 1-2 nm is formed at the end of the screw dislocation at a high growth rate, and the diameter is 120-200 nm, as shown in FIG. 5;
(3)通过紫外光刻方法在覆盖纳米柱势垒的外延片表面指标源极和漏极所需要光刻胶图形(源漏电极边缘间距25μm，电极长度20μm，电极宽度100μm)，利用电子束蒸发设备在光刻胶表面蒸镀Ti/Al/Ni/Au(20nm/150nm/70nm/100nm)；在剥离液中剥离金属得到源漏电极，利用快速退火炉将源漏电极在900℃条件下退火50s(氮气流量6L/min)使源漏电极和势垒形成欧姆接触；(3) The photoresist pattern required for the source and drain of the surface of the epitaxial wafer covering the nano-pillar barrier by ultraviolet lithography (source-drain electrode edge spacing 25 μm, electrode length 20 μm, electrode width 100 μm), using electron beam Evaporation equipment evaporates Ti/Al/Ni/Au (20nm/150nm/70nm/100nm) on the surface of the photoresist; strips the metal in the stripping solution to obtain the source and drain electrodes, and uses the rapid annealing furnace to make the source and drain electrodes at 900 °C Annealing for 50s (nitrogen flow rate 6L/min) to make the source-drain electrode and the barrier form an ohmic contact;
(4)通过紫外曝光方法在势垒层表面源漏电极间制备栅电极需要的光刻胶图形(栅长2μm，距离源极距离3μm，距离漏极距离15μm，栅宽100μm)，用磁控溅射设备在覆盖光刻胶外延片表蒸镀栅电极(TiN，厚度180nm)，在剥离液中剥离金属得到栅电极，利用管式退火炉在650℃氮气气氛下将栅电极退火40min，使栅电极和势垒形成肖特基接触；(4) The photoresist pattern required for preparing the gate electrode between the source and drain electrodes on the surface of the barrier layer by ultraviolet exposure method (gate length 2 μm, distance from source to source 3 μm, distance from drain to 15 μm, gate width 100 μm), using magnetic control The sputtering apparatus covers the photoresist epitaxial wafer vapor-deposited gate electrode (TiN, thickness: 180 nm), strips the metal in the stripping solution to obtain a gate electrode, and anneals the gate electrode in a tubular annealing furnace at 650 ° C for 40 min in a nitrogen atmosphere. The gate electrode and the barrier form a Schottky contact;
在通常的低生长速率和高V/III比的条件下势垒层4’表面的螺位错终止处会形成V型缺陷5’，如图4和图6所示(其中图4是结构示意图，图6是外延片表面原子力显微图)。通过采用低V/III比和高速势垒生长方法可以在势垒表面的螺位错终止处形成合金纳米柱如图3和图5所示(其中图3是结构示意图，图5是外延片表面原子力显微图)。由于势垒表面螺位错终止处形成了纳米柱结构可以有 效抑制栅电极下漏电通道形成，同时由于纳米柱增加螺位错附件的有效势垒厚度，漏极和栅极间势垒击穿特性也会得到一定提高。At the normal low growth rate and high V/III ratio, a V-type defect 5' is formed at the end of the screw dislocation on the surface of the barrier layer 4', as shown in FIG. 4 and FIG. 6 (where FIG. 4 is a schematic structural view). Figure 6 is an atomic force micrograph of the surface of the epitaxial wafer). Alloy nanopillars can be formed at the end of the screw dislocation at the barrier surface by using a low V/III ratio and high-speed barrier growth method as shown in FIGS. 3 and 5 (wherein FIG. 3 is a schematic structural view, and FIG. 5 is an epitaxial wafer surface). Atomic force micrograph). Due to the formation of the nano-pillar structure at the end of the barrier surface of the barrier, the formation of the leakage channel under the gate electrode can be effectively suppressed. At the same time, the effective barrier thickness of the screw dislocation attachment is increased due to the nano-column, and the barrier breakdown between the drain and the gate is obtained. Will also get a certain increase.
本发明公开的方法还可以用于在自组织生长Al xGa 1-xN合金纳米柱以及用于抑制GaN外延螺纹错向上传播改善外延质量。 The method disclosed in the present invention can also be used to grow Al x Ga 1-x N alloy nanocolumns in self-organizing and to suppress GaN epitaxial thread misalignment to improve epitaxial quality.
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，比如，对实例中的工艺参数进行了简单的改变，均应包含在本发明的保护范围之内。The above description is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. within the spirit and scope of the present invention, such as a simple modification of the process parameters in the examples, are intended to be included within the scope of the present invention.

Claims (10)

  1. 一种覆盖纳米柱势垒的GaN晶体管，其特征在于：所述晶体管由下至上包括衬底、缓冲层、沟道层及覆盖纳米柱的势垒层，势垒层上设置有源极、漏极及栅极，且栅极位于源极和漏极之间；所述沟道层由GaN异质外延生长形成，所述势垒层由Al xGa 1-xN异质外延生长形成，且势垒层表面分布有Al xGa 1-xN合金纳米柱，其中0＜x＜1；所述纳米柱与势垒层中的螺位错一一对应。 A GaN transistor covering a nano-pillar barrier is characterized in that: the transistor includes a substrate, a buffer layer, a channel layer, and a barrier layer covering the nano-pillar from bottom to top, and a source electrode and a drain are disposed on the barrier layer a gate and a gate between the source and the drain; the channel layer being formed by heteroepitaxial growth of GaN, the barrier layer being formed by Al x Ga 1-x N heteroepitaxial growth, and An Al x Ga 1-x N alloy nanocolumn is distributed on the surface of the barrier layer, wherein 0<x<1; the nanocolumn has a one-to-one correspondence with the screw dislocations in the barrier layer.
  2. 根据权利要求1所述的覆盖纳米柱势垒的GaN晶体管，其特征在于：所述纳米柱的高度为1-3nm。The GaN transistor covering a nano-pillar barrier according to claim 1, wherein the nano-pillar has a height of 1-3 nm.
  3. 根据权利要求1所述的覆盖纳米柱势垒的GaN晶体管，其特征在于：所述纳米柱的密度为10 6个/cm 2-10 9个/cm 2。 The GaN transistor covering a nano-pillar barrier according to claim 1, wherein the nano-column has a density of 10 6 /cm 2 -10 9 /cm 2 .
  4. 根据权利要求1所述的覆盖纳米柱势垒的GaN晶体管，其特征在于：所述Al xGa 1-xN势垒层的Al组分为15％-22％。 The GaN transistor covering a nano-pillar barrier according to claim 1, wherein the Al x Ga 1-x N barrier layer has an Al composition of 15% to 22%.
  5. 根据权利要求1所述的覆盖纳米柱势垒的GaN晶体管，其特征在于：所述源极、漏极及栅极由金属制成且源极和漏极与势垒层形成欧姆接触，栅极与势垒层形成肖特基接触。The GaN transistor covering a nano-pillar barrier according to claim 1, wherein the source, the drain and the gate are made of metal and the source and the drain form an ohmic contact with the barrier layer, and the gate A Schottky contact is formed with the barrier layer.
  6. 一种如权利要求1～5任一项所述的覆盖纳米柱势垒的GaN晶体管的制备方法，其特征在于包括以下步骤：A method of fabricating a GaN transistor covering a nano-pillar barrier according to any one of claims 1 to 5, comprising the steps of:
    (1)于一衬底上形成缓冲层；(1) forming a buffer layer on a substrate;
    (2)于所述缓冲层上异质外延生长GaN沟道层；(2) heteroepitaxially growing a GaN channel layer on the buffer layer;
    (3)通过MOCVD方法于所述沟道层上异质外延生长覆盖纳米柱的Al xGa 1-xN势垒层，生长条件为：TMGa为180-300sccm，TMAl为350-800sccm，NH 3的流量为8000-12000sccm，外延生长的表面温度1000-1150℃，从而于势垒层表面的螺位错终止处一一对应的形成纳米柱； (3) hetero-epitaxially growing the Al x Ga 1-x N barrier layer covering the nano-pillar on the channel layer by MOCVD method, the growth conditions are: TMGa is 180-300 sccm, TMAl is 350-800 sccm, NH 3 The flow rate is 8000-12000 sccm, and the surface temperature of the epitaxial growth is 1000-1150 ° C, so that the nano-columns are formed one by one at the end of the screw dislocation on the surface of the barrier layer;
    (4)于覆盖纳米柱势垒层表面上形成源极和漏极；(4) forming a source and a drain on the surface of the barrier layer covering the nano-pillar;
    (5)于源极和漏极之间定义一栅极区域形成栅极。(5) A gate region is defined between the source and the drain to form a gate.
  7. 根据权利要求6所述的制备方法，其特征在于：步骤(3)中，所述 势垒层生长条件为：表面温度为1070℃，TMAl流量400sccm，TMGa流量230sccm，NH 3流量9000sccm。 The preparation method according to claim 6, wherein in the step (3), the barrier layer growth conditions are: a surface temperature of 1070 ° C, a TMAl flow rate of 400 sccm, a TMGa flow rate of 230 sccm, and a NH 3 flow rate of 9000 sccm.
  8. 根据权利要求6所述的制备方法，其特征在于：所述势垒层生长速度为1.8μm/h-3μm/h。The preparation method according to claim 6, wherein the barrier layer growth rate is from 1.8 μm/h to 3 μm/h.
  9. 根据权利要求6所述的制备方法，其特征在于：步骤(2)具体包括以下子步骤：The preparation method according to claim 6, wherein the step (2) specifically comprises the following substeps:
    通过电子束蒸镀的方法于所述势垒层表面的两个区域分别蒸镀上Ti/Al/Ni/Au多金属层，其中所述Ti/Al/Ni/Au的厚度分别是20/150/70/100nm；Depositing a Ti/Al/Ni/Au multi-metal layer on two regions of the surface of the barrier layer by electron beam evaporation, wherein the thickness of the Ti/Al/Ni/Au is 20/150 /70/100nm;
    于850-950℃下退火25-50秒形成欧姆接触，形成所述源极和漏极。An ohmic contact is formed by annealing at 850-950 ° C for 25-50 seconds to form the source and drain.
  10. 根据权利要求6所述的制备方法，其特征在于：步骤(4)中，所述栅极是金属，通过磁控溅镀、离子蒸镀或电子束蒸发的方法沉积于所述覆盖纳米柱的势垒层表面并与势垒层形成肖特基接触。The preparation method according to claim 6, wherein in the step (4), the gate is a metal, and is deposited on the covered nanocolumn by magnetron sputtering, ion evaporation or electron beam evaporation. The surface of the barrier layer forms a Schottky contact with the barrier layer.
PCT/CN2018/110707 2017-11-14 2018-10-17 Gan transistor having barrier covered by nanopillars and preparation method therefor WO2019095923A1 (en)

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