WO2000019440A2 - Magnetoresistiver speicher mit niedriger stromdichte - Google Patents
Magnetoresistiver speicher mit niedriger stromdichte Download PDFInfo
- Publication number
- WO2000019440A2 WO2000019440A2 PCT/DE1999/002983 DE9902983W WO0019440A2 WO 2000019440 A2 WO2000019440 A2 WO 2000019440A2 DE 9902983 W DE9902983 W DE 9902983W WO 0019440 A2 WO0019440 A2 WO 0019440A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- electrically insulating
- magnetoresistive memory
- insulating material
- layers
- magnetoresistive
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
- G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
- G11C11/1655—Bit-line or column circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
- G11C11/1657—Word-line or row circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
Definitions
- Magnetoresistive memory with low current density.
- the invention relates to a magnetoresistive read / write memory (MRAM), the memory effect of which lies in the magnetically variable electrical resistance of the memory cell.
- MRAM magnetoresistive read / write memory
- Magnetoresistive memories have, for example, a magnetoresistive layer system between a word line and a bit line, which system consists, for example, of a soft magnetic layer and a hard magnetic layer which are separated by a thin tunnel oxide.
- the resistance between the bit line and the word line now depends on whether the magnetization directions in the materials are parallel or antiparallel, a parallel magnetization direction leading to a lower resistance value and an antiparallel magnetization direction leading to a higher resistance value.
- the relatively high currents or current peaks in the word or bit lines, in particular those required for writing a cell are disadvantageous in several respects, since the resulting current densities lead to electrical migration problems and a relatively high power loss.
- the object on which the invention is based is to specify a magnetoresistive read / write memory in which, with the smallest possible chip area, the current density in the bit or word lines is as low as possible.
- Figure 1A and IB two mutually orthogonal sections through a first embodiment of a magnetoresistive memory cell
- 2B and 2B show two mutually orthogonal sections through a second exemplary embodiment of a magnetoresistive memory cell according to the invention.
- the invention essentially consists in that, due to an improved coupling of a magnetic field generated by the bit lines and / or the word lines into the magnetoresistive memory cell, a lower current density is required in these lines. This is made possible by the invention in a particularly space-saving and efficient manner.
- FIG. 1A shows a sectional view in the area of two magnetoresistive cells.
- magnetoresistive Memory cells consist, for example, of a soft magnetic layer, which is separated from a hard magnetic layer by a tunnel oxide, the tunnel likely and thus the electrical resistance between the two layers depending on the direction of magnetization of the two layers.
- the magnetoresistive memory cells are each indicated by the soft magnetic layer WML and the hard magnetic layer HML and are located at intersections between bit lines and word lines. Laterally between the cells with the layers WML and HML are areas C, which consist of an electrically insulating material with a high permeability number.
- region B made of electrically insulating material with a high permeability number laterally between at least two lines LTO ⁇ and TO2, for example bit lines.
- the section of FIG. IB is orthogonal to the section of FIG. 1A and also shows areas D laterally between at least two lines LTU] _ and TU2, for example word lines, made of an electrically insulating material with a high permeability number.
- the layers A and E and the regions B, C and D can consist of different or else the same electrically insulating materials with a high permeability number. Suitable materials for this layer A and E and the areas B, C and D are, for example, ferrites.
- a further alternative is shown in two mutually orthogonal sections in FIGS. 2A and 2B, two magnetoresistive memory cells being shown between two layers F and H made of an electrically conductive or poorly insulating material with high permeability.
- the main difference from the first alternative is that the layers F and H do not touch the bit lines or the word lines, but are separated from them by an electrically insulating material with a relatively low permeability constant. This enables, for example, the use of electrically conductive or poorly insulating materials with a high permeability number, since the bit and word lines and also the memory cells themselves are not short-circuited or bridged by the electrically insulating material.
- the layers F and H can consist of different or of the same electrically conductive but also of electrically non-conductive materials with a high permeability number. Electrically conductive layers with a high permeability number are usually alloys made of iron, nickel and / or cobalt.
- Layer G can fill the entire space between layers F and H and the memory cells including word and bit lines.
- the material of layer G is an electrical insulator with a low permeability number and consists, for example, of silicon dioxide or silicon nitride.
- regions B and / or C and / or D can be made of an electrically insulating material with a high permeability number, e.g. B. consist of ferrite.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE59901952T DE59901952D1 (de) | 1998-09-30 | 1999-09-17 | Magnetoresistiver speicher mit niedriger stromdichte |
EP99955732A EP1099221B1 (de) | 1998-09-30 | 1999-09-17 | Magnetoresistiver speicher mit niedriger stromdichte |
JP2000572854A JP2002526909A (ja) | 1998-09-30 | 1999-09-17 | 電流密度の小さい磁気抵抗型メモリ |
US09/822,019 US6580636B2 (en) | 1998-09-30 | 2001-03-30 | Magnetoresistive memory with a low current density |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19845068.0 | 1998-09-30 | ||
DE19845068 | 1998-09-30 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/822,019 Continuation US6580636B2 (en) | 1998-09-30 | 2001-03-30 | Magnetoresistive memory with a low current density |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2000019440A2 true WO2000019440A2 (de) | 2000-04-06 |
WO2000019440A3 WO2000019440A3 (de) | 2000-05-25 |
Family
ID=7882946
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE1999/002983 WO2000019440A2 (de) | 1998-09-30 | 1999-09-17 | Magnetoresistiver speicher mit niedriger stromdichte |
Country Status (7)
Country | Link |
---|---|
US (1) | US6580636B2 (de) |
EP (1) | EP1099221B1 (de) |
JP (1) | JP2002526909A (de) |
KR (1) | KR100567972B1 (de) |
DE (1) | DE59901952D1 (de) |
TW (1) | TW454187B (de) |
WO (1) | WO2000019440A2 (de) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000072324A1 (en) * | 1999-05-25 | 2000-11-30 | Honeywell Inc. | Local shielding for memory cells |
EP1120790A1 (de) * | 2000-01-27 | 2001-08-01 | Hewlett-Packard Company, A Delaware Corporation | Magnetischer Speicher mit Strukturen die magnetische Störungen in Abfühlschichten verhüten |
DE10032278C1 (de) * | 2000-07-03 | 2001-11-29 | Infineon Technologies Ag | Verfahren zur Verhinderung von Elektromigration in einem MRAM |
US6392922B1 (en) | 2000-08-14 | 2002-05-21 | Micron Technology, Inc. | Passivated magneto-resistive bit structure and passivation method therefor |
US6413788B1 (en) | 2001-02-28 | 2002-07-02 | Micron Technology, Inc. | Keepers for MRAM electrodes |
WO2003043015A2 (en) * | 2001-11-13 | 2003-05-22 | Motorola, Inc., A Corporation Of The State Of Delaware | Multiple turn for conductive line programming mram |
EP1246191A3 (de) * | 2001-03-27 | 2003-09-17 | Kabushiki Kaisha Toshiba | Magnetische Speicheranordnung |
US6783995B2 (en) | 2002-04-30 | 2004-08-31 | Micron Technology, Inc. | Protective layers for MRAM devices |
US6989576B1 (en) | 2001-08-30 | 2006-01-24 | Micron Technology, Inc. | MRAM sense layer isolation |
US7112454B2 (en) | 2003-10-14 | 2006-09-26 | Micron Technology, Inc. | System and method for reducing shorting in memory cells |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW569442B (en) | 2001-12-18 | 2004-01-01 | Toshiba Corp | Magnetic memory device having magnetic shield layer, and manufacturing method thereof |
US6770491B2 (en) * | 2002-08-07 | 2004-08-03 | Micron Technology, Inc. | Magnetoresistive memory and method of manufacturing the same |
US6914805B2 (en) | 2002-08-21 | 2005-07-05 | Micron Technology, Inc. | Method for building a magnetic keeper or flux concentrator used for writing magnetic bits on a MRAM device |
KR100496860B1 (ko) | 2002-09-19 | 2005-06-22 | 삼성전자주식회사 | 자기 저항 기억 소자 및 그 제조 방법 |
KR100515053B1 (ko) * | 2002-10-02 | 2005-09-14 | 삼성전자주식회사 | 비트라인 클램핑 전압 레벨에 대해 안정적인 독출 동작이가능한 마그네틱 메모리 장치 |
US7068537B2 (en) * | 2002-11-06 | 2006-06-27 | Interuniversitair Microelektronica Centrum (Imec) | Magnetic device and method of making the same |
EP1418590A1 (de) * | 2002-11-07 | 2004-05-12 | Interuniversitair Micro-Elektronica Centrum Vzw | Magnetische Anordnung |
JP2004228187A (ja) * | 2003-01-21 | 2004-08-12 | Renesas Technology Corp | 薄膜磁性体記憶装置 |
US6865107B2 (en) | 2003-06-23 | 2005-03-08 | Hewlett-Packard Development Company, L.P. | Magnetic memory device |
US7034374B2 (en) * | 2003-08-22 | 2006-04-25 | Micron Technology, Inc. | MRAM layer having domain wall traps |
US7078239B2 (en) | 2003-09-05 | 2006-07-18 | Micron Technology, Inc. | Integrated circuit structure formed by damascene process |
US7285835B2 (en) * | 2005-02-24 | 2007-10-23 | Freescale Semiconductor, Inc. | Low power magnetoelectronic device structures utilizing enhanced permeability materials |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4455626A (en) * | 1983-03-21 | 1984-06-19 | Honeywell Inc. | Thin film memory with magnetoresistive read-out |
EP0776011A2 (de) * | 1995-11-24 | 1997-05-28 | Motorola, Inc. | Magnetischer Speicher und Verfahren dafür |
EP0875901A2 (de) * | 1997-04-28 | 1998-11-04 | Canon Kabushiki Kaisha | Magnetisches Dünnfilmspeicherelement unter Verwendung des GMR-Effekts und magnetischer Dünnfilmspeicher |
US5902690A (en) * | 1997-02-25 | 1999-05-11 | Motorola, Inc. | Stray magnetic shielding for a non-volatile MRAM |
US5920500A (en) * | 1996-08-23 | 1999-07-06 | Motorola, Inc. | Magnetic random access memory having stacked memory cells and fabrication method therefor |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3604109A (en) * | 1969-11-17 | 1971-09-14 | Thomas & Betts Corp | Method of making horseshoe-shaped keepered word-line structure for memory planes |
US5587943A (en) * | 1995-02-13 | 1996-12-24 | Integrated Microtransducer Electronics Corporation | Nonvolatile magnetoresistive memory with fully closed flux operation |
-
1999
- 1999-09-01 TW TW088115029A patent/TW454187B/zh not_active IP Right Cessation
- 1999-09-17 WO PCT/DE1999/002983 patent/WO2000019440A2/de active IP Right Grant
- 1999-09-17 DE DE59901952T patent/DE59901952D1/de not_active Expired - Fee Related
- 1999-09-17 KR KR1020017004100A patent/KR100567972B1/ko not_active IP Right Cessation
- 1999-09-17 JP JP2000572854A patent/JP2002526909A/ja not_active Withdrawn
- 1999-09-17 EP EP99955732A patent/EP1099221B1/de not_active Expired - Lifetime
-
2001
- 2001-03-30 US US09/822,019 patent/US6580636B2/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4455626A (en) * | 1983-03-21 | 1984-06-19 | Honeywell Inc. | Thin film memory with magnetoresistive read-out |
EP0776011A2 (de) * | 1995-11-24 | 1997-05-28 | Motorola, Inc. | Magnetischer Speicher und Verfahren dafür |
US5920500A (en) * | 1996-08-23 | 1999-07-06 | Motorola, Inc. | Magnetic random access memory having stacked memory cells and fabrication method therefor |
US5902690A (en) * | 1997-02-25 | 1999-05-11 | Motorola, Inc. | Stray magnetic shielding for a non-volatile MRAM |
EP0875901A2 (de) * | 1997-04-28 | 1998-11-04 | Canon Kabushiki Kaisha | Magnetisches Dünnfilmspeicherelement unter Verwendung des GMR-Effekts und magnetischer Dünnfilmspeicher |
Cited By (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000072324A1 (en) * | 1999-05-25 | 2000-11-30 | Honeywell Inc. | Local shielding for memory cells |
US7166479B2 (en) | 1999-05-25 | 2007-01-23 | Micron Technology, Inc. | Methods of forming magnetic shielding for a thin-film memory element |
EP1120790A1 (de) * | 2000-01-27 | 2001-08-01 | Hewlett-Packard Company, A Delaware Corporation | Magnetischer Speicher mit Strukturen die magnetische Störungen in Abfühlschichten verhüten |
DE10032278C1 (de) * | 2000-07-03 | 2001-11-29 | Infineon Technologies Ag | Verfahren zur Verhinderung von Elektromigration in einem MRAM |
US6623987B2 (en) | 2000-08-14 | 2003-09-23 | Micron Technology, Inc. | Passivated magneto-resistive bit structure and passivation method therefor |
US6392922B1 (en) | 2000-08-14 | 2002-05-21 | Micron Technology, Inc. | Passivated magneto-resistive bit structure and passivation method therefor |
US7427514B2 (en) | 2000-08-14 | 2008-09-23 | Micron Technology, Inc. | Passivated magneto-resistive bit structure and passivation method therefor |
US6806546B2 (en) | 2000-08-14 | 2004-10-19 | Micron Technology, Inc. | Passivated magneto-resistive bit structure |
US6413788B1 (en) | 2001-02-28 | 2002-07-02 | Micron Technology, Inc. | Keepers for MRAM electrodes |
US6417561B1 (en) | 2001-02-28 | 2002-07-09 | Micron Technology, Inc. | Keepers for MRAM electrodes |
EP1246191A3 (de) * | 2001-03-27 | 2003-09-17 | Kabushiki Kaisha Toshiba | Magnetische Speicheranordnung |
KR100579686B1 (ko) * | 2001-03-27 | 2006-05-15 | 가부시끼가이샤 도시바 | 자기 메모리 디바이스 |
US6989576B1 (en) | 2001-08-30 | 2006-01-24 | Micron Technology, Inc. | MRAM sense layer isolation |
US7242067B1 (en) | 2001-08-30 | 2007-07-10 | Micron Technology, Inc. | MRAM sense layer isolation |
WO2003043015A3 (en) * | 2001-11-13 | 2004-02-19 | Motorola Inc | Multiple turn for conductive line programming mram |
WO2003043015A2 (en) * | 2001-11-13 | 2003-05-22 | Motorola, Inc., A Corporation Of The State Of Delaware | Multiple turn for conductive line programming mram |
US6783995B2 (en) | 2002-04-30 | 2004-08-31 | Micron Technology, Inc. | Protective layers for MRAM devices |
US7211849B2 (en) | 2002-04-30 | 2007-05-01 | Micron Technology, Inc. | Protective layers for MRAM devices |
US7112454B2 (en) | 2003-10-14 | 2006-09-26 | Micron Technology, Inc. | System and method for reducing shorting in memory cells |
Also Published As
Publication number | Publication date |
---|---|
DE59901952D1 (de) | 2002-08-08 |
US6580636B2 (en) | 2003-06-17 |
KR20010100862A (ko) | 2001-11-14 |
WO2000019440A3 (de) | 2000-05-25 |
EP1099221B1 (de) | 2002-07-03 |
EP1099221A2 (de) | 2001-05-16 |
US20010030886A1 (en) | 2001-10-18 |
TW454187B (en) | 2001-09-11 |
JP2002526909A (ja) | 2002-08-20 |
KR100567972B1 (ko) | 2006-04-07 |
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