WO2000016303A1

WO2000016303A1 - Driving circuit for field emission display

Info

Publication number: WO2000016303A1
Application number: PCT/KR1999/000527
Authority: WO
Inventors: Seung Tae Kim; Oh Kyong Kwon
Original assignee: Orion Electric Co. Ltd.
Priority date: 1998-09-11
Filing date: 1999-09-09
Publication date: 2000-03-23
Also published as: KR20000019416A; KR20010031928A; JP2002525659A

Abstract

A driving circuit for an FED capable of re-using charge accumulated in gate lines, cathode lines or anode lines, so that the swing width of the drive voltage for the FED resulting from a supply voltage is reduced, thereby achieving a reduction in power consumption while improving the reliability of high-voltage devices. The driving circuit includes output circuits (28, 30) connected to lines, which are gate, anode, or cathode lines, and adapted to charge the lines in a sequential method based on successive line selection control signals, respectively, switching devices each coupled between adjacent ones of the lines and adapted to conduct a switching operation based on a switching control signal, logic operating devices each adapted to receive an associated one of the line selection control signals while receiving a charge recycling signal, thereby controlling a charge migration from a currently activated one of the lines to the line adapted to be activated following the currently activated line, and switching controllers each coupled to an associated logic operating device while being coupled to controller serving to control the switching operation of the associated switching device based on an output signal from the associated logic operating device.

Description

DRIVING CIRCUIT FOR FIELD EMISSION DISPLAY

TECHNICAL FIELD

The present invention relates to a field emission display, and more particularly to a driving circuit for such a field emission display that is adapted to drive gate lines, cathode lines, and anode lines of the field emission display.

BACKGROUND ART

Field emission displays (FEDs), which have recently been highlighted in the flat display device field, are configured to display in a manner similar to that of CRTs configured to display images using emitted electrons. However, such FEDs have a difference from CRTs in that they utilize cold electron emission. Thermal electron emission is utilized in CRTs.

Conventional FEDs include several hundred to several thousand field emission devices each associated with one pixel. Electrons emitted from each field emission device impinge on an anode coated with a phosphor film, thereby displaying an image.

Referring to Fig. 1, a field emission device, which constitutes one pixel of the above mentioned FED, is illustrated. As shown in Fig. 1, the field emission device includes a cathode 12 coupled to a cathode electrode 10, a gate 14 arranged above the cathode 12 while being spaced apart from the cathode 12, and an anode 18 arranged above the gate 14 and coated at a lower surface thereof with a phosphor film 16.

The phosphor film 16 serves to emit light in a quantity corresponding to the quantity of electrons impinging thereon, thereby displaying an 'image.

The anode 18 serves to attract electrons emitted from the cathode 12. The anode 18 also has a transparency allowing light from the phosphor film 16 to be transmitted therethrough.

The cathode 12 has a conical shape providing a tip. The cathode 12 emits electrons from the tip by virtue of an electric field established between the cathode 12 and gate 14.

A high voltage, which is lower than the voltage applied to the anode 18, is applied to the gate 14, thereby causing the gate 14 to guide emission of electrons from the cathode 12 to holes and the emitted electrons to be directed to the anode 18 to which the higher voltage is applied. Now, current-voltage characteristics of the FED constituted by field emission devices each having a general configuration as mentioned above will be described in conjunction with Fig. 2. As shown in Fig. 2, there is no or little cathode current Ic until the voltage V_G._C applied between the gate and the cathode reaches "V_L" during an activation of the FED. When the voltage V_G._C excesses "V_L", the cathode current Ic increases abruptly. That is, the FED exhibits characteristics as those of a diode . In Fig. 2, "V_H" represents a drive voltage applied to the gate. "V_H" is about 100 V whereas "V_L" is about 80 V.

Fig. 3 is a block diagram for describing a conventional panel driving circuit of a typical FED. In Fig. 3, the reference numeral 20 denotes a panel that is an image display region formed by field emission devices, arranged in the form of a matrix array in such a method that each of them corresponds to one pixel. The panel driving circuit includes a control means 22 that receives control signals and image signals, thereby outputting control signals and video signals meeting characteristics of the panel 20. A gate driver 24 is coupled to a plurality of gate lines. The gate driver 24 receives a control signal from the control means 22, thereby generating a signal for scanning a selected one of the gate lines. A data driver 26 is connected to a plurality of data lines. The data driver 26 receives an image signal from the control means 22, and converts the received image signal into an output image signal meeting the characteristics of the panel 20. The data driver 26 sends its output image signal to all pixels via the data lines .

In the illustrated configuration, the gate driver 24 is switched, based on the associated control signal from the control means 22, to generate a high voltage allowing emission of electrons every time an optional one of the gate lines is selected. At this time, the data driver 26 outputs, to the selected gate line, an image signal meeting the characteristics of the panel 20. Thus, a desired image is displayed on the panel 20.

The gate driver 24 or data driver 26 uses high- voltage output circuits which receive a low-voltage signal from a shift register, thereby transmitting a high voltage of 100 V or more to a gate stage (namely, a selected one of the gate lines) . The high-voltage output circuits will be described in conjunction with Fig. 4.

Fig. 4 illustrates one output circuit of the conventional driving circuit of Fig. 3 for driving one gate line or one data line (cathode line) .

The circuit of Fig. 4 includes high-voltage PMOS and NMOS devices PI and Nl connected in series between a high- voltage source V_high and a ground voltage source, and a high-voltage PMOS device controller 24a for controlling switching of the high-voltage PMOS device PI, based on an input signal IN from a control logic (not shown) . A drain node between the high-voltage PMOS and NMOS devices PI and Nl is coupled to a selected one of the gate lines (or a selected one of the data lines) of the FED panel 20. In accordance with the above conventional circuit, the high-voltage PMOS and NMOS devices PI and Nl conduct switching operations reverse to each other, respectively, in response to a start control signal inputted in sync with a clock signal, as shown in Fig. 5. In accordance with the reverse switching operations of the high-voltage PMOS and NMOS devices PI and Nl, the gate lines, for example, n, n+1, and n+2, are activated in a sequential method. In the case of Fig. 5, the gate lines n, n+1, and n+2 are activated by the high voltage V_hιgh at a rising or falling edge of the clock signal, respectively.

Electric power consumed at each output circuits of the conventional driver operating as mentioned above can be calculated. The following expression 1 represents electric power P_conv consumed at one output circuit of a gate driver.

[ Expression 1 ] P_conv = N f C_Load V_hιgh ² where, "N" represents the number of gate lines in the FED panel, "f" represents a frame frequency, "C_Load" represents the capacitance of one gate line, and "V_high" represents a voltage swing width at the output circuit.

When it is assumed that the voltage swing width V_high at the output circuit is 100 V, the power consumption P_conv can be expressed by the following Expression 2:

[Expression 2]

P_conv = 10000 N f C_Load

As apparent from the above Expression 2, the conventional gate driver exhibits a high power consumption because the output voltage at the output circuit thereof swings fully between zero V and V_high, for example, 100 V. Due to such a high power consumption, a large amount of heat is generated at the gate driver where the gate driver has an integrated circuit configuration. For this reason, the gate driver has a limited capacity, and its high- voltage devices have a reduced reliability. Such problems are also involved in drivers for driving cathode lines and anode lines.

DISCLOSURE OF THE INVENTION

Therefore, the present invention has been made in view of the above mentioned problems involved in the prior art, and an object of the invention is to provide a driving circuit for an FED which is capable of re-using charge accumulated in gate lines, cathode lines or anode lines, so that the swing width of the drive voltage for the FED resulting from a supply voltage is reduced, thereby achieving a reduction in power consumption while improving the reliability of high-voltage devices.

In accordance with the present invention, this object is accomplished by providing in a field emission display including a panel provided with a plurality of gate lines, a plurality of anode lines, and a plurality of cathode lines, a driving circuit for driving the field emission display, comprising: a plurality of output circuits connected to lines selected from the gate, anode, or cathode lines and adapted to charge the lines in a sequential method based on successive line selection control signals, respectively; a plurality of switching means each coupled between adjacent ones of the lines and adapted to conduct a switching operation based on a switching control signal; a plurality of logic operating means each adapted to receive an associated one of the line selection control signals while receiving a charge recycling signal transiting periodically to an activation level, thereby controlling a charge migration from a currently activated one of the lines to the line arranged adjacent to the currently activated line while being adapted to be activated following the currently activated line; and a plurality of switching controller each coupled to an associated one of the logic operating means while being coupled to an associated one of the switching means, each of the switching controllers serving to control the switching operation of the associated switching means based on an output signal from the associated logic operating means .

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and aspects of the invention will become apparent from the following description of embodiments with reference to the accompanying drawings in which :

Fig. 1 is a schematic view illustrating the structure of a typical FED;

Fig. 2 is a graph depicting current-voltage characteristics of a typical FED;

Fig. 3 is a block diagram for describing a panel driving circuit of a typical FED;

Fig. 4 is a circuit diagram illustrating a conventional output circuit of the driving circuit shown in Fig. 3;

Fig. 5 is a timing diagram of the circuit shown in Fig. 4;

Fig. 6 is a circuit diagram illustrating a driving circuit for an FED in accordance with an embodiment of the present invention;

Fig. 7 is a timing diagram of the driving circuit shown in Fig. 6;

Fig. 8 is a waveform diagram illustrating a voltage variation occurring in a gate line in accordance with the present invention; and

Fig. 9 is a circuit diagram illustrating a driving circuit for an FED in accordance with another embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Fig. 6 is a circuit diagram illustrating a driving circuit for an FED that is applied to gate lines in accordance with an embodiment of the present invention. As shown in Fig. 6, the driving circuit includes a plurality of output circuits each coupled to a selected one of gate lines, and a plurality of switching devices each coupled between adjacent ones of the gate lines. The driving circuit also includes a plurality of logic operating means, and a plurality of a high-voltage device controllers each coupled between an associated one of the logic operating means and an associated one of the switching devices. In Fig. 6, only two sets of those elements included in the driving circuit is illustrated. For the simplicity of description, the following description will be made only in conjunction with those two elements set of the driving circuit. An output circuit 28 is coupled to a gate line Gate_Line (n) and adapted to charge the gate line Gate_Line(n) with a desired voltage (V_high or zero V) , based on a gate line selection control signal Gate_Control (n) applied thereto from a shift register (not shown) , when a charge recycling signal Charge_Recycling is in its inactive state "L" . When the charge recycling signal Charge_Recycling is in its active state "H", the output circuit 28 is in its high impedance state.

An output circuit 30 is coupled to a gate line Gate_Line (n+1 ) and adapted to charge the gate line Gate_Line (n+1) with a desired voltage (V_hιgh or zero V), based on a gate line selection control signal

Gate_Control (n+1 ) applied thereto from a shift register

(not shown) , when the charge recycling signal

Charge_Recycling is in its inactive state "L" . When the charge recycling signal Charge_Recycling is in its active state "H", the output circuit 30 is in its high impedance state .

The output circuits 28 and 30 may have a typical CMOS inverter configuration. In this case, when the charge recycling signal Charge_Recycling is activated, high- voltage PMOS and NMOS transistors, which may constitute the CMOS inverter, turn off, thereby causing the CMOS inverter to be in its high impedance state. Such a design of the output circuits 28 and 30 is comparative to those of conventional gate drivers.

A logic operating means 32, which comprises a NAND gate having two inputs and one output, receives the gate line selection control signal Gate_Control (n) at one input thereof. The logic operating means 32 also periodically receives the charge recycling signal Charge_Recycling . The logic operating means 32 NANDs the received signals, thereby outputting a signal allowing about 50% of charge accumulated in the gate line Gate_Line (n) to migrate to the gate line Gate_Line (n+1 ) following the gate line Gate_Line (n) prior to an activation of the gate line selection control signal Gate_Control (n+1) .

A high-voltage device controller 34 controls the switching operation of a high-voltage switching device PI coupled between the adjacent gate lines Gate_Line (n) and

Gate_Line (n+1) , based on the output signal from the logic operating means 32.

A logic operating means 36, which comprises a NAND gate having two inputs and one output, receives the gate line selection control signal Gate_Control (n+1 ) at one input thereof. The logic operating means 32 also periodically receives the charge recycling signal Charge_Recycling. The logic operating means 32 NANDs the received signals, thereby outputting a signal allowing about 50% of charge accumulated in the gate line Gate_Line (n+1 ) to migrate to a gate line Gate_Line (n+2 ) following the gate line Gate_Line (n+1 ) prior to an activation of the gate line selection control signal Gate_Control (n+2) .

A high-voltage device controller 38 controls the switching operation of a high-voltage switching device P2 coupled between the adjacent gate lines Gate_Line (n+1 ) and Gate_Line (n+2) , based on the output signal from the logic operating means 36.

The charge recycling signal Charge_Recycling is activated to have a "high" level in each period of blanking time (including a horizontal blanking time and a vertical blanking time) or before the gate line selection control signal Gate_Control (x) for each gate line Gate_Line(x) is inactivated.

The horizontal and vertical blanking times exist between intervals of successive image signals respectively applied to the gate lines. In other words, the horizontal and vertical blanking times correspond to a period of time in which no image signal is inputted.

In accordance with the illustrated embodiment of the present invention, each of the high-voltage switching devices PI and P2 comprises a high-voltage PMOS transistor. Alternatively, the high-voltage switching devices PI and P2 may comprise a high-voltage NMOS transistor (as Nl or N2 in the case of Fig. 9) or an analog switch. Now, the operation of the driving circuit for an FED according to the embodiment of the present invention will be described in conjunction with the case in which the driving circuit is applied to gate lines.

Referring to Fig. 7, the gate line selection control signals Gate_Control (x) (including signals Gate_Control (n) , Gate_Control (n+1) , Gate_Control (n+2 ) , and Gate_Control (n+3) , ...) rise at successive rising edges of a clock signal Clock generated from a controller (not shown) , respectively. After rising in response to one rising edge of the clock signal Clock, an associated one of the gate line selection control signal Gate_Control (x) falls at a subsequent rising edge of the clock signal Clock. Thus, the gate line selection control signals Gate_Control (x) are applied to the output circuits 28, 30, ... in a sequential method, respectively. Based on the these gate line selection control signal Gate_Control (x) , the gate lines Gate_Line(x) (including lines Gate_Line (n) , Gate_Line (n+1) , Gate_Line (n+2 ) , and Gate_Line (n+3) , ...) are driven by a high voltage V_high in a sequential method, respectively.

The operation of the driving circuit will be described in more detail under the assumption in which the high voltage V_high is applied to the gate line Gate_Line(n) - in response to a rising edge of the clock signal Clock in an initial state of the driving circuit while the ground voltage of, for example, zero V, is applied to the gate line Gate_Line (n+1) following the gate line Gate_Line (n) .

After a desired period of time elapses from the initial state of the driving circuit, the charge recycling signal Charge_Recycling transits to a "high" level in a horizontal or vertical blanking time interval existing in the period of time, during which the gate line Gate_Line(n) is driven, or within a period of time preceding or following a subsequent rising edge of the clock signal Clock. At this time, the output circuit 28 generates an output exhibiting a high impedance state. The logic operating means 32 applies a "low"-level signal to the high-voltage device controller 34.

As a result, the high-voltage device controller 34 controls the high-voltage switching device PI to turn on. The high-voltage switching device PI migrates, at its ON state, a part (about 50%) of accumulated charge from the gate line Gate_Line (n) to the gate line Gate_Line (n+1 ) selected following the gate line Gate_Line (n) .

Accordingly, the voltage level of the gate line Gate_Line (n) drops from "V_high" to "V_hlgh/2" whereas the voltage level of the gate line Gate_Line (n+1) rises from "zero V" to "V_high/2", as shown in Fig. 8.

The quantity of migrated charge in this case and the voltage swing width resulting therefrom can be calculated using the following Expression 3:

[Expression 3]

Qτotal ^— C_Load V_high

^— ^c_Load v_CR where, "V_CR" corresponds to "V_high/2", and "Q_Totai" represents the total quantity of accumulated charge.

Since V_CR = V_nigh/2, and "Q_Totai" is constant, it can be found that the quantity of migrated charge corresponds to "^C _Load ^Vi_gh/2", and the voltage swing width corresponds to

For the period of time in which the selected gate line Gate-Line (n) is driven while the charge recycling signal Charge_Recycling is maintained at a "high" level, therefore, both the gate line Gate_Line (n) and the gate line Gate_Line (n+1) selected following the gate line Gate_Line (n+1) are maintained at a voltage level of "V_high/2", as shown in Fig. 8.

At a subsequent rising edge of the clock signal Clock, the charge recycling signal Charge_Recycling then transits to a "low" level. At this time, the gate line selection control signal Gate_Control (n+1) is rendered to have a "high" level. As a result, the voltage level of the gate line Gate_Line (n+1) rises from "V_high/2" to "V_high" because the gate line Gate_Line (n+1) is maintained in a "V_high/2"- charged state. On the other hand, the output circuit 28 is inactivated, thereby causing the gate line Gate_Line (n) to drop in voltage level from "V_high/2" to "zero V".

When the charge recycling signal Charge Recycling transits subsequently to a "high" level in the "V_high"- charged state of the gate line Gate_Line (n+1) , the logic operating means 36 generates a "low"-level signal which is, in turn, applied to the high-voltage switching device P2 via the high-voltage device controller 38. As a result, a part (about 50%) of accumulated charge from the gate line Gate_Line (n+1 ) to the gate line Gate_Line (n+2 ) selected following the gate line Gate_Line (n+1 ) via the high- voltage switching device P2.

As shown in Fig. 8, accordingly, the voltage level of the gate line Gate_Line (n+1 ) drops from "V_high" to "V_high/2". On the other hand, the voltage level of the gate line Gate_Line (n+2) rises from "zero V" to "V_high/2" by virtue of the migrated charge.

Since an increase in voltage resulting from an external supply voltage corresponds to "V_high/2" in the above case, the power consumption P_CR in accordance with the illustrated embodiment of the present invention can be derived as follows:

[Expression 4]

P_CR = (N f C_Load V_high ² ) / 2 where, "N" represents the number of gate lines in the FED panel, "f" represents a frame frequency, "C_Load" represents the capacitance of one gate line, and "V_high" represents a voltage swing width at one output circuit.

When it is assumed that the voltage swing width V_high at the output circuit is 100 V, the Expression 4 can be described again as follows: [Expres sion 5 ]

P_CR = 5000 N f C_Load

= P /2 where, "P_conv" represents electric power consumed in the conventional circuit shown in Fig. 2.

By referring to the above Expression 5, it can be found that the driving circuit according to the illustrated embodiment of the present invention achieves a reduction in power consumption by 50%, as compared to the conventional driving circuit.

As apparent from the above description, the present invention provides a driving circuit for an FED which is capable of reducing the swing width of the drive voltage for the FED, thereby achieving a reduction in power consumption and a reduction in the size of high-voltage switches used at output circuits thereof.

The reduction in power consumption also results in a reduction in the quantity of heat generated from the driving circuit. Accordingly, it is possible to achieve an improvement in the reliability of the driving circuit. Such a reduction in the generation of heat also results in an easy packaging process for gate driving circuits.

Since the size of high-voltage switches used at each output circuit of the driving circuit and the quantity of heat generated can be reduced in accordance with the present invention, as compared to the convention circuit, an increased number of output circuit can be integrated in a given size of the driving circuit. Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Claims

WHAT IS CLAIMED IS:

1. A driving circuit for driving the field emission display including a panel provided with a plurality of gate lines, a plurality of anode lines, and a plurality of cathode lines, comprising: a plurality of output circuits connected to lines selected from the gate, anode or cathode lines and for charging the lines based on line selection control signals successively; a plurality of switching means each coupled between adjacent ones of the lines and for conducting a switching operation based on a switching control signal; a plurality of logic operating means for receiving an associated one of the line selection control signals while receiving a charge recycling signal transiting periodically to an activation level, thereby controlling a charge migration from a currently one of the lines to the line arranged adjacent to the currently activated line while being adapted to be activated following the currently activated line; and a plurality of switching controller each coupled to an associated one of the logic operating means while being coupled to an associated one of the switching means, each of the switching controller serving to control the switching operation of the associated switching means based on an output signal from the associated logic operating means.

2. The driving circuit in accordance with claim 1, wherein the charge recycling signal transits to the activation level in a blanking time period existing between successive activation intervals of the lines.

3. The driving circuit in accordance with claim 2, wherein the blanking time period is a horizontal blanking time period.

4. The driving circuit in accordance with claim 2, wherein the blanking time period is a vertical blanking time period.

5. The driving circuit in accordance with claim 2, wherein the blanking time period includes a horizontal blanking time period and a vertical blanking time period.

6. The driving circuit in accordance with claim 1, wherein the charge recycling signal transits to the activation level just before every activation of the successive line selection control signals.

7. The driving circuit in accordance with claim 1(6), wherein each of the switching controllers control the charge migration in such a method that the line adapted to be activated following the currently activated line exhibits a voltage swing width corresponding to V_high/2 when the following line is activated, wherein V_h╬╣gh represents a maximum level of voltage applied to the lines.

8. The driving circuit in accordance with claim 1, wherein each of the logic operating means comprises a NAND gate.

9. The driving circuit in accordance with claim 1, wherein each of the switching means comprises a high- voltage MOS device.

10. The driving circuit in accordance with claim 9, wherein the high-voltage MOS device comprises a high- voltage PMOS transistor.

11. The driving circuit in accordance with claim 9, wherein the high-voltage MOS device comprises a high- voltage NMOS transistor.

12. The driving circuit in accordance with claim 1, wherein the output circuits are maintained in a high- impedance state when the charge recycling signal is in an activated state thereof.