KR20010031928A - Driving circuit for field emission display - Google Patents

Abstract

PURPOSE: A driving circuit of a field emission display is provided to reduce a power consumption and improve the reliability of a high voltage device by recycling the charge accumulated in a gate line, a cathode line or an anode line and reducing a driving voltage swing width by a supply voltage. CONSTITUTION: In a driving circuit of a field emission display, a plurality of output terminals(28,30) are connected to one line among a plurality of gate lines, anode lines and cathode lines and charge a corresponding line depending on a sequential line selection control signal from a shift register. Switching devices(P1,P2) are connected between the adjacent lines and perform a switching operation depending on a switching control signal. A plurality of logic operation devices(32) input the line selection signal and the charge recycling signal from a controller to control a charge movement from the current driving line to the next line. A device(38) for controlling a plurality of switching devices are connected to the plurality of logic operation devices one-to-one and are connected to the switching device. The plurality of switching devices switch and control the corresponding switching device depending on the signals from the respective logic operation device.

Description

DRIVING CIRCUIT FOR FIELD EMISSION DISPLAY}

Field Emission Display (FED), which is emerging as a new flat panel display, displays the screen in a similar way to the cathode ray tube (CRT), which displays the screen using emitted electrons. It is different from the cathode ray tube (CRT) using the thermal electron emission (thermal electron emission) in that it is used.

Such conventional field emission indicators install hundreds to thousands of field emission elements for emitting electrons per pixel, and impinge electrons from the field emission elements on an anode coated with a fluorescent film to display an image.

The field emission device constituting the pixel of the field emission indicator includes a cathode 12 connected to the cathode electrode 10 and a gate provided at regular intervals above the cathode 12, as shown in FIG. (14) and an anode 18 having a phosphor film 16 coated thereon.

Here, the fluorescent film 16 generates light corresponding to the amount of electrons colliding to display an image.

In addition, the anode 18 plays a role of attracting electrons emitted from the cathode 12, and also has transparency to transmit light by the fluorescent film 16.

The cathode 12 also has the shape of a horn forming the top of the tent and emits electrons from its tent by an electric field between the cathode and the gate 14.

In addition, the gate 14 induces the emission of electrons from the cathode 12 to the hole by a high voltage lower than the voltage applied to the anode 18, the emitted electrons are subjected to a higher voltage Facing towards the anode 18.

Looking at the current-voltage characteristics of a field emission indicator composed of such a general field emission device, as shown in FIG. 2, the voltage V _GC between the gate and the cathode reaches “V _L ” when the field emission indicator is driven. Until the cathode current I _C hardly flows until the voltage V _GC is higher than “V _L ”, the cathode current I _C is rapidly increased like the diode characteristic.

In the same figure, "V _H " is about 100V as the driving power applied to the gate, and "V _L " is about 80V.

3 is a block diagram illustrating a panel driving operation of a general field emission indicator. The panel 20 is an image display area in which the field emission elements in pixel units shown in FIG. 22 receives the control signal and the image signal from the outside and outputs the control signal and the image signal in accordance with the characteristics of the panel 20, the gate driver 24 is connected to a plurality of gate lines are input from the control means 22 Receives a control signal and generates a signal for scanning a corresponding gate line, and the data driver 26 is connected to a plurality of data lines and outputs an image signal input from the control means 22 according to the characteristics of the panel 20. After converting, we pass each pixel through the data line.

According to the figure, the gate driver 24 switches to a high voltage capable of emitting electrons whenever an arbitrary gate line is selected by the control signal of the control means 22, wherein the data driver 26 The video signal corresponding to the characteristics of the panel 20 is output to the selected gate line. Therefore, a desired image is displayed on the panel 20.

Here, the gate driver 24 or the data driver 26 uses a high voltage output terminal that receives a low voltage signal input from a shift register and transfers a voltage higher than 100V to a gate terminal (ie, a gate line). It will be described with reference to Figure 4 as follows.

4 shows a circuit for driving one gate line or data line (cathode line).

The circuit of FIG. 4 is connected by a high voltage PMOS device P1 and a high voltage NMOS device N1 connected in series between a _high voltage power supply V _high and a ground power supply, and an input signal IN from control logic (not shown). And a high voltage PMOS device controller 24a for switching and controlling the high voltage PMOS device P1, and a drain contact between the high voltage PMOS device P1 and the high voltage NMOS device N1 is connected to a gate line (or a gate line of the FED panel 20). Data line).

According to the conventional output stage circuit configured as described above, as shown in FIG. 5, the high voltage PMOS device P1 and the high voltage NMOS device N1 are input as the start control signal Start, which is shifted and output in synchronization with the clock signal Clk, is input. Are reversely switched to drive the gate lines (e.g., n, n + 1, n + 2) sequentially. Here, each of the gate lines n, n + 1 and n + 2 is sequentially driven at a _high voltage V _{high (for} example, 100 V) at a rising edge or a falling edge of the clock signal Clk. do.

The power consumption (P _CONV ) at the output of the conventional driver operating as described above is calculated as shown in Equation 1 below. Equation 1 is for the power consumption (P _CONV ) at the output terminal of the gate driver.

<Equation 1>

P _CONV = _Nf f C _Load V _high ²

Where N is the number of gate lines of the FED panel, f is the frame frequency, C _Load is the capacitance of one gate line, and V _high is the voltage swing width of the output stage.

When the voltage swing width (V _high ) of the output terminal is calculated to be 100V in Equation 1, the power consumption P _CONV is expressed by Equation 2 below.

<Equation 2>

P _CONV = _{10000NFfC Load}

As can be seen from Equation 2, in the conventional gate driver, since the output voltage of the output stage is full swing from 0V to V _H (for example, 100V), power consumption is not only large, thereby integrating the gate driving circuit. When circuitry, as the power consumption is large, high heat is generated to reduce the capacity of the integrated circuit, the problem of lowering the reliability of the high-voltage device and the problem of lowering the reliability of the high-voltage device due to voltage. This problem occurs almost similarly in the driver for driving the cathode line and the anode line.

The present invention relates to a field emission indicator, and more particularly to a driving circuit of a field emission indicator for driving a gate line and a cathode line and an anode line of the field emission indicator.

Other objects and arrangements of the present invention will become apparent from the following description of the accompanying drawings.

1 is a view schematically showing a structure of a general field emission device;

2 is a diagram showing current-voltage characteristics of a general field emission indicator;

3 is a block diagram for explaining a panel driving operation of a general field emission indicator;

4 is a circuit diagram of a high voltage output stage of the driver shown in FIG.

5 is a timing diagram of the circuit shown in FIG. 4;

6 is a driving circuit diagram of a field emission indicator according to an embodiment of the present invention;

7 is a timing diagram of a driving circuit of the field emission indicator shown in FIG. 6;

8 is a waveform diagram showing in detail the voltage change of the gate line according to an embodiment of the present invention;

9 is a driving circuit diagram of a field emission indicator according to another embodiment of the present invention.

Accordingly, the present invention has been made to solve the above-mentioned problems, and by recycling the charge accumulated in the gate line, the cathode line or the anode line to reduce the driving voltage swing width by the power source to reduce power consumption and reliability of the high-voltage device It is an object of the present invention to provide a driving circuit of the field emission indicator to improve the efficiency.

In order to achieve the above object, a driving circuit of a field emission indicator according to a preferred embodiment of the present invention is a field emission indicator having a panel having a plurality of gate lines, anode lines and cathode lines,

A plurality of output stages connected to one of the plurality of gate lines and the anode line and the cathode line and charging the corresponding lines by sequential line selection control signals from a shift register,

Switching means connected between mutually adjacent lines and switched by a switching control signal;

A plurality of logic operation means for receiving the line selection control signal and the charge recycling signal of a predetermined period from the controller and controlling the movement of the charge from the currently driven line to the subsequent line;

And a plurality of switching element control means connected to the plurality of logic operation means one-to-one and connected to the switching means to control switching of the corresponding switching means according to a signal from each logic operation means.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

6 is a diagram illustrating a driving circuit of a field emission indicator according to an exemplary embodiment of the present invention applied to a gate line. The output terminal 28 is connected to the gate line n, and the charge recycling signal Char_Recycling is inactive (“L”). ”), The gate line n is charged to a predetermined voltage (V _high or 0 V) by the gate line selection control signal Gate_Control (n) provided from the shift register (not shown), and the charge recycling signal When (Charge_Recycling) is activated (“H”), it has a high impedance state.

The output terminal 30 is connected to the gate line n + 1 and the gate line selection control signal Gate_Control (n) provided from the shift register (not shown) when the charge recycling signal Char_Recycling is inactive (“L”). +1)), the gate line n + 1 is charged to a predetermined voltage (V _high or 0 V) and has a high impedance state when the charge recycling signal Char_Recycling is in an active state (“H”).

The output stages 28 and 30 may be implemented in the form of a conventional CMOS inverter. Unlike the conventional gate driver, when the charge recycling signal Char_Recycling is activated, the high voltage PMOS transistor and the high voltage NMOS transistor implementing the CMOS inverter are turned off. Can be designed to have a high impedance state.

The logic operation means 32 comprises a NAND gate of two inputs and one output, and inputs a control signal Gate_Control (n) for selecting a gate line and a charge recycling signal (Charge_Recycling) of a predetermined period provided from a controller. By receiving the signal, a signal is output so as to move about 50% of the charge accumulated in the gate line Gate_Line (n) to the subsequent gate line Gate_Line (n + 1) in advance.

The high voltage device controller 34 is a high voltage switching device P1 connected between adjacent gate lines (that is, Gate_Line (n) and Gate_Line (n + 1)) in accordance with the signal output from the logic operation means 32. Switching control.

The logic operation means 36 comprises a NAND gate of two inputs and one output, and receives a gate line selection control signal (Gate_Control (n + 1)) and a charge recycling signal (Charge_Recycling) of a predetermined period provided from the controller. By processing, a signal is output so as to move about 50% of the charge stored in the gate line Gate_Line (n + 1) to the subsequent gate line Gate_Line (n + 2) in advance.

The high voltage device controller 38 includes a high voltage switching device connected between adjacent gate lines (that is, Gate_Line (n + 1) and Gate_Line (n + 2)) according to a signal output from the logic operation means 36 ( Switching control of P2).

In the figure, the charge recycling signal Charge_Recycling is a blanking time (horizontal blanking) that exists when driving each gate line Gate_Line (n), Gate_Line (n + 1), Gate_Line (n + 2), ... It is activated to the "high" level just before the time (Horizontal Blanking Time), Vertical Blanking Time (Vertical Blanking Time) or the selection control signal (Gate_Control (x)) for each line.

The horizontal blanking time and the vertical blanking time exist between the video signals of the respective gate lines, and are time periods at which the video signals are not input.

Further, in the embodiment of the present invention, the high voltage switching elements P1 and P2 are made of high voltage PMOS transistors, and may be formed of devices such as high voltage NMOS transistors (see FIG. 9; N1 and N2) or analog switches.

Next, the driving operation of the field emission indicator according to the embodiment of the present invention configured as described above is applied to the gate line to explain the driving operation as follows.

Referring to FIG. 7, each rising edge of the clock signal Clock provided with a gate line selection control signal Gate_Control (n, n + 1, n + 2, n + 3 ...) from a controller (not shown) It is applied to the corresponding output stages 28, 30, ... in order to rise at the edge and poll at the subsequent rising edge. Therefore, each gate line n, n + 1, n + 2, n + 3 ... is driven by the _high voltage power supply V _high .

Assume that the initial state of the embodiment of the present invention is a state in which a high voltage power supply V _high is applied to the gate line Gate_Line (n) and a ground voltage (for example, 0 V) is applied to the gate line Gate_Line (n + 1). It will be described in more detail.

Charge recycling within a predetermined time immediately before or after the horizontal blanking time or vertical blanking time or subsequent clock signal Clock rises when the gate line Gate (n) is driven as a predetermined time flows in the initial state. Since the signal Charge_Recycling is at the "high" level, the output of the output stage 28 is in a high-impedance state, and the logic operation means 32 sends the signal at the "low" level to the high voltage device controller 34. Is authorized.

As a result, as the high voltage switching element P1 is turned on by the high voltage element controller 34, a part (about 50%) of the charges charged in the gate line Gate_Line (n) becomes its high voltage switching element P1. It moves to the gate line Gate_Line (n + 1) to be selected subsequently through.

Thus, it said gate lines (Gate_Line (n)) voltage level "V _high" from "V _high / 2" is reduced to the level of the gate line to be selected for a subsequent (Gate_Line as shown in Figure 8 ( The voltage level of n + 1)) rises from "0V" to "V _high / 2".

Here, the amount of charge transfer and the resulting voltage swing width are calculated by Equation 3 below.

<Equation 3>

Q _Total = C _{LoadV high}

= 2C _{LoadV CR}

Since V _CR = V _high / 2, as can be seen from Equation 3, since the amount of charge is constant, the voltage swing width is "V _high / 2", and the amount of charge transfer is "C _Load V _high / 2".

Thus, the gate line n is selected and driven and the gate line Gaten (n) and subsequent as shown in FIG. 8 due to the movement of the charge while the charge recycling signal Char_Recycling maintains the “high” level. The potential of the gate line Gate_Line (n + 1) to be selected is maintained at "V _high / 2".

Thereafter, the charge recycling signal Char_Recycling becomes the "low" level at the next rising edge of the clock signal Clock, and the subsequent gate line selection control signal Gate_Line (n + 1) becomes the "high" level. Accordingly, since the gate line Gate_Line (n + 1) has already been charged by "V _high / 2", the voltage level of the gate line Gate_Line (n + 1) is set by the output terminal 30 to "V _high /". 2 "is elevated to an output stage 28, a voltage level of the gate lines (Gate_Line (n)) as the disabling""in" V _high is lowered to the _high V / 2 "from the" 0V ".

Then, when the charge recycling signal Char_Recycling becomes the "high" level while the gate line n + 1 is being charged to "V _high ", the signal of the "low" level in the logic operation means 36 is generated. The high voltage device controller 38 is applied to the high voltage switching device P2.

Thus, a portion (about 50%) of the charges charged in the gate line Gate_Line (n + 1) currently being selected and driven is subsequently selected by the gate line Gate_Line (n +) through the high voltage switching element P2. 2)).

Therefore, in this case, as shown in FIG. 8, the voltage level of the gate line Gate_Line (n + 1) is lowered from “V _high ” to “V _high / 2”, and the subsequent gate line Gate_Line (n The voltage level of +2)) increases from "0V" to "V _high / 2" by the amount of mobile charge.

When calculating the power consumption (P _CR ) according to the embodiment of the present invention described above, since the voltage rise by the external power source is "V _high / 2" is as shown in Equation 4 below.

<Equation 4>

P _CR = (Nf f C _{LoadV high} ² ) / 2

(N is the number of gate lines of the FED panel, f is the frame frequency, C _Load is one gate line capacitance, and V _high is the voltage swing width of the output stage.)

When "V _high " is "100V" in Equation 4, Equation 4 is equal to Equation 5 below.

<Equation 5>

_{P CR = 5000 · N · f} · C Load

= P _conv / 2

(Wherein P _conv is power consumption in the conventional method shown in Equation 2).

That is, according to the embodiment of the present invention, as can be seen from Equation 5, the power consumption is reduced by 1/2 compared to the conventional driving method.

According to the present invention as described above, not only can reduce the swing width of the output voltage by the power supply, but also can reduce the power consumption, thereby reducing the swing width of the output voltage by the power supply high voltage switch of the output stage The size of is reduced.

In addition, since the power consumption is reduced, the heat generation amount of the driving circuit is also reduced, so that the reliability of the device with respect to heat is improved, and the heat generation amount is also reduced, making the package of the gate driving circuit easier.

Furthermore, since the size and heat generation of the high voltage device can be reduced as compared with the related art, more output stages can be integrated in one integrated circuit, if necessary.

On the other hand, the present invention is not limited to the above-described embodiments, but may be modified, modified, and added within the scope not departing from the gist of the present invention.

Claims (12)

In a field emission indicator having a panel with a plurality of gate lines and an anode line and a cathode line, A plurality of output stages connected to one of the plurality of gate lines and the anode line and the cathode line and charging the corresponding lines by sequential line selection control signals from a shift register, Switching means connected between mutually adjacent lines and switched by a switching control signal; A plurality of logic operation means for receiving the line selection control signal and the charge recycling signal of a predetermined period from the controller and controlling the movement of the charge from the currently driven line to the subsequent line; And a plurality of switching element control means connected to the plurality of logical operation means one-to-one and connected to the switching means to control switching of the corresponding switching means according to a signal from each logical operation means. Driving circuit of the emission indicator. 2. The driving circuit of a field emission indicator according to claim 1, wherein said charge recycling signal is shifted to an activation signal level at a blanking time present when driving each line. 3. The driving circuit of a field emission indicator according to claim 2, wherein the blanking time is a horizontal blanking time. 3. The driving circuit of a field emission indicator according to claim 2, wherein the blanking time is a vertical blanking time. 3. The driving circuit of a field emission indicator according to claim 2, wherein the blanking time is a horizontal blanking time and a vertical blanking time. 2. The driving circuit of a field emission indicator according to claim 1, wherein the charge recycling signal is shifted to an activation signal level just before the selection control signal for each line is deactivated. 7. The driving circuit of a field emission indicator according to claim 6, wherein, when the charge recycling signal is activated, the voltage swing width at the time of charge transfer from the previously activated line to the next line is "V _high / 2". Where V _high is the highest voltage applied to the line. 2. The driving circuit of a field emission indicator according to claim 1, wherein said plurality of logic operation means is a NAND gate. 2. The driving circuit of the field emission indicator according to claim 1, wherein the plurality of high voltage switching means comprises a high voltage MOS device. 10. The driving circuit of claim 9, wherein the high voltage MOS device is a high voltage PMOS transistor. 10. The driving circuit of claim 9, wherein the high voltage MOS device is a high voltage NMOS transistor. 2. The driving circuit of claim 1, wherein the plurality of output terminals have an impedance state when the charge recycling signal is in an active state.