WO2000008786A1 - Circuit and method for receiving and transmitting data - Google Patents
Circuit and method for receiving and transmitting data Download PDFInfo
- Publication number
- WO2000008786A1 WO2000008786A1 PCT/DE1999/002077 DE9902077W WO0008786A1 WO 2000008786 A1 WO2000008786 A1 WO 2000008786A1 DE 9902077 W DE9902077 W DE 9902077W WO 0008786 A1 WO0008786 A1 WO 0008786A1
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- WO
- WIPO (PCT)
- Prior art keywords
- time slot
- data
- tsn
- unit
- storage unit
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
Definitions
- high-level data link controllers are used for data transmission at network interworking points.
- These HDLC controllers are arranged at network interchanges, for example between a network with a synchronous data transmission and a network with an asynchronous data transmission.
- the choice of a data transmission rate or a time slot width is specified by the transmission speed of the interworking units.
- a time slot width was previously preset using marked fields. However, this has the disadvantage that the data transmission can only be carried out in the time slots marked for this purpose.
- the invention has for its object to provide a circuit arrangement and a method that eliminates the disadvantage listed above.
- the invention has the advantage that all time slots of a transmission frame can be used for the transmission of data.
- the invention has the advantage that the number of channels for an HDLC controller can be changed by changing configuration parameters.
- FIG. 1 shows a schematic representation of a transmission path
- FIG. 2 shows a structure of a transmission frame
- FIG. 3 shows a schematic structure of an HDLC controller
- FIG. 4 shows a block diagram of an HDLC receiving unit
- FIG. 5 shows a block diagram of an HDLC transmission unit
- FIG. 6 shows a more detailed representation an HDLC receiver unit
- FIG. 7 shows a more detailed illustration of an HDLC transmission unit.
- FIG. 1 A network configuration of a data transmission link is shown in FIG.
- This network configuration consists of a data network AD for asynchronous data transmission and at least one data network SD for synchronous data transmission.
- the data network AD for asynchronous data transmission can be, for example, an ATM network, an integer network, a Datex-P network or an ether network.
- For synchronous data transmission in the data networks SD for example PCM systems or a synchronous transfer mode STM can be used.
- High-level data link controllers HDLC are arranged at the interfaces between the synchronous and the asynchronous data network AD or SD.
- a large number of data terminals TL can be connected to a network termination point NT of the synchronously operating data network SD.
- a data terminal TL is assigned one or more time slots or time channels for data transmission between the network termination point NT and the interface between the data networks AD, SD.
- FIG. 2 shows a transmission frame of a PCM transmission system as used in the data network SD with synchronous data transmission.
- This PCM transmission frame is, for example, 16 bits long and can be divided into a maximum of 16 time slots or channels. The smallest possible time slot can be one bit, the largest time slot can comprise 16 bits.
- the bits of the transmission frame are numbered from 0 to 15.
- the first time slot TS with the time slot width TSB of 3 bits has the time slots TS or channels 0, 1 and 2 combined to form a data transmission channel.
- the designation of the respective time slot TS takes place through the number of the first channel at the beginning of the time slot TS.
- the first time slot TS is assigned the number of the first bit.
- the second time slot TS which comprises channels 3, 4, 5 and 6, the second time slot TS has the time slot number TS corresponding to the number of the first bit of the second time slot TS.
- the third and fourth time slots are designated TS7 and TS8.
- FIG. 3 shows the structure of a high-level data link controller HDLC.
- This HDLC controller essentially has an HDLC receiver unit HDLC-E, an HDLC transmitter unit HDLC-S, an HDLC processor HDLC-P and a frame buffer FB.
- the HDLC receiver unit HDLC-E and the HDLC transmitter unit HDLC-S are each connected to lines of the synchronously operating data network SD.
- the frame buffer FB is connected to an asynchronous controller AC of the asynchronously operated data network AD.
- the HDLC controller shown is essentially divided into three processing units. Among other things, each of the processing units is designed to reduce the speed requirements of the next stage.
- the processing the current time slot is processed on the basis of state parameters and the state parameters are loaded for a time slot following the current time slot.
- the state parameters are, for example, the time slot length, state, bit counter, shift register content, etc.
- the state parameters of the current time slot are temporarily stored in a first storage unit and the state parameters of the coming time slot, which were previously stored temporarily, are saved to the HDLC processor HDLC-P forwarded.
- the complete data words are output or read in on a data port.
- the HDLC processor HDLC-P can be divided into two halves on the receiving and transmitting sides. Each half comprises a second processing unit BV, BVS and a third processing unit FV, FVS.
- state parameters associated with time slots are managed in a second storage unit ST, STS and the data words are read from or reloaded from or in a part of the first storage unit SE, SS to the data hold DH, DHS register (see Fig. 6, 7). Furthermore, the state parameters are assigned to the first memory unit SE, SS.
- the data are forwarded to or received from a third processing unit FV, FVS via separate data paths.
- FIG. 4 shows a block diagram of the HDLC receiver unit HDLC-E.
- the essential units are a serial-parallel converter S / P, an HDLC processor HDLC-P and the data hold register DH to be assigned to either the first processing unit WSPE or the HDLC processor HDLC-P and a state parameter register SP.
- the data transported on a serial data bus DB of the synchronous data network SD are read in serially in a serial-parallel converter S / P, which can also be referred to as a shift register.
- the data of the receiver unit HDLC-E and the content of the serial-parallel converter S / P are reloaded into the register SP provided for the state parameters (see FIG. 6). If the data is complete within the time slots, these are transferred to the data hold register DH. At the same time, the data of a subsequent time slot are loaded into the register SP and the receiving unit HDLC-E is preset with the temporarily stored data for the subsequent time slot of the previous PCM frame.
- FIG. 5 shows a block diagram of the HDLC transmitter unit HDLC-S. This is used to insert the data to be sent into a data bus DB via the parallel-serial converter P / S. Whenever a data word has been output on the data bus DB, a new data word is loaded from the data hold register DHS into the parallel-serial converter P / S. At the beginning of a new time slot, all data and states of the HDLC processor HDLC-P, which were temporarily stored in the data hold register DHS and in the state parameter register SPS, are exchanged by the HDLC processor HDLC-P.
- the HDLC-E HDLC-E unit is shown in detail in FIG.
- the essential elements of the HDLC-E HDLC-E are the serial-parallel converter S / P, the register Data-Hold DH, a state parameter register SP, a unit for byte processing BV, a unit for frame processing FV and a Framebuffer FB.
- the data temporarily stored in the state parameter register SP for a time slot are stored in a state table ST of the byte processing unit BV after the current time slot.
- the state table ST is organized in the byte processing unit BV in such a way that the data of an upcoming time slot are loaded into the state parameter register SP each time a time slot changes.
- the data retrieved from the data hold register DH are classified and processed in an event queue EQ, a link between the byte processing unit BV and the frame processing unit FV.
- the data from the data bus DB are read out using the serial-parallel converter S / P of the first processing unit (WSPE).
- the data is stored in the DH data hold register.
- all data and associated states are exchanged between the serial-parallel converter S / P and the state parameter register SP.
- the time slot width, the register content and its state as well as other parameters are buffered in the state parameter register SP.
- the state parameters that were read into the state parameter register SP are temporarily stored in the state table ST.
- the size of the state table ST corresponds to the maximum number of possible time slots of a transmission link in the synchronously operating data network SD.
- a start of a time slot following a current time slot is calculated from the status data of the current time slot.
- the event queue EQ which is arranged between the byte processing unit BV and the frame processing unit FV, is organized in such a way that prioritization is possible in accordance with the transmission speed of a time slot or channel.
- the data of all HDLC channels is stored in the frame buffer FB downstream of the frame processing unit FV.
- FIG. 7 shows the HDLC transmitter unit HDLC-S. In accordance with the arrow direction shown in the schematic illustration, the data to be transported in time slots or channels are read out of the frame buffer FB.
- the relevant time slot numbers TS no. are assigned to the data words and fed to a data hold register DHS via a data table DTS to be cached there.
- the initialization data STS required for the HDLC processor HDLC-P are converted from a state table in the byte processing unit BVS into a second storage unit STS by an assignment unit ZU in the second storage unit STS saved.
- the data words temporarily stored in the DHS data hold register are inserted as intended in the time slots provided for this purpose, due to the initialization of the high-level data link control processor HDLC-P.
- the portion of the data word that has not yet been processed, together with the current status values of the high data link control processor HDLC-P is transferred from the state parameter register PLC to the second memory unit
- the state parameters in the state parameter register PLC and the data words in the data hold register DHS simultaneously arrive for the subsequent time slot Tsn + x of the PCM frame.
- the data temporarily stored in the data hold register DHS is inserted into the time slots of the PCM frame.
- the state parameters of the high-level data link control processor HDLC-P and the data are loaded into the data hold register DHS, or the state parameters are loaded into the state parameter register PLC and in the state STS table cached.
- New for Data and settings required for the high-level data link control processor HDLC-P for the upcoming time slot are determined by the allocation unit ZU.
- the data for the data table DTS are forwarded using the event queue EQS.
- the data table DTS the data of all possible time slots are buffered in a transmission frame for the data hold register DHS. This makes it possible to carry out frame processing even outside the time slot.
- the event queue EQS data processing according to the respective transmission speed is possible.
- the time slot numbers TS number of the last, current and following time slot are calculated in the byte processing unit BVS from the position of the time slot and the time slot length in the transmission frame.
- the state parameters PLC of all time slots to be processed are stored in the state table STS.
- the size of the STS state table always corresponds to the maximum possible number of time slots.
- the state parameters, which are entered in the state parameter register PLC contain the following information: time slot width, bit number in the data word as well as the content of the shift register and other status information.
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Small-Scale Networks (AREA)
- Communication Control (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP99945915A EP1101306A1 (en) | 1998-07-31 | 1999-07-06 | Circuit and method for receiving and transmitting data |
JP2000564319A JP2002522949A (en) | 1998-07-31 | 1999-07-06 | Circuit device and method for receiving and transmitting data |
CA002338867A CA2338867A1 (en) | 1998-07-31 | 1999-07-06 | Circuit arrangement and method for receiving and transmitting data |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19834630.1 | 1998-07-31 | ||
DE19834630 | 1998-07-31 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000008786A1 true WO2000008786A1 (en) | 2000-02-17 |
Family
ID=7876032
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE1999/002077 WO2000008786A1 (en) | 1998-07-31 | 1999-07-06 | Circuit and method for receiving and transmitting data |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP1101306A1 (en) |
JP (1) | JP2002522949A (en) |
CA (1) | CA2338867A1 (en) |
WO (1) | WO2000008786A1 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5029163A (en) * | 1988-03-18 | 1991-07-02 | At&T Bell Laboratories | Synchronous protocol data formatter |
US5619500A (en) * | 1994-09-01 | 1997-04-08 | Digital Link Corporation | ATM network interface |
-
1999
- 1999-07-06 JP JP2000564319A patent/JP2002522949A/en not_active Withdrawn
- 1999-07-06 WO PCT/DE1999/002077 patent/WO2000008786A1/en not_active Application Discontinuation
- 1999-07-06 EP EP99945915A patent/EP1101306A1/en not_active Withdrawn
- 1999-07-06 CA CA002338867A patent/CA2338867A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5029163A (en) * | 1988-03-18 | 1991-07-02 | At&T Bell Laboratories | Synchronous protocol data formatter |
US5619500A (en) * | 1994-09-01 | 1997-04-08 | Digital Link Corporation | ATM network interface |
Also Published As
Publication number | Publication date |
---|---|
CA2338867A1 (en) | 2000-02-17 |
EP1101306A1 (en) | 2001-05-23 |
JP2002522949A (en) | 2002-07-23 |
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