DE10260806A1 - Network interface, especially an Ethernet interface, has a hard-wired interface circuit that permits the forwarding of data packets between ports before they have been completely received - Google Patents

Abstract

Network interface (2) has three ports that are hard-wired together via an interface circuit (11). One of the ports is an internal port (8) with which a terminal (1) is connected to the interface. Two of the ports (9, 10) are external ports with which network lines (3) are connected to the interface. The ports operate in full duplex mode. Data can be distributed to the ports before a data packet is completely received.

Description

The present invention relates to a network connection, in particular an Ethernet connection.

With the increasing use of Network technologies that come from the field of office communication, e.g. B. Ethernet, Token Ring, ATM and others, also in the field of industrial automation wins an inexpensive Networking of end devices via such Network technologies are becoming increasingly important.

With the network technologies of office communication networking is usually via nodes (hubs, switches), of which star-shaped Make point-to-point connections to the individual devices. This is for Applications in the industrial environment, in which often linear structures present, disadvantageous.

From the US-A-5,802,278 a network interface is already known that has exactly three ports. One of the ports is an internal port via which a terminal can be connected to the network interface. The other two ports are external ports, via which a network cable can be connected to the network interface. A so-called media access controller (MAC) is arranged between the ports. This MAC receives data packets, stores them temporarily and sends them on - possibly only via one of the other ports.

The teaching of the state of the art has a number of disadvantages.

First, the MAC is complex. The Network connection as a whole is therefore relatively expensive. Furthermore Always receive complete data packets and only after complete receipt forwarded. Therefore, a large buffer is required on the one hand others kick big delay times on. Especially the delay times represent a disadvantage. Because in the field of industrial automation the real-time behavior of a networked system is also important. The delay times that occur in the prior art are however so large, that they have real-time capability of the networked system.

The object of the present invention consists of a generic network connection to develop in such a way that they are easier and less expensive can be produced and in particular also when using this network connection for Building line structures that maintain real-time capability as much as possible remains.

The task is solved by

• - that the ports over a hard-wired connection circuit interconnected are,
• - that the ports can be operated in full duplex mode and
• - that the connection circuit is designed such that data of a Data packet that is fed to the network interface via one of the ports even before the full Feeding the Data packet over at least one of the other ports can be output.

The network connection according to the invention is not just in terms of the number of its ports tailored to a line application. Furthermore is fast thanks to the hard-wired connection circuit Signal processing and a quick response to the reception of Data possible. Full duplex operation means that data can be received at the same time and broadcast. Above all, the output of data becomes one Data packet a clear before the complete delivery of the data packet Reduce memory requirements and delay times reached.

If the connection circuit is like this is formed that one of the network interface over the internal port fed Data packet always over both external ports is output, the connection circuit is easier structured. Because then when sending a data packet supplied via the internal port no evaluation of the target information of the data packet required.

The data packets contain in the Usually at least one source address and one destination address. The connection circuit is therefore preferably designed such that it has at least one of the filtering below:

• - At one of the network interface over one of the external ports Data packet is first extracted the destination address. The data packet is then only via the internal port output if the target address is a terminal switching condition Fulfills. The terminal switching condition can then be met in particular if the target address matches the address of the connected device. If necessary, you can multicast and broadcast data packets can also be switched through. Maybe you can for multicast and broadcast data packets also the type and / or the functionality of the data packet can be used to check whether the terminal switching condition Fulfills is.
• - In a similar way Way can also be checked whether the destination address of the over one of the external ports Data packet fulfills a network switching condition. Just if fulfilled this network switching condition, the data packet over the another external port. The network switching condition can then be met in particular if the destination address does not match the address of the end device.
• - The source address can also be extracted. In this case, the data packet is only sent via the internal port and the whose external port is output if the source address fulfills a source switching condition. The source switching condition can consist in particular in that the source address is different from the address of the terminal. This is because circular rotors in particular are filtered out.

To review the above conditions to allow the connection circuit has at least one buffer on, in the data supplied to the network interface of a data packet be temporarily stored until the check as to whether the terminal switching condition, the network switching condition and / or the source switching condition is or are completed is. For every port, regarding whose switching condition is checked is a separate one Buffer required.

In a simple version, the Connection circuit but also be designed such that a the network connection via one of the external ports Data packet always over the internal port and the other external port is output. Because then the connection circuit is structured more simply because no evaluation of an incoming data packet is necessary, if this over one of the external ports is received.

The connection circuit is preferably such trained that data one of the network interface over a of the ports fed Data packets are stored in a buffer until the Data has assumed a minimum size, and only then when the data packet is output via at least one of the others Ports is started. Because then it cannot happen that the Buffer completely emptied by reading out the data to be sent because the data is read and sent faster than to lead and writing the data into the buffer. If the data packet one size below the minimum size, can of course the data packet can already be output if the Data packet complete is stored in the buffer.

If the external ports as medium-independent interfaces (MII) are trained and the network lines via physical Layer devices can be connected to the external ports is the network connection and in particular their connection circuit independent of the physical design of the network lines can be designed.

Even if the internal port as a medium-independent interface (MII) is formed, the terminal is directly to the internal port connectable.

The connection circuit is preferably such trained that one of the ports through another of the ports supplied Data packet from the one port is cached if it from the A data packet is already fed to the third port. Because then kick no data loss, although simultaneously on the other two ports Data are accepted.

To implement the buffer it is particularly possible that the external ports cache for caching Data packets are assigned to the network connection via the internal port fed be, with a maximum of one in the buffer at any time Data packet can be saved. The management of several over the internal port to be fed Data packets then take place within the terminal device to implement the intermediate storage are also preferably the external ports buffer Intermediate storage of data packets assigned to the network connection via the each other external port are supplied, in this Buffer more than one data packet can be stored.

The larger dimensioning of the buffer for the external ports taken into account especially the usually higher one Data volume over the network lines. If there is more than one buffer per external port is there is in particular a prioritization of the other external port received data packets possible. This may result to an improved real-time behavior for time-critical data packets.

The internal port is also preferably at least assigned a buffer for buffering data packets, over the network interface one of the external ports be, with more than one in this buffer Data packet can be saved.

Also the dimensioning of the buffer or the cache of the internal port usually takes this into account higher Data volume over the network lines. If there is more than one cache is available, for example, each external port has its own Buffer can be assigned. Alternatively - or with a sufficient number Caching also additionally - can also between different priorities can be easily distinguished.

The data packets are usually priorities assigned. Therefore, when the external ports are assigned packet controls by means of which several of the external ports can be output Data packets always the highest priority Data packet output first is a simple prioritization of data traffic possible.

Preferably, the data packets supplied to the network connection via the internal port are alternatively assigned a high or low priority and the data packets supplied to the network connection via the external ports are assigned a medium priority. This is because - at least as a rule - data packets that are already in transmission have priority over new ones Data packets. Blocking the network by a single end device is therefore very unlikely. On the other hand, due to the possibility of also assigning a high priority to the data packets of the internal port, priority feeding of a newly added data packet is possible in individual cases.

If using the package controls supplied to the external ports Data packets can be delayed in this way are that between the end of one through one of the external ports output data packet and the beginning of the next output via this external port If there is a minimum pause for data packets, there are automatically gaps in the Data stream in which other network interfaces their data packets can feed.

If the minimum break from the priority of the sending data packet depends and / or depends on whether the data packet to be sent from the network interface via the internal port or via the other external port is a priority feed into the Network. For this purpose, in particular the minimum break can be set in such a way that the bigger it is the lower the priority of the data packet to be sent.

If the network connection is a Interface circuit via which the connection circuit is parameterizable, the network connection is particularly flexible and universally applicable.

If at least the network connection as electronically programmable circuit, e.g. B. as a field programmable gate ar ray (FPGA) or as electronically programmable logic device (EPLD), is formed, even with small quantities can be implemented in a particularly simple manner and integrated into the overall system.

However, if the network connection as ASIC is trained, it is particularly in large quantities economical produced.

If the network connection from terminal is particularly easy to supply with electrical energy educated. Alternatively or additionally is also possible that the network connection is independent of the end device, especially via a of the network lines, can be supplied with electrical energy.

Other advantages and details result from the following description of an exemplary embodiment in conjunction with the drawings. Show in principle

1 several end devices connected in line topology,

2 a terminal with a network connection,

3A - 3C a connection circuit and an interface,

4 a data packet,

5 a flow chart,

6A - 6D an extension of the connection circuit of the 3A - 3C .

7 a correction circuit and

8th another flowchart.

According to 1 are multiple devices 1 via network connections 2 and network lines 3 networked with each other. The networking between the end devices 1 takes place, for example, according to the Ethernet standard.

The end devices 1 usually have an intelligent unit 4 , e.g. B. a microcontroller or a microprocessor, and a media access controller 5 (MAC 5 ) on. The intelligent units 4 are with the MACs 5 via address / data buses 6 connected. The MACs 5 are with the internal ports 8th the network connections 2 connected.

The internal ports 8th are designed as media-independent interfaces (MII). The end devices 1 are therefore directly to the internal ports 8th connectable.

The network lines 3 can be electrical or optical fibers. Mixed forms are also possible. They are about physical layer devices 7 to the network interfaces 2 switched on, to external ports 9 . 10 the network connections 2 , The physical layer devices 7 include the send drivers for the data to be sent and the threshold converters for binarizing the received data. Even the external ports 9 . 10 are thus designed as media-independent interfaces (MII).

As already out 1 and more clearly 2 can be seen are the lines through which from the ports 8th to 10 Data are sent, different from the lines via which the ports 8th to 10 Data are supplied. The ports 8th to 10 are therefore operated in full duplex mode, i.e. with simultaneous sending and receiving of data. This is particularly advantageous due to the lack of an intermediate MAC.

The data are sent and received with a transmission clock of e.g. B. 100 MHz. The connection circuit works internally 11 with an internal clock that is lower than the transmission clock. The internal clock is e.g. B. only 25 MHz.

As further from the 1 and 2 can be seen, show the network connections 2 except for the ports already mentioned 8th to 10 no further ports for data exchange with the network. So there are exactly three ports 8th to 10 available.

The ports 8th to 10 are according to 2 via a connection circuit 11 interconnected. The connection circuit 11 does not process a software program, but is a hard-wired connection circuit 11 educated. It contains the control units, the buffers and the connecting lines for the ports 8th to 10 ,

The network interface 2 is a power supply device 12 assigned. The stream supply device 12 can e.g. B. with supply lines 13 be connected via the terminal 1 is supplied with electrical energy. In this case the network connection is 2 So from the end device 1 can be supplied with electrical energy.

Alternatively or additionally, it is also possible to use the network connection 2 regardless of the device 1 to supply with electrical energy. In particular, as in 2 shown, a supply via the network lines 3 possible. It is even possible to use the power supply device 12 to supply electrical energy in both ways. In this case, the power supply device 12 preferably a monitoring circuit, by means of which the supply lines break down when the power supply breaks down 13 to the alternative power supply, for example via the network lines 3 , is switched.

The network connection 2 also has an interface circuit 14 on. About this interface circuit 14 is in particular the connection circuit 11 parameterized. This will be discussed in more detail later.

The network connection 2 can, as in 2 is indicated by a dashed frame with appropriate labeling, can be designed as a field programmable gate array (FPGA) or as an electronically programmable logic device (EPLD). In this case it is an electronically programmable circuit 11 educated. In principle, the connection circuit could 11 but also be designed as a non-programmable circuit, for. B. as an integrated circuit, in particular as an ASIC. The power supply device 12 is there, as also in 2 shown, arranged outside the circuit.

The internal structure of the connection circuit 11 will now be used in conjunction with 3A to 3C explained in more detail how the connection circuit works 11 combined with 5 , In addition, the structure of a typical data packet as used in 4 is shown.

According to 3 assigns the connection circuit 11 an internal block 15 and two external blocks 16 . 17 on. The blocks 15 to 17 are there - see 2 - all within the connection circuit 11 arranged. The internal block 15 but is the internal port 8th assigned (hence the designation as an internal block), the external blocks 16 . 17 the external ports 9 . 10 (hence the name as external blocks).

If the network connection 2 from the terminal 1 via the internal port 8th If a data packet is to be fed in, this is done as follows:
A receiving machine 18 of the internal block 15 is via an AND gate 19 the corresponding logical combination of two enable bits is supplied. One of the enable bits comes from one of the external blocks 16 . 17 , The release bits are from sending machines 20 . 21 of the external blocks 16 . 17 set to logical one if buffer 22 . 23 are empty. The cache 22 . 23 are organized according to the FIFO principle (FIFO = first-in-first-out).

If both buffers 22 . 23 are empty, the receiving machine picks up 18 from the terminal 1 a data packet and forwards it via a data output 24 and data inputs 25 . 26 the caches 22 . 23 to. The data transmission takes place z. B. in so-called nibbles, i.e. in groups of 4 bits each. The data packet is therefore in the buffer 22 . 23 enrolled. The cache 22 . 23 thus serve to temporarily store data packets that are used for network connection 2 via the internal port 8th are fed. Due to the fact that the data packets are only then cached 22 . 23 be written when the cache 22 . 23 have been emptied before, is at any time in the buffer 22 . 23 only one data packet can be stored. If necessary, further data packets are sent from the end device 1 managed.

The caches 22 . 23 are occupancy investigators 27 . 28 assigned. The occupancy investigators 27 . 28 first determine whether the cache 22 . 23 are documented as to whether data to be sent are stored in them. If this is the case, appropriate information is sent to the sending machines 20 . 21 given, which then reset the release bits. The occupancy investigators also determine 27 . 28 whether the following conditions are met:

• a) The data packet is completely in the buffer 22 . 23 enrolled.
• b) The in the buffer 22 . 23 Inscribed data of the data packet have a minimum size of z. B. 50 bytes reached.

As soon as one of these two conditions is fulfilled (OR link), the occupancy officers will transmit 27 . 28 a ready-to-send bit to the sending machines 20 . 21 ,

Finally, the occupancy investigators determine 27 . 28 by analyzing the data packet still its priority. When the data packet is recognized as a high priority, a priority bit is sent to the sending machines 20 . 21 is set to one.

The question of whether that's in the cache 22 . 23 - completely or partially - stored data packet is now sent immediately and immediately depends on a variety of circumstances, which will be discussed later. At this point, however, it should be mentioned that - if the further transmission conditions are met - the data of the data packet is output via the external ports 9 . 10 is started as soon as the transmission ready bit is set. So there is no waiting until the data packet is completely in the buffer 22 . 23 is stored. Rather, the connection circuit 11 formed in such a way that the data of the data packet is already supplied via the external ports before the data packet is completely supplied 9 . 10 be issued. Something else applies only to extremely small data packets whose total size is below the minimum size of e.g. B. is 50 bytes.

The output is not started with the first stored bit, nibble or byte. It waits until in the intermediate stores 22 . 23 - at least for longer data packets - the minimum number of data is stored.

The procedure described above to start outputting data of the data packet and, alternatively, the data packet completely into the buffer 22 . 23 is stored or in the buffer 22 . 23 stored data of the data packet have reached a minimum size, of course applies to both external ports 9 . 10 , Conversely, it also applies when connecting to the network 2 via one of the external ports 9 . 10 Data are fed to the internal port 8th and / or the other external port 10 . 9 forwarded and issued there.

From the above statements, it is also evident in particular that the connection circuit 11 is designed such that the data packet is always via both external ports 9 . 10 is output when the data packet of the network interface 2 via the internal port 8th is fed.

If vice versa the internal block 15 the network connection 2 a data packet is fed to the network interface 2 via one of the external ports 9 . 10 this is done as follows:
How out 4 can be seen, the data packet has a destination address and a source address. The source address is always a unique single address. The destination address can be a single address. However, it can also be a multiple address that is used for several or even for all end devices 1 is valid.

The internal block 15 points according to 3A Adressextraktoren 29 and an address comparator 30 on. The address extractors 29 first extract the destination address from the data packets supplied to them. The destination address becomes the address comparator 30 fed. The address comparator 30 compares the target address with (at least) an internally stored filter address. If the extracted target address corresponds to this filter address or one of the filter addresses, the address comparator transmits 30 a release bit to the transmitting extractor 29 , Only in this case is the supplied data packet sent to an internal data path investigator 31 passed. Otherwise, it will not be forwarded and therefore in particular from the internal port 8th kept away.

The check in the address comparator 30 includes in particular a check whether the target address is identical to the filter address. It also includes a check whether the target address, if it is a multiple address, also includes the filter address. If necessary, further tests for the type and / or function of the data packet are possible. However, this is not necessary.

As a result, the data packet is only sent via the internal port 8th output when the destination address of the data packet meets a switching condition, hereinafter called terminal switching condition.

It takes time to extract the destination address and check the destination address. During this time, the internal block 15 via its corresponding data input 32 data continues to be supplied. The internal block 15 and with it the connection circuit 11 therefore has a buffer 33 in which this data is temporarily stored until the check as to whether the terminal switching condition is fulfilled is completed. This cache 33 can be made relatively small. It is preferably organized as a FIFO memory. It is written and read out cyclically.

Because the traffic on the ports 8th to 10 runs independently, it is possible that the internal block 15 over both data inputs 32 data are supplied simultaneously. The data path investigator 31 therefore checks if he receives data from one of the address extractors 29 whether it is already supplied by the other address extractor 29 Data are fed and where he outputs this data. If the data path investigator 31 this other data directly to a sending machine 34 of the internal block 15 outputs, it stores the later received data of the other data input 32 in a buffer 35 from. Otherwise, it sends them directly to the sending machine 34 further. The cache 35 is also organized according to the FIFO principle. He can, as in 3A indicated to cache more than one data packet at a time. It is in this cache 35 that is, more than one data packet can be stored.

Similarly, as in 3B indicated by dashed lines, also the external blocks 16 . 17 Adressextraktoren 36 and address comparator 37 exhibit. In this case the address comparator compares 37 the target address with the filter address only for identity and then inverts the comparison result. The address extractor 36 routes the data packet that it receives from the other external port (e.g. the port 10 ) is supplied, i.e. only then to the sending machine 20 continue if this data packet is not or not exclusively for the connected terminal 1 is determined. In this case, a network switching condition is fulfilled.

To simplify the circuitry, it is possible to use the address comparator to check whether the network switching condition is fulfilled 30 of the internal block 15 to use and only the corresponding release bit to a buffer 38 to transmit the - just like the cache 33 - The data is buffered until the check for the network switching condition is completed.

As an alternative or in addition to the destination address, the address extractors can 29 of the internal block 15 or the address extractors 36 of the external blocks 16 . 17 also extract the source address and send it to the address comparator 30 . 37 to transfer. In this case, the address comparators check 30 . 37 the source address with the filter address (or one of the filter addresses). If the source address is different from the filter address, a source switching condition is fulfilled. Otherwise, the data packet is both from the address extractor 29 as well as from the address extractor 36 not forwarded. Circulars in the data packets can thus be filtered out.

With regard to the checking for the source switching condition, intermediate storage in the intermediate stores is of course also necessary 33 . 38 required to complete this exam.

As in the 3A and 3B is indicated by dashed crosses, can in a simplified version of the connection circuit 11 the address extractors 29 . 36 and the address comparator 30 . 37 omitted. In this case, data packets are assigned to the network interface 2 via one of the external ports 9 . 10 are always fed via the internal port 8th and the other external port 10 . 9 output.

As stated above, the ports are 8th to 10 Can be operated in full duplex mode. It is therefore possible to send and receive simultaneously on each port. If now one of the ports 8th to 10 - e.g. B. the internal port 8th - Simultaneously outputs data from a data packet and accepts data from another data packet, then data from a second port, e.g. B. the external port 9 supplied, namely the data that he himself z. B. on his sending machine 34 outputs. This data is - at least as a rule - also the third port or block, here the external port 10 or the external block 17 , fed. This port 10 or block 17 however, the data that the first named port (in the given example the internal port 8th ) receives. The block in question - here the block 17 - must have data from the other two blocks at the same time 15 . 16 accept. The block 17 can - logically - via the port 10 to which it is assigned only output the data of a single data packet. To avoid data loss in such a case, each of the blocks therefore points 15 to 17 at least one buffer 22 . 23 . 35 . 39 and 40 on. In these buffers 22 . 23 . 35 . 39 and 40 data packets that are not output immediately are buffered.

How out 3A the internal block shows 15 a single such buffer, namely the buffer 35 , In this buffer 35 As already mentioned, more than one data packet can be stored.

The external blocks 16 . 17 each have two such buffers, namely the buffers 22 and 39 for the external block 16 and secondly the buffers 23 and 40 for the external block 17 , The cache 22 . 23 serve, as already mentioned, for the temporary storage of a maximum of one data packet that the external blocks 16 . 17 via the internal port 8th is fed. The cache 39 and 40 on the other hand, serve for the temporary storage of data packets that are used for network connection 2 over the other external port 10 . 9 are fed. In this cache 39 . 40 is like in the 3B and 3C indicated, more than one data packet can be stored.

If necessary, the blocks 15 to 17 also have further buffers, not shown in the FIG. For example, the buffers 39 . 40 be divided into several FIFO memories connected in parallel. This could be a relatively simple way of prioritizing over the other external port 9 . 10 supplied data packets take place.

How the sending machine works 20 of the external block 16 will now be used in conjunction with 5 explained in more detail. The sending machine 21 of the other external block 17 works through an identical procedure.

According to 5 sends the sending machine 20 in a step 41 data of a data packet via the external port 9 to which it is assigned. It then checks in a step 42 whether the data packet has been sent completely. If not, it returns to step 41. Otherwise, it executes a step 43 in which a time register is set to the value zero.

After step 43, the sending machine checks 20 in a step 44 whether the value of the time register has reached a first minimum pause T1. If this is not the case, step 44 is repeated - at a somewhat later point in time, that is to say with a somewhat higher value in the time register.

If the value of the time register has exceeded the first minimum pause T1, a branch is made from step 44 to a step 45. There - by checking that of the occupancy officer 27 transmitted bits - checks whether high-priority data from the internal port 8th queue up to send. If this check is positive, the transmission of this data is started in a step 46 and a branch is made to step 41.

On the other hand, if it was decided in step 45 that no high-priority data from the internal port 8th pending to send, a branch is made to a step 47. In step 47 it is checked whether the Time register has exceeded a second minimum break T2. The second minimum break T2 is greater than the first minimum break T1.

If the second minimum break T2 is not exceeded is returned to step 44. If the second minimum break T2 is exceeded, it is checked in a step 48 whether data from the other external port 10 to be sent. If this is the If this is the case, the transmission of this data is started in a step 49 and then branched to step 41.

If, however, no data from the other external In a step 50, port 10 is pending to be sent, it is checked whether the Contents of the time register exceeded a third minimum break T3 Has. The third minimum break T3 is greater than the second minimum break T2.

If the third minimum break T3 has not been exceeded, a branch is made to step 44. Otherwise, it is checked in a step 51 whether - now low-priority - data from the internal port 8th queue up to send. If this is not the case, the process branches to step 44. If, however, data from the internal port 8th pending transmission, this data is started in a step 52 and a branch is made to step 41.

Priorities are therefore assigned to the data packets. The sending machines 20 . 21 perform the function of packet control elements, by means of which the highest priority data packet is always output first when from the respective external block 16 . 17 In principle, several data packets can be output. The data packets are those of the network interface 2 via the internal port 8th are alternatively assigned a high or a low priority. The data packets that the network connection 2 over the other external port 10 . 9 medium priority is assigned.

In addition, the external ports 9 . 10 data packets to be fed from the sending machines 20 . 21 delayed in such a way that there is a minimum pause, namely one of the minimum pauses T1 to T3, between the end of a data packet already output and the beginning of the next data packet. The minimum pause T1 to T3 is evidently dependent on the priority of the data packet to be sent. Furthermore, the priority and thus indirectly also the minimum pause T1 to T3 also depends on whether the data packet to be sent by the network interface 2 via the internal port 8th or the other external port 10 . 9 was fed. The minimum pause T1 to T3 is greater the lower the priority of the data packet to be sent.

It has already been mentioned above that the connection circuit 11 is not a processor-controlled circuit that executes a software program, but a hard-wired circuit. For security, however, it is again pointed out that the sending machines 20 . 21 the above in connection with 5 Do not implement the described sequence of steps by executing a software program, but rather by means of a circuit design for the transmitting machines 20 . 21 , The word “machine” is therefore to be understood in the present case in the sense of a Turing machine. The other elements of the connection circuit too 11 , for example the receiving machine 18 who have favourited Occupancy Investigators 27 . 28 who have favourited Address Extractors 29 . 36 and also the address comparators 30 . 37 do not always run a software program, but are designed in terms of circuitry in such a way that they implement the required functionality.

As already mentioned, the network connection points 2 an interface circuit 14 by means of which the connection circuit 11 is parameterizable. The parameterization of the connection circuit 11 includes in particular the specification of the filter addresses, which the address comparators 30 . 37 are fed, as well as the minimum breaks T1 to T3. If necessary, other parameters can also be set. For example, individual ports, in particular alternatively one of the two external ports 9 . 10 , can be switched off.

In the 6A to 6D is an extension of the network connection 2 the 3A to 3C shown. The main difference to the representation of the 3A to 3C is that the network connection 2 the 6A to 6D in addition to the blocks 15 to 17 a timer block 53 having. The timer block 53 serves to synchronize the to the network interface 2 connected end device 1 with other devices 1 ,

The internal block 15 is in 6A shown. It is opposite 3A remained unchanged. Regarding the internal block 15 no further explanations are therefore necessary.

The external blocks 16 . 17 however, have additional elements. So the external blocks point 16 . 17 especially packet selectors at the receiving end 54 . 55 on. Using these packet selectors 54 . 55 it is checked whether the respective external port 9 . 10 supplied data packet is a time data packet. If the data packet is not a time data packet, it is sent to normal data outputs 56 . 57 of the external blocks 16 . 17 connected through. Conversely, if it is a time data packet, it will be on time outputs 58 . 59 of the external blocks 16 . 17 connected through.

A received time data packet is sent via the corresponding time output 58 respectively. 59 the corresponding time entrance 60 respectively. 61 of the timer block 53 fed. From the respective time entrance 60 respectively. 61 it becomes a timestamp generator 62 fed. This can determine the time using the supplied time data packet. The timestamp generator is used to determine the time correctly 62 via the interface circuit 14 a correction value is supplied. The correction value can therefore be parameterized. It is used to take the time (reception time delay T4) into account stamp generator 62 needed to calculate the initial value from the transmitted time and into a time counter 63 einzuspeichern.

Feeding a time data packet to the timer block 53 takes place in the same way as the feeding of a data packet to the internal port B. The data of the time data packets are thus also sent to the external ports before these data packets are completely fed 9 . 10 to the timer block 53 forwarded.

Just like the internal block 15 and the external blocks 16 . 17 is also the timer block 53 Part of the connection circuit 11 , It is thus also designed as a hardware circuit, integrated in an Ethernet interface, possibly integrated in an ASIC or possibly also part of the FPGA or EPLD. So no software program is processed. The time it takes to determine the correct time from the time data packet and to the time counter 63 Forwarding can therefore be determined in advance. This ensures a highly accurate correction in the time stamp generator 62 possible. Due to the highly accurate correction, it is also possible that the time counter 63 each time a reference value is reached - e.g. B. once per second - a highly accurate time signal PPS via the interface circuit 14 to the end device 1 outputs.

The procedure described above is carried out when the connected terminal 1 is operated as a dependent terminal (slave) to which the time reference is transmitted via the transmission medium 3 is specified. For this purpose, a mode register of the interface circuit 14 loaded accordingly. The content of this register determines, for example, whether the connected terminal 1 is dependent or independent. It can also be specified via which of the external ports 9 . 10 if appropriate, a time data packet is received and via which a time data packet is sent.

Via a time address register can also - e.g. B. by default to the packet selectors 54 . 55 - Which data packets are recognized and treated as time data packets are specified.

If the timer block 53 The timestamp generator is used as the master 62 at previously known times, e.g. B. every second, the highly accurate time signal PPS via the interface circuit 14 fed. When this time signal PPS arrives, the time counter becomes 63 each loaded with a predetermined initial value and restarted. The time counter 63 thereupon transmits a request signal to a time transmission control 64 , This asks at one of the sending machines 20 . 21 , possibly also with both sending machines 20 . 21 , whether they can send a time telegram immediately and without delay. He waits for corresponding confirmations from the sending machines 20 . 21 from.

The sending machines 20 . 21 monitor whether they are otherwise sending a data packet. So you monitor whether the transmission medium 3 , that is, the lines 3 , are occupied. They only send their confirmations when the lines 3 are free.

Such an approach is commonly known as handshake and therefore will not be discussed below described in more detail.

If the sending machines 20 . 21 time transmission control 64 have indicated their readiness to send, this transmits a time data packet generator 65 a start signal. This then reads from the time counter 63 the current meter reading. He inserts the meter reading into a time data packet and sends it via a time output 66 at time entrances 67 and or 68 of the external blocks 16 . 17 and from there to the sending machines 20 respectively. 21 , If necessary, the counter reading can be corrected by a correction value before insertion into the time data packet. The correction can be done in a correction circuit - just like when receiving a time reference. In particular, a transmission time delay T5 can thus be compensated for.

The sending machines 20 . 21 then output the time data packet supplied to them. If the time packet over both external ports 9 . 10 the time counter is read out 63 only with the transmission of confirmations from both sending machines 20 . 21 , The output of the time data packet to the sending machines 20 respectively. 21 done as from 6 can be seen directly. Between the timer block 53 and the external ports 9 . 10 so no buffers are arranged.

Sending the time data packets via the external ports 9 . 10 is carried out in the same way as sending a data packet, which is the external ports 9 . 10 via the internal port 8th is fed. Data of a time data packet are thus also already supplied via the external ports before the time data packet has been completely supplied 9 . 10 output.

Since also the time data packet generator 65 is designed as a hardware circuit, the time delay T5 caused thereby can be determined in advance and / or is known. It can therefore be taken into account when determining the correct time. The necessary correction factor for taking into account the delay time T5, i.e. the initial transmission value, can again be made via the interface circuit 14 be parameterizable. In particular, it determines the initial value, which in the case of transmission is in the time counter 63 is loaded, or the correction value by which the from the time counter 63 read value is corrected.

The structure and operation of the timer block 53 are subsequently used in conjunction with the 6 . 7 and 8th described again in more detail. The transmission case, that is the output of a time data packet, is described first, then the reception case, that is to say the reception of a time data packet.

In the master case, the timer block 53 from time to time, e.g. B. every second, the time signal PPS supplied. This time signal PPS is within of the timer block 53 the timestamp generator 62 fed. The time signal PPS thus serves as a synchronization pulse for the timer block 53 ,

When the synchronization pulse PPS is supplied, the time stamp generator saves 62 in the time counter 63 an initial transmission value. Then the time counter 63 clocked incremented. The time counter 63 is therefore a counting register. The initial transmission value corresponds to the transmission delay time T5.

As already stated, the time transmission control transmits 64 to the sending machines 20 . 21 a request as to whether they can send a time telegram immediately and without delay. This corresponds to a request signal sent to the sending machines 20 . 21 is transmitted. The sending machines 20 . 21 wait for this request signal. After receiving it, check whether it is currently on the transmission medium itself 3 (the network lines 3 ) send a data packet. If not, the transmission medium is 3 not used. In this case, they transmit their readiness for transmission in the form of a corresponding release signal to the time transmission control 64 ,

As well as the time transmission control 64 has received the release signals, it transmits the start signal to the time data packet generator 65 , This then reads the current counter reading from the time counter 63 out. This counter reading (= value) corresponds - if necessary after a corresponding correction - to the time reference to be transmitted. This time reference are generated by the time data packet generator 65 but added additional information. In particular, a complete time data package is created. So the time reference will be - see 4 - Added a source and a destination address as well as priority and / or type information. This additional information can make up the timer block 53 or the time data packet generator 65 in advance via the interface circuit 14 be specified.

The time data packet generator also determines 65 test information (CRC = cyclic redundancy check) for the time data packet, in particular also for the time reference.

The time data packet determined in this way is then sent to the sending machines without further delay 20 . 21 transmitted and by these as a time reference via the transmission medium 3 Posted.

How out 6 can be seen is the timer block 53 directly with the sending machines 20 . 21 connected via which the time reference into the transmission medium 3 is feedable. There is no further temporary storage. In combination with the fact that the entire in 6 Connection circuit shown 11 is a hard-wired circuit, therefore lies between the reading of the time counter 63 and sending the time reference over the transmission medium 3 or the lines 3 a predetermined transmission time delay T5.

The initial transmission value or the correction value taken into account during transmission corresponds to the transmission time delay T5. It is thus determined in such a way that it compensates for the transmission time delay T5. In particular, the initial transmission value results as f × T5, where f is the clock frequency (eg 25 MHz) with which the time counter 63 is incremented. This initial value can be the timer block - be it directly as a numerical value or indirectly by specifying the transmission time delay T5 53 be specified.

As a rule, synchronization takes place between the end devices 1 with the first bit of the new time data packet. The transmission time delay T5 is therefore generally due to the reading of the time counter 63 and the start of outputting the time reference or the time data packet.

The procedure is completely analogous if one of the external blocks 16 . 17 via the transmission medium 3 a time data packet is received. In this case, first in the packet selectors 54 . 55 checks whether the source address contained in the time data packet matches a target source address. It is also checked whether the destination address contained in the data packet matches a target destination address. The addresses are the packet selectors 54 . 55 again via the interface circuit 14 specified. As already mentioned, the time data packet is only sent to the timer block in the event of a match 53 forwarded. Otherwise, the further steps described below are omitted.

In the event of a match, the time data packet from the receiving external block 16, 17 becomes the time stamp generator 62 fed. First, the checker uses the check information to check whether the time reference has been correctly transmitted. The time reference is only processed if this is the case. Otherwise it will be discarded.

In the case of a properly received time data packet, the time stamp generator extracts 62 the time reference and corrects it - see 7 In a correction circuit 69 by a correction value. The corrected time reference is then entered into the time counter as the start reception value 63 stored. As soon as the reception start value is saved, the time counter becomes 63 then incremented clocked. If the value of the time counter 63 reaches a reference value, e.g. B. corresponds to the next full second, a synchronization pulse to the connected terminal is in the form of the time signal PPS 1 output.

The timer block is also as far as the reception path is concerned 53 directly with the receiving circuits 16 . 17 connected via which the time reference via the transmission medium 3 is receivable. There is therefore no temporary storage. In connection with the design of the entire connection circuit 11 as a hardware circuit is thus the processing time between the receivers predetermined according to the time reference and the storage of the reception start value. This time is called the reception time delay T4 below. The correction value by which the received time reference is corrected can therefore be determined in such a way that it compensates for the reception time delay T4. It can - analog to the initial transmission value - directly as a numerical value or indirectly through the reception time delay T4 the timer block 53 or the timestamp generator 62 via the interface circuit 14 be specified.

As a rule, as already mentioned, synchronization takes place with the first bit received. The reception time delay T4 is therefore due to the start of reception of the time reference or of the time data packet and the storage of the reception start value in the time counter 63 certainly.

As already mentioned in connection with 6D executed, it can be determined by a corresponding specification of the operating mode whether the timer block 53 is operated as a master or as a slave. But it is also possible to use the timer block 53 to parameterize in such a way that he chooses his role dynamically. This is discussed below in conjunction with 8th explained in more detail.

According to 8th can from time transmission control 64 are first checked in a step 70 whether the timestamp generator 62 via the transmission medium 3 a time reference was supplied and the supplied time reference was correct. This can be achieved, for example, in that, as in 6D indicated an OK bit to the time transmission control 64 is transmitted.

If the time transmission control 64 this bit is transmitted, in step 71 it sets a timer to the value zero and starts it. In a step 72, it also sets a master bit M to the value zero. The master bit M becomes the time stamp generator 62 supplied, which in this case behaves as a slave. Further processing then takes place on the basis of the time reference received, as has already been described.

If the time transmission control 64 however, if no OK bit is transmitted, it checks in a step 73 whether the timer has reached a limit value. If this is the case, it sets the master bit M to the value one in a step 74 and sends it to the time stamp generator 62 out. This then switches to master mode. It therefore takes over the interface circuit as long as the master bit M with a value of one is transmitted to it 14 the time signal PPS counter and writes the transmission start value in the time counter 63 on. The time transmission control 64 then determines according to the manner described above whether a time data packet can be sent and, if necessary, initiates the sending of this packet.

According to 8th the timer is started every time the start receive value is saved. Until the timer reaches the limit, the timer block becomes 53 operated as a slave. It therefore generates the time signal PPS (or the synchronization pulse PPS) on the basis of the transmitted time reference. When the timer reaches and exceeds the limit, the timer block 53 however, operated as a master. It therefore transmits itself via one or both of the sending machines 20 . 21 a time reference. As soon as a time data packet is received properly again, i.e. an initial reception value in the time counter 63 the timer block is configured 53 but switched back to slave operation.

A mixed form of master and slave operation is also possible. In this case the timer block functions 53 eg regarding the external port 9 As a slave, it receives a time reference from there and determines it - if necessary with correction in the correction circuit 69 - the one in the register 63 initial value to be written. Regarding the other external port 10 acts the timer block 53 as a master. The only difference to the "normal" master operation is that the timer block 53 the synchronization pulse PPS is not specified from the outside.

The correction of the transmission and reception time delay T5, T4 can continue in the correction circuit 69 and the corresponding transmission-side correction circuit. But it can also be completely in one or the other correction circuit 69 respectively.

By means of the network connection according to the invention 2 is thus a line topology of several end devices in a simple and inexpensive manner 1 built up. With this topology, the real-time capability is retained. By adding the timer block 53 can even synchronize multiple end devices in a simple and highly precise manner 1 be effected.

Claims (26)

Network connection, especially Ethernet connection, with exactly three ports ( 8th to 10 ), - where the ports ( 8th to 10 ) via a hard-wired connection circuit ( 11 ) are interconnected, - one ( 8th ) the ports ( 8th to 10 ) an internal port ( 8th ) via which a device ( 1 ) can be connected to the network interface, - whereby the other two ports ( 9 . 10 ) external ports ( 9 . 10 ) via which a network cable ( 3 ) can be connected to the network interface, - the ports ( 8th to 10 ) can be operated in full duplex mode and - the connection circuit ( 11 ) is designed such that data of a data packet that is sent to the network interface via one of the ports (e.g. 8th ) is supplied via at least one (e.g. 9 ) the other ports (e.g. 9 . 10 ) can be output. Network interface according to claim 1, characterized in that the connection circuit ( 11 ) is designed such that one of the network connections via the internal port ( 8th ) supplied data packet always via both external ports ( 9 . 10 ) is output. Network interface according to claim 1 or 2, characterized in that the data packets contain destination addresses and that the connection circuit ( 11 ) is designed such that in one of the network connections via one of the external ports ( 9 . 10 ) data packet is first extracted the destination address and this data packet only then via the internal port ( 8th ) is output if the target address fulfills a terminal switching condition. Network interface according to claim 1, 2 or 3, characterized in that the data packets contain destination addresses and that the connection circuit ( 11 ) is designed such that one of the network connections via one of the external ports ( 9 . 10 ) data packet is first extracted the destination address and that this data packet only then via the other external port ( 10 . 9 ) is output if the target address fulfills a network switching condition. Network interface according to one of the above claims, characterized in that the data packets contain source addresses and that the connection circuit ( 11 ) is designed such that in one of the network connections via one of the external ports ( 9 . 10 ) data packet is first extracted the source address and this data packet only then via the internal port ( 8th ) and the other external port ( 10 . 9 ) is output if the source address fulfills a source switching condition. Network interface according to claim 3, 4 or 5, characterized in that the connection circuit ( 11 ) at least one buffer ( 33 . 38 ), in which data of a data packet supplied to the network interface are temporarily stored until the check as to whether the terminal switching condition, the network switching condition and / or the source switching condition is or are fulfilled. Network connection according to claim 1 or 2, characterized in that the connection circuit ( 11 ) is designed such that one of the network connections via one of the external ports ( 9 . 10 ) supplied data packet always via the internal port ( 8th ) and the other external port ( 10 . 9 ) is output. Network interface according to one of the above claims, characterized in that the connection circuit ( 11 ) is designed such that data from one of the network interfaces via one of the ports ( 8th to 10 ) supplied data packets in a buffer ( 22 . 23 . 35 . 39 . 40 ) are stored until the data have reached a minimum size and / or the data packet is completely in the buffer ( 22 . 23 . 35 . 39 . 40 ) is stored, and only then when the data packet is output via at least one of the other ports ( 8th to 10 ) is started. Network interface according to one of the above claims, characterized in that the external ports ( 9 . 10 ) are designed as media-independent interfaces (MII) and that the network lines ( 3 ) via physical layer devices ( 7 ) to the external ports ( 9 . 10 ) can be switched on. Network interface according to one of the above claims, characterized in that the internal port ( 8th ) is designed as a medium-independent interface (MII) and that the end device ( 1 ) directly to the internal port ( 8th ) can be switched on. Network interface according to one of the above claims, characterized in that the connection circuit ( 11 ) is designed such that one of the ports ( 8th to 10 ) via one of the other ports ( 8th to 10 ) supplied data packet from the one port ( 8th to 10 ) is cached if it is from the third port ( 8th to 10 ) a data packet is already being fed. Network interface according to claim 11, characterized in that the external ports ( 9 . 10 ) Cache ( 22 . 23 ) for the temporary storage of data packets assigned to the network connection via the internal port ( 8th ) who the, and that in the buffer ( 22 . 23 ) a maximum of one data packet can be stored at any time. Network interface according to claim 11 or 12, characterized in that the external ports ( 9 . 10 ) Cache ( 39 . 40 ) for the temporary storage of data assigned to the network connection via the other external port ( 10 . 9 ) and that in the buffer ( 39 . 40 ) more than one data packet can be stored. Network interface according to claim 11, 12 or 13, characterized in that the internal port ( 8th ) at least one buffer ( 35 ) for the temporary storage of data packets assigned to the network connection via one of the ex remote ports ( 9 . 10 ) are fed, and that in the buffer ( 35 ) more than one data packet can be stored. Network interface according to one of the above claims, characterized in that priorities are assigned to the data packets and that the external ports ( 9 . 10 ) Package controls ( 20 . 21 ) are assigned, by means of which several of the external ports ( 9 . 10 ) the highest priority data packet is always output first. Network interface according to claim 15, characterized in that the network interface via the internal port ( 8th ) data packets supplied alternatively a high or a low priority and that of the network connection via the external ports ( 9 . 10 ) supplied data packets are assigned a medium priority. Network connection according to claim 15 or 16, characterized in that by means of the packet control elements ( 20 . 21 ) the external ports ( 9 . 10 ) supplied data packets can be delayed in such a way that between the end of one of the external ports ( 9 . 10 ) output data packet and the beginning of the next one via this external port ( 9 . 10 ) output data packet a minimum pause (T1 to T3). Network interface according to claim 17, characterized in that the minimum pause (T1 to T3) depends on the priority of the data packet to be sent and / or depends on whether the data packet to be sent to the network interface via the internal port ( 8th ) or via the other external port ( 10 . 9 ) is supplied. Network connection according to claim 18, characterized in that that the minimum break (T1 to T3) is greater, the lower the priority of the sending data packet. Network interface according to one of the above claims, characterized in that it is an interface circuit ( 14 ) via which the connection circuit ( 11 ) can be parameterized. Network connection according to one of claims 1 to 20, characterized in that they are electronically programmable Circuit, e.g. B. as a field programmable gate array (FPGA) or as electronically programmable logic device (EPLD). Network connection according to one of claims 1 to 20, characterized in that it is designed as an ASIC. Network interface according to one of the above claims, characterized in that it is connected by the terminal ( 1 ) can be supplied with electrical energy. Network connection according to one of the above claims, characterized in that it is independent of the terminal ( 1 ), especially via one of the network lines ( 3 ), can be supplied with electrical energy. Network interface according to one of the above claims, characterized in that - it comprises a timer block ( 53 ), by means of which this is sent to the internal port ( 8th ) connected end device ( 1 ) via the network line ( 3 ) with at least one other device ( 1 ) can be synchronized - that at least part of the network connection via the external ports ( 9 . 10 ) data packets supplied to the timer block ( 53 ) can be supplied and evaluated by the latter for synchronization, the supply of data from these data packets to the timer block ( 53 ) before these data packets are completely fed to the external ports ( 9 . 10 ), and / or - that from the timer block ( 53 ) via at least one of the external ports ( 9 . 10 ) Data packets can be output for the synchronization, with the output of data of these data packets also via the external ports ( 9 . 10 ) before these data packets are completely fed to the external ports ( 9 . 10 ) he follows. Network connection according to claim 25, characterized in that between the timer block ( 53 ) and the external ports ( 9 . 10 ) no buffers are arranged.