JP2002522949A - Circuit device and method for receiving and transmitting data - Google Patents

Abstract

(57) [Summary] By using this circuit device and a method belonging thereto, by temporarily storing all the time slits in the state parameter assigned to the transmission frame, it is possible to adjust to an actual time slit.

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a circuit device and a method for receiving and transmitting data.

In a communication system, for example, a switch, a high-level data link controller
Used for data transmission at network relay points. The HDLC controller is disposed at a network relay point, for example, between a synchronous data transmission network and an asynchronous data transmission network. In the selection of the data transmission rate or the time slit width, the time slit width set by the transmission rate of the network transmission unit during frame-oriented data transmission has been adjusted using a marking field in the related art. However, this has the disadvantage that the data transmission can only be performed in the time slits marked for it.

It is therefore an object of the present invention to provide a circuit device and a method which overcome the above-mentioned disadvantages.

According to the invention, this problem is solved by the requirements of claims 1, 2 and 6,7.

An advantage achieved by the present invention is that all time slits of a transmission frame for data transmission can be used.

An advantage achieved by the present invention is that the number of channels for an HDLC controller can be changed by changing the configuration parameters.

[0007] Particularly advantageous embodiments of the invention result from the dependent claims.

Hereinafter, a circuit device and a method according to the present invention will be described in detail with reference to the illustrated embodiments.

At this time, FIG. 1 is a schematic diagram of a transmission section, FIG. 2 is a schematic diagram of a transmission frame, FIG. 3 is a schematic diagram of a HDLC controller, FIG. FIG. 6 is a diagram showing the HDLC receiving unit in more detail, and FIG. 7 is a diagram showing the HDLC transmitting unit in more detail.

FIG. 1 shows a network configuration of a data transmission section. This network configuration includes a data network AD for asynchronous data transmission and at least one data network SD for synchronous data transmission. The data network AD for asynchronous data transmission is, for example, an ATM network, an integer (Int)
eger) network, Datex-P-network or Ether network. For synchronous data transmission in the data network SD, for example, a PCM system or a synchronous transfer mode STM can be used. Interfaces between the data network AD operating synchronously and the data network SD operating asynchronously are each provided with a high-level data link controller HDLC. A number of data terminals TL can be connected to the network termination point NT of the data network SD operating synchronously. One data terminal TL is assigned one or more time slits or time channels between the data networks AD, SD for data transmission between the network termination point NT and the interface.

FIG. 2 shows a transmission frame of a PCM transmission system used in a data network SD for performing synchronous data transmission, for example. The PCM transmission frame is, for example, 16 bits long and can be divided into slits or channels for a maximum of 16 hours. The minimum possible time slit may include one bit, and the maximum time slit may include 16 bits. The bits of the transmission frame are numbered from 0 to 15. The first time slit TS of the 3-bit time slit width TSB has the time slit TS to channels 0, 1 and 2 integrated into one data transmission channel. Each time slit TS is numbered at the beginning of the time slit TS for the first channel. The first bit number is assigned to the first time slit TS. In the subsequent second time slit TS (including channels 3, 4, 5 and 6), the second time slit TS is the time slit number TS corresponding to the number of the first bit of the second time slit TS. have. TS7 and TS8 are shown in the third and fourth time slits.

FIG. 3 shows a configuration of the high-level data link controller HDLC. This HDLC controller substantially has an HDLC receiving unit HDLC-E, an HDLC transmitting unit HDLC-S, an HDLC processor HDLC-P, and a frame buffer FB. HD
The LC receiving unit HDLC-E and the HDLC transmitting unit HDLC-S are each connected to a line of the synchronous operation data network SD. The frame buffer FB is connected to the asynchronous controller AC of the synchronous operation data network AD.

The illustrated HDLC controller is substantially divided into three processing units.
Each of the processing units is specifically configured to reduce the speed requirements of the immediately next stage.

In the first processing unit WSPE, WPSS, the data is converted to serial-parallel or parallel-serial, the actual time slit is processed based on the state parameters, and the actual time slit follows the actual time slit. The state parameter for charging is charged. The state parameters include, for example, time slit length, state, number of bits, shift register contents,
And so on. At the end of the actual time slit, the actual time slit state parameters are temporarily stored in the first memory content, and the temporarily stored arrival time slit state parameters are supplied to the HDLC processor HDLC-P. During the processing of the time slit, a complete data word is output or read from the data port.

The HDLC processor HDLC-P allows the receiving and transmitting sides to be split into two halves. At that time, each half is divided into the second processing units BV, BVS and the third processing units FV, FV.
Has VS.

In the second processing unit BV, BVS, the byte processing unit, the state parameters in the second memory contents ST, STS belonging to the time slit are monitored by the time slit, and the first memory content is monitored. Data words from or within one part of SE and SS are read from the data hold DH and DHS registers and are stored again (FIGS. 6 and 7).
reference). Furthermore, state parameters are allocated in the first memory units SE, SS.
Data is transferred to or received from a third processing unit FV, FVS via a separate data path.

In a third processing unit FV, FVS of the frame processing unit (see FIGS. 6 and 7), the data words belonging to the data frame are combined. In the third processing units FV, FVS additionally address detection, block security and further protocol functions are performed.

FIG. 4 shows a block connection diagram of the HDLC receiving unit HDLC-E. The main units are a serial-parallel converter S / P, an HDLC processor HDLC-P and, alternatively, a data hold register DH and a state parameter register SP assigned to the first processing unit WSPE or HDLC-P. It is. Data transmitted on the serial data bus DB of the synchronous data network SD is serially connected to the serial-parallel converter S / P (
Shift register). When the pre-adjustable time slit width is reached, the data of the receiving unit HDLC-E and the contents of the serial-parallel converter S / P are stored again in the register SP provided for the state parameter (see FIG. 6). )
. If the data is complete in the time slit, this data is transmitted into the data hold register DH. At the same time, the data of the subsequent time slit is stored in the register SP, and the receiving unit HDLC-E is pre-adjusted with the temporarily stored data for the subsequent time slit of the previous PCM frame.

FIG. 5 shows a block connection diagram of the HDLC transmission unit HDLC-S. this
Using the HDLC transmission unit HDLC-S, the data to be transmitted is converted to a parallel-serial converter P /
It is inserted into the data bus DB via S. A new data word from the data hold register DHS is always stored in the parallel-to-serial converter P / S after the data word has been output to the data bus DB. At the start of a new time slit, all data and HD temporarily stored in data hold register DHS and state parameter register SPS
The state of the LC processor HDLC-P is exchanged by the HDLC processor HDLC-P.

FIG. 6 shows the HDLC receiving unit HDLC-E in detail. At this time, the main elements of the HDLC receiving unit HDLC-E are a serial-parallel converter S / P, a register data hold DH, a state parameter register SP, a byte processing unit BV, a frame processing unit FV, and a frame buffer FB.

Each data temporarily stored in the state parameter register SP for each time slit is stored in the state table ST of the byte processing unit BV according to the actual time slit. In the byte processing unit BV, the state table ST is generated such that the data of the arrival time slit is read into the state parameter register SP each time the time slit is switched. The data called from the data hold register DH is classified into an event queue unit EQ, a coupling unit between the byte processing unit BV and the frame processing unit FV, and further processed.

Data is read from the data bus DB using the serial-parallel converter S / P of the first processing unit (WSPE). Data is stored in the data hold register DH. At the end of the length of the time slit, which is pre-adjustable via a counter, all data and associated states are exchanged between the serial-parallel converter S / P and the state parameter register SP. In the state parameter register SP, the time slit width, the register content and its state, and other parameters are temporarily stored. In the state table ST, the state parameters read into the state parameter register SP are temporarily stored. The size of the state table ST is determined by the synchronous operation data network SD.
Corresponds to the maximum number of possible time slits in the transmission section within. The start of the time slit following the actual time slit is calculated from the state data of the actual time slit. The event queue section EQ provided between the byte processing unit BV and the frame processing unit FV is generated so that the priority can be determined according to the time slit or the transmission rate of the channel. In particular, data of all HDLC channels is stored in a frame buffer FB provided behind the frame processing unit FV.

FIG. 7 shows an HDLC transmission unit HDLC-S. Data to be transmitted in a time slit or a channel is read from the frame buffer FB according to the direction of the arrow shown in the schematic diagram.

When data is read from the frame buffer FB to the frame processing unit FVS and the data is allocated in a predetermined time slit of the PCM frame, the data word is allocated the corresponding time slit number TS number. Is supplied to the data hold register DHS via the data table DTS and is temporarily stored therein. The data words to be inserted in the time slits of the PCM frame are temporarily stored, and at the same time, from the status table of the second memory content STS allocated in the byte processing unit BVS, HD
Initialization data STS necessary for LC processor HDLC-P is secondarily allocated by allocation unit ZU.
Is stored in the memory unit STS. The data word temporarily stored in the data hold register DHS is inserted in a predetermined manner into a time slit provided for it based on the initialization of the high-level data link control processor HDLC-P.

At the end of the time slit, the components of the data word, which have not yet been processed, are stored in the second memory unit STS from the state parameter register SPS together with the instantaneous state values of the high data link control processor HDLC-P. Will be fixed. During the re-storing, at the same time as the subsequent time slit Tsn + x of the PCM frame, the state parameters are provided in the state parameter register SPS and the data words are provided in the data hold register DHS. In accordance with the preliminary adjustment of the high-level data link control processor HDLC-P, the data temporarily stored in the data hold register DHS is inserted into the time slit of the PCm frame. When a new time slit is switched, the state parameters and data of the high-level data link control processor HDLC-P are inserted into the data hold register DHS, and the state parameters are stored in the state parameter register SPS, and the state table STS Is temporarily stored. The new data needed for the incoming time slit and the adjustment of the high-level data link control processor HDLC-P are specified by the allocation unit ZU.

In the frame processing unit FVS, data for the data table DTS is transferred using the event queue EQS. In the data table DTS, data of all possible time slits is temporarily stored in a transmission frame for the data hold register DHS. By doing so, the frame can be processed other than the time slit. Using the event queue EQS, data processing can be performed according to each transmission rate. In the byte processing unit BVS, the time slit number TS number of the last actual and subsequent time slit is calculated from the position of the time slit and the time slit length in the transmission frame. The state table STS stores the state parameters SPS of all the time slits to be processed. The size of the state table STS always corresponds to the maximum possible number of time slits. The state parameters recorded in the state parameter register SPS include the following information: the time slit width, the number of bits in a data word, and the contents of the shift register and other state information.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a transmission section

FIG. 2 Configuration of transmission frame

FIG. 3 is a schematic diagram of a configuration of an HDLC controller.

FIG. 4 is a block connection diagram of an HDLC receiving unit.

FIG. 5 is a block connection diagram of an HDLC transmission unit.

FIG. 6 shows the HDLC receiving unit in more detail.

FIG. 7 shows the HDLC transmission unit in more detail.

[Procedural Amendment] Submission of translation of Article 34 Amendment of the Patent Cooperation Treaty

[Submission date] August 22, 2000 (2000.8.22)

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[0003] US Pat. No. 5,619,500 discloses an HDLC controller framed by a fixed number of channels. This HDLC controller, however, has the disadvantage that the number of channels as well as their channel width are not variable within this frame. It is therefore an object of the present invention to provide a circuit arrangement and a method which overcome the above-mentioned disadvantages.

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FIG. 7

──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5K028 AA11 CC05 DD03 KK35 LL01 RR01 SS24 TT01 5K030 GA19 JL10 KA02 LA09 5K033 AA01 CA11 CB01 CB08 CB14 DA05 DB12 DB18 5K034 DD03 EE11 HH24 HH42 KK24 MM08

Claims (7)

[Claims] 1. A circuit device for receiving data in which at least one time slit (TS1, TSn, TSn + x,...) Is allocated in a transmission frame, comprising: a first processing unit (WSPE); , A second processing unit (BV) and a third processing unit (FV), wherein the first processing unit (WSPE) reads data from an actual time slit (TSn), And preparing the actual state parameters of the actual time slit (TSn), temporarily storing the state parameters of the time slit (TSn + x) subsequent to the actual time slit (TSn), Temporarily storing the read data of (TSn) in a first memory unit (SE), the second processing unit (BV) having an allocation unit (ZU), Of the second memory unit (ST). In the knit (ST), the first
The state parameters read from the memory unit (SE) during the time slit switching are stored, the state parameters to be temporarily stored in the first memory unit (SE) are prepared and the second processing unit is prepared. (BV) is the data of the actual time slit (TSn) temporarily stored in the first memory unit (SE).
The third processing unit (FV) stores the data words in the third memory unit (EQ).
A circuit device formed from data stored in an EQ). 2. A circuit for transmitting data in which at least one time slit (TS1, TSn, TSn + x,...) Is allocated in a transmission frame, comprising: a first processing unit (WPSS); , A second processing unit (BVS) and a third processing unit (FVS), wherein the first processing unit (WPSS) comprises a unit (P / S) and a first memory. Unit (SS), and the unit (P / S) has an actual time slit (TSn).
) Is read into the transmission frame and the actual state parameters for the actual time slit are prepared and adjusted, and the first memory unit (SS) stores the time slit (TSn) following the actual time slit (TSn). TSn + x), the second processing unit (BVS) has an allocation unit (ZU),
Of the first memory unit (STS) is stored in the second memory unit (STS), and the state parameter read from the first memory unit (SS) when the time slit is switched is stored in the second memory unit (STS). A state parameter to be temporarily stored in a memory unit (SS) is prepared and the second processing unit (BVS) converts the data temporarily stored in the third memory unit (DTS) to a first data. Memory unit (SS)
The third processing unit (FVS) allocates data belonging to the time slit (TSn, TSn + z) and stores the data in the third memory unit (DTS). A circuit device characterized by the above-mentioned. 3. The circuit device according to claim 1, wherein the first memory unit (SE, SS) includes first and second registers (SP, DH; SPS, DHS). 4. A shift register (S) in a first processing unit (WSPE, WPSS).
/ P, P / S), wherein the shift register (S / P, P / S) receives data from a transmission frame (TSn) and transmits data in the transmission frame. Or the circuit device according to 2. 5. The circuit device according to claim 1, wherein the circuit device is integrated in an HDLC controller (HDLC) for receiving and transmitting data. 6. A method for receiving data in which at least one time slit (TS1, TSn, TSn + x,...) Is allocated in a transmission frame, comprising: Is read out and temporarily stored, and an actual state parameter of the actual time slit is prepared, and the state parameter of the time slit (TSn + 1) subsequent to the actual time slit (TSn) is stored in the first memory. Temporarily storing in the unit (SE), storing and monitoring in the second memory unit (ST) the state parameters read out from the first memory unit (SE) when the time slit is switched, Preparing the state parameters to be temporarily stored in the first memory unit (SE), and storing the data temporarily stored in said first memory unit (SE) for the actual time slit (TSn); Third Read in memory units (EQ), - the third from the memory unit (EQ) stored in the data receiving method of the data and forming a data word. 7. A method for transmitting data in which at least one time slit (TS1, TSn, TSn + x,...) Is allocated in a transmission frame, comprising: preparing state parameters of an actual time slit. Forming, reading the data into the actual time slit (TSn), and temporarily storing the state parameter of the subsequent time slit (TSn + z) in the first memory unit (SS) after the actual time slit (TSn). Storing, in a second memory unit (STS), a state parameter read out from the first memory unit (SS) when a time slit is switched, in a second memory unit (STS); Preparing state parameters to be temporarily stored in the first memory unit (SS), and storing the data temporarily stored in the third memory unit (DTS) in the first memory unit (SS). Assignment,-before A method for transmitting data, characterized by allocating data belonging to said time slit (TSn, TSn + x) and storing said data in said third memory unit (DTS).