JP2001285339A - Data processing system for receiver of packet switch device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a development cost by realizing a sharing of circuit even at fluctuation of a number of capacity HW. SOLUTION: In this system, a physical layer processor 1-1-1-n retrieves a packet by processing a SDH termination as a physical layer process of OSI referring model for input data of respective HW. The retrieved packet is read at each packet unit and multiplexed on a time axis by a packet multiplex processor 3 after storage into a buffer memory 2 for packet multiplex at each HW, then inputted to a common part 11 consisting of a data link layer processor 4, a page divider 5, INF part 6 of data link layer processing and VOQ processor 8. Therefore the common part 11 can process practically at the packet unit, the system can process without any change of circuit configuration even a change of the number of capacity HW.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a packet switch, and more particularly, to a page switch for transmitting packet data from a plurality of input lines.
The present invention relates to a data processing method of a receiving unit of a packet switching device that performs time division multiplexing by dividing into two.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a data processing system of a conventional packet switch device receiving section. In the data processing method of the packet switch device receiving unit, packets are extracted by the physical layer processing units 36-1 to 36-n from input data of the transmission path accommodation HWs (highways) 1 to HWn.

[0003] The physical layer processing here is SDH (Synchro
nous Digital Hierarchy)
The overhead part of the SDH frame shown in FIG. 7 is terminated, and the HDLC-Fl
ame packet is extracted.

[0004] Data link layer processing units 37-1 to 37-37
-N, HDLC termination (High-level data link Con
trolProcedure, a kind of data link layer TCP / IP protocol, which performs high-level data link control procedures, and PPP termination (Point to Point Protocol, a kind of data link layer TCP / IP protocol, which connects to the Internet via a modem. (A protocol used in such a case) is performed in parallel for each HW to extract a network layer packet.

In the page division units 38-1 to 38-n,
Page division processing for switching for each HW (p
(Age is a processing unit when switching is performed by the subsequent switch unit 45), and then, in the page multiplexing unit 39, all the packet data divided into pages are time-division multiplexed, and the subsequent network layer processing unit 40
And the interface conditions of the portion where the HW multiplex interface is required, such as the VOQ processing unit 42.

Further, in VOQ processing for switching (virtual output queuing, a switching method in which packet data is buffered and scheduling is performed when output HWs overlap in switching), it is necessary to simultaneously manage packets of a plurality of HWs. For this reason, it has a packet link management unit 44, and performs packet link management of each HW.

[0007]

In the conventional data processing method of the packet switch device receiving section shown in FIG. 6, the processing of each HW is performed at the packet stage, and the network layer packet extracted from each HW is divided into pages. After division into pages in the units 38-1 to 38-n,
Since the page multiplexing unit 39 time-division multiplexes the page data from each HW, each subsequent processing block cannot be processed as continuous packet data, and is processed for each HW. Must have different processing circuits.

Further, the VOQ processing unit needs to be provided with a packet link management unit for managing to which packet the data input in the page unit belongs.

As described above, every time the required number of accommodated HWs changes, the circuit configuration for realizing the packet switch device receiving unit differs, and there is a problem that the development cost is increased.

An object of the present invention is to propose a data processing method of a packet switch device receiving section which solves the above problems.

[0011]

According to the data processing method of the receiving unit of the packet switch device according to the present invention, the packet multiplexing of the input data for each of the accommodated HWs after the extraction of the packet is performed. Regardless of this, it is possible to process the packet data as continuous packet data, and the data link layer processing unit, the page division unit, the network layer processing INF unit, and the VOQ processing unit are shared by the same circuit.

More specifically, it has an input interface of a plurality of HWs from a transmission line, and has physical layer processing, data link layer processing, network layer processing (the above is processing for each layer of the OSI reference model), and a pag for switching.
e-division processing (packaging a packet as a unit of pag
e), and in the configuration of the packet switch device receiving unit that performs the VOQ process, a packet multiplexing function is provided after the physical layer process to perform packet multiplexing of a plurality of HWs, and the subsequent processes are accommodated in the transmission path. By treating it as continuous packet data regardless of the number of HWs,
Regardless of the number of HWs accommodated in the transmission path, the data link layer processing unit, the page division unit, the network layer processing INF unit, and the VOQ processing unit at the subsequent stage are configured by the same circuit irrespective of the number of HWs. .

In order to realize the configuration of the present invention, a packet multiplexing memory is newly required. However, the cost of the memory is expected to become lower, and the cost of sharing a circuit regardless of the number of accommodated HWs is expected. The benefits of reduction are greater.

In the present invention, the transmission path accommodation HW1 to HWn
Of the input data in the physical layer processing units 1 to n
The physical layer processing of the SI reference model is performed for each input HW, a packet for performing the data link layer processing of the OSI reference model is extracted, and the extracted packet is buffered in the packet multiplexing memory.

At this time, the packet length of each packet does not need to be the same, and when a packet of a certain HW is being read from the packet multiplexing unit, input data of another HW is buffered in a packet multiplexing memory. Is ringing.
The packet multiplexing unit sequentially reads out the buffered packets so as to be fair between the HWs and performs packet multiplexing.

The data link layer processing unit, the page division unit, the network layer processing INF unit, and the VOQ processing unit provided after the packet multiplexing unit process the data after the packet multiplexing. Regardless, it can be processed as continuous packet data.

Therefore, the data link layer processing unit, pa
The ge division unit and the network layer processing INF unit do not need to have parallel processing circuits for the number of accommodated HWs, and can perform processing by having one circuit for packet-multiplexed data. However, it can be realized with the same circuit configuration.

The VOQ processing unit pags the same packet.
Since the e-divided data is continuously input, the packet is transferred to the VOQ memory unit in a page unit which is a switching unit.
A request signal is transmitted to the switch unit for buffering each time and indicating an output destination to be transmitted, and a packet whose transmission is permitted by the scheduling of the switch unit is transmitted to the switch unit.

At this time, if the data is not packet-multiplexed, packets by a plurality of HWs are handled at the same time. Therefore, when writing / reading page data to / from the VOQ memory unit, link management in units of packets is performed. This link management unit has a different configuration depending on the number of accommodated HWs. However, in the present invention, since data is packet-multiplexed, when writing / reading page data to / from the VOQ memory unit for switching, It is not necessary to perform link management for each packet in
Whatever the number of W is HW, it can be realized with the same circuit configuration.

As described above, according to the present invention, the accommodation H of the transmission path
Regardless of the number of HWs, if the input data capacity is within the capacity that can be processed by the switch unit, a packet multiplexing memory and a circuit that can accommodate the number of HWs accommodating the packet multiplexing unit can be used for data link layer processing. Part, page
By sharing the dividing unit, the network layer processing INF unit, and the VOQ processing unit in the same circuit as a common unit,
It is possible to flexibly respond to changes in the number of accommodated HWs,
Development costs can be reduced.

[0021]

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, physical layer processing units 1-1 to 1-n are blocks for extracting packet data to be processed in each subsequent block, and perform physical layer processing of an OSI reference model on input data for each HW. To perform SDH termination.

When data is input to this block,
Since packet data has not yet been extracted and packet multiplexing cannot be performed, it is necessary to perform data processing before multiplexing in this block. Therefore, the physical layer processing units 1-1 to 1-1 for the number of accommodated HWs (for n circuits) -N.

The packet multiplexing memory unit 2 is a block for buffering input data of another HW while a packet of a certain HW is being read out by the packet multiplexing processing unit 3 at the subsequent stage for packet multiplexing. is there. The packet multiplexing unit 3 is a block that sequentially reads out the packets buffered for each HW and multiplexes the packets.

The data link layer processing unit 4 performs HDLC termination (High-level data link C) on the extracted and multiplexed packet data as data link layer processing.
ontrol Procedure, which is a kind of TCP / IP protocol of the data link layer, performs a high-level data link control procedure), and PPP termination (Point to Point Protocol, a kind of TCP / IP protocol of the data link layer, which connects to the Internet with a modem This is a block for performing a protocol used in the case of performing the operation.

The page division unit 5 is a block that divides the multiplexed packet data into pages that are processing units when switching is performed by the switch unit 10 at the subsequent stage.

The network layer processing INF unit 6 interfaces with the network layer processing unit 7,
This is a block for transmitting and receiving data required for destination resolution processing. The network layer processing unit 7 is a block that performs destination resolution in switching of packets input from each HW as network layer processing.

The VOQ processing section 8 buffers the page-divided packet data in the VOQ memory section 9,
This is a block for transmitting a request signal of a destination to be output to the switch unit 10 and transmitting a packet whose transmission has been permitted according to the scheduling process of the switch.

FIG. 2 is a block diagram showing details of packet multiplexing in the present invention. In FIG. 2, HDLC-Fra output from physical layer processing units 1-1 to 1-n
The me and PPP packets are respectively stored in buffer memories 12-1 to 12-n provided for each HW.

The packet multiplexing control unit 13 controls the HDLC-Frame output from the physical layer processing units 1-1 to 1-n.
e and the start position and end position information of the PPP packet, and the packet multiplexing buffer 12-1 according to the information.
12-n, and at the same time, performs packet multiplexing by controlling reading from each HW to be fair.

FIG. 3 is an example of a time chart in the case of multiplexing packets of input data for 4 HWs. The data output after the packet multiplexing is output so as to be fair among HW1 to HW4.

FIG. 4 is a block diagram showing details of the VOQ process in the present invention. 4, the VOQ memory unit 9 buffers the page-divided packet data in buffers 17-1 to 17-m (where m indicates the number of destination ports) for each destination, and the VOQ processing unit 8 pa
The destination information is received for each of the ge-divided packets, the request information for indicating the destination to be transmitted to the switch scheduler unit 20 and the A of the packet for which the transmission permission is obtained.
CK information is transmitted and received, and a packet for which transmission permission has been obtained is read.

Since the page unit data of the same packet is continuously input to the VOQ processing unit according to the present invention, the VOQ processing unit 8 does not need to confirm the address for each input page and perform buffering. Buffering can be easily performed for each packet data.

Next, the operation of the present embodiment will be described with reference to the drawings.

The physical layer processing units 1-1 to 1-n perform the physical layer processing of the OSI reference model for each input HW on the input data of the transmission path accommodation HW1 to HWn. The physical layer processing here is the termination processing of the SDH frame, and terminates the overhead part of the SDH frame shown in FIG.
HDLC-Flame from payload part of SDH frame
Extract e-packet.

This processing is packet extraction, and therefore, it is necessary to perform data processing before packet multiplexing. Therefore, processing units for the number of accommodated HWs (for n circuits) are required. Next, the physical layer processing units 1-1 to 1-n buffer the extracted packet data for each HW in the packet multiplexing buffer memories 12-1 to 12-n shown in FIG.

The physical layer processing units 1-1 to 1-n
The packet start / end position information of each packet is transmitted to the packet control unit 13 in FIG. 2, and the packet control unit 13 uses the packet multiplexing buffer memories 12-1 to 12-n in accordance with the information.
The packet multiplexing unit 3 performs packet multiplexing processing while controlling packet data to be read from each HW at the same time as reading packet data from the HW.

As a result, for example, when the number of HWs is n = 4, as shown after the packet multiplexing in FIG. 3, input data for 4 HWs is packet-multiplexed on the time axis. At this time, each HW
Packets have different lengths (packet lengths). Therefore, if the packet length of a certain HW from which data is being read is long, the input data of the other HWs during that time will have packet multiplexing buffers 12-1 to 12-. n.

Therefore, the packet multiplexing buffer 12-1
１２12-n requires a buffer capacity in consideration of the maximum packet length. The packet multiplexed data is transmitted to the data link layer processing unit 4 as shown in FIG.
Ame termination and PPP termination are performed, and a network layer packet for performing network layer processing is extracted.

Since the present circuit processes data after packet multiplexing, it is not necessary to have parallel processing circuits for the number of accommodated HWs, and it is sufficient to provide one circuit for packet-multiplexed data. Next, the data is page-divided by the page division unit 5 in units of processing when switching is performed by the switch unit 10 at the subsequent stage, and this circuit also performs 1 division on packet-multiplexed data similarly to the data link layer processing unit.
All you have to do is have a circuit.

Next, the data is sent to the network layer processing unit 7.
Performs the destination resolution in the switching of the packet input from each HW, and exchanges the data necessary for the destination resolution and the destination resolution result with the network layer processing I.
This is performed via the NF unit 6. Network layer processing INF
The unit 6 only needs to have one circuit for packet-multiplexed data, like the data link layer processing unit and the page division unit.

The configuration of one circuit for packet-multiplexed data as described above means that processing can be realized by the same circuit regardless of the number of HWs accommodated in the transmission path. Here, the network layer processing unit 7 needs to manage each input HW when deciding the switching destination, and cannot process the fluctuation of the number n of accommodated HWs with the same circuit, so that it is different from other processing blocks. Cannot be added to the common part 11 shown in FIG.

The HW information necessary for destination resolution must be transmitted from the packet multiplexing unit 3 to the network layer processing unit 7 on a separate line from the main signal. Next, for the data whose destination has been resolved, packet data that has been page-divided by the VOQ memory unit 9 in FIG.
7-m, and the VOQ processing unit 8 receives the destination information 21 at the same time.

The VOQ processing unit 8 transmits a request signal of a destination to be output to the switch unit in accordance with the received destination information, and receives and transmits ACK information of a packet for which transmission is permitted based on the scheduler processing of the switch scheduler unit 19. Read the permitted packet.

At this time, if the data is not packet-multiplexed, packets by a plurality of HWs are handled at the same time. Therefore, when writing / reading page data to / from the VOQ memory unit, link management in packet units must be performed. Although the circuit configuration of the link management unit differs depending on the number of accommodated HWs, the data is packet-multiplexed here. Therefore, it is not necessary to perform link management in packet units for switching, and the number of accommodated HWs is not required. What H
Even if it is W, it can be realized with the same circuit configuration.

As described above, by performing packet multiplexing of input data for each accommodated HW, regardless of the number of accommodated HWs in the transmission path, the data link layer processing unit 4, the page division unit 5, the network layer processing INF unit 6 , The VOQ processing unit 8 can be shared by the same circuit as the common unit 11, and the development cost can be reduced when the number of accommodated HWs changes.

FIG. 5 is a block diagram showing another embodiment of the present invention. This embodiment is different from the embodiment shown in FIG. 1 in that a network layer processing unit is provided in front of a packet multiplex processing unit, and network layer processing IN
The difference is that the F section is divided into transmission and reception, and transmission INF is performed from data buffered in the packet multiplexing memory.

Since the data link layer processing needs to be completed before the network layer processing is performed, the data link layer processing is provided as data link layer processing units 26-1 to 26-n at a stage preceding the network layer processing unit.

In this embodiment, when the network layer processing unit 28 requires a time longer than a fixed processing time for the destination resolution processing of the packet, a packet multiplexing memory which requires a large capacity for the packet multiplexing. Part 27
The packet is multiplexed by reading the packet data after the destination resolution is completed.

Thus, by using the packet multiplexing memory, there is a new effect that it is possible to cope with a case where the destination resolution processing of the packet of the network layer processing unit does not always end within a fixed processing.

[0050]

According to the present invention, by performing packet multiplexing of input data for each accommodated HW after extracting a packet, blocks subsequent thereto can be processed as continuous packet data regardless of the number of accommodated HWs. Since the data link layer processing unit, the page division unit, the network layer processing INF unit, and the VOQ processing unit can be shared by the same circuit, the development cost can be reduced with respect to a change in the number of accommodated HWs. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing details of packet multiplexing in the present invention.

FIG. 3 is a time chart illustrating packet multiplexing of input data for 4HW.

FIG. 4 is a block diagram illustrating details of a VOQ process according to the present invention.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

FIG. 6 is a block diagram showing a conventional example.

FIG. 7 is an explanatory diagram of an SDH frame.

[Explanation of symbols]

1-1 to 1-n, 25-1 to 25-n, 36-1 to 36
-N Physical layer processing unit 2 Packet multiplexing memory 3, 30 Packet multiplexing unit 4, 26-1 to 26-n, 37-1 to 37-n Data link layer processing unit 5, 31 Page splitting unit 6, 40 Network layer Processing INF unit 7, 28, 41 Network layer processing unit 8, 32, 42 VOQ processing unit 9, 33, 43 VOQ memory unit 10, 18, 34, 45 Switch unit 11, 35 Common unit 12-1 to 12-n Packet Multiplexing buffer 13 Packet multiplexing control section 17-1 to 17-m buffer 19 Switch scheduler section 27 Packet multiplexing memory & network layer processing transmission INF section 29 Network layer processing reception INF section 38-1 to 38-n page division Unit 39 page multiplexing unit 44 packet link management unit

Claims (5)

[Claims] 1. It has an input interface of a plurality of HWs from a transmission path, and has a p for physical layer processing, data link layer processing, network layer processing, and switching.
In the configuration of the packet switch device receiving unit that performs an age division process and a VOQ process, before performing the page division process, there is provided a packet multiplexing unit that multiplexes packets input from the plurality of HWs on a time axis in packet units. A data processing system for a packet switch device receiving unit. 2. The method according to claim 1, wherein the packet multiplexing unit includes a plurality of HWs.
A plurality of buffer memories for storing the packets extracted by the plurality of physical layer processing units provided for each of the HWs, based on the start position and end position information of the input packet received from each of the physical layer processing units. A packet multiplexing control unit that controls reading of packets stored in a plurality of buffer memories, and a packet multiplexing unit that multiplexes the read packets on a time axis and outputs the multiplexed packets. Item 2. The data processing method of the packet switch device receiving unit according to Item 1. 3. The packet multiplexing means according to claim 2, wherein
A plurality of buffer memories for storing the packets extracted by the plurality of data link layer processing units provided for each of the HWs, based on the start position and end position information of the input packet received from each of the data link layer processing units. A packet multiplexing control unit that controls reading of packets stored in the plurality of buffer memories, a network layer processing INF unit that performs network layer processing on the read packets, and a network layer processed packet. 2. A data processing method for a packet switch device receiving unit according to claim 1, comprising a packet multiplexing unit that multiplexes the data on a time axis and outputs the multiplexed data. 4. A plurality of physical layer processing units for performing physical layer processing of an OSI reference model on input data of a plurality of HWs for each input HW to extract packets, and extracting the packets by the plurality of physical layer processing units. H packets
A plurality of packet multiplexing buffer memories that accumulate for each W; and a packet read out from the plurality of buffer memories based on the start position and end position information of the input packet received from each of the physical layer processing units. A packet multiplexing unit that multiplexes and outputs the multiplexed packet; a data link layer processing unit that performs a data link layer process on the multiplexed packet; Page which is the processing unit of
A page division unit that divides the page data into packet data, a network layer processing INF unit that receives the page-divided packet data, performs an interface with a network layer processing unit, and transmits and receives data necessary for destination resolution processing; VOQ for buffering the divided packet data in a VOQ memory unit, transmitting a request signal of a destination to be output to a switch unit, and transmitting a packet whose transmission has been permitted according to a scheduling process of the switch.
A receiving unit for the packet switch device, comprising: a processing unit. 5. A plurality of physical layer processing units for performing a physical layer process of an OSI reference model for each input HW on input data of a plurality of HWs to extract a packet; H packets
A plurality of data link layer processing units for performing data link layer processing for each W; a packet multiplexing buffer memory for storing, for each HW, a packet subjected to the data link processing by the plurality of data link layer processing units; A network layer processing INF unit for receiving a packet read from the multiplexing buffer memory, interfacing with a network layer processing unit and transmitting / receiving data required for destination resolution processing, and a network layer processed packet A packet multiplexing unit that multiplexes and outputs the multiplexed packet on a time axis, and a page that divides the multiplexed packet into pages, which are processing units when switching is performed by a subsequent switch unit.
a VOQ buffering the page-divided packet data in a VOQ memory unit, transmitting a request signal of a destination to be output to a switch unit, and transmitting a packet whose transmission has been permitted according to a scheduling process of the switch.
A receiving unit for the packet switch device, comprising: a processing unit.