WO2000000960A1

WO2000000960A1 - Method of processing video data in pdp type tv receiver

Info

Publication number: WO2000000960A1
Application number: PCT/KR1999/000009
Authority: WO
Inventors: Joon Seok Park
Original assignee: Daewoo Electronics Co., Ltd.
Priority date: 1998-06-30
Filing date: 1999-01-04
Publication date: 2000-01-06

Abstract

A method of writing interlaced video data and reading the same, in/from an SRAM used as a frame memory in a PDP type TV receiver, where one frame comprises N x M pixels, each of pixels being sampled with L bits, and then K samples are reordered by L number of weight data and reading the same is described. First, the SRAM is divided into a first and a second field regions for storing odd field data and even field data, respectively. Second, the first aand second field regions is divided into L number of weight regions, respectively. Third, the odd field data are written into the L number of weight regions in the first field region according to weights. Fourth, the even field data are written into the L number of weight regions in the second field region according to weights. Finally, the first to fourth processes are performed repeatedly the step d) by N/K x M/2. Here, N is the number of horizontal pixels, M is the number of vertical lines, L is the number of subfields, and K is the number of bits of the weight data. Accordingly, in writing video data on a frame memory using an SRAM and reading the video data therefrom, the addressing method is simple.

Description

METHOD OF PROCESSING VIDEO DATA IN PDP TYPE TV RECEIVER

DESCRIPTION

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a method of processing video data in a plasma display panel (PDP) type TV receiver, and more particularly, to a method of rearranging video data sampled in 8 bits into units of 8 bits or 16 bits according to weight, recording the rearranged video data on a static random access memory

(SRAM) and reading the same.

BACKGROUND ART For attaining high-resolution vivid picture image in a display device for home-use, such as a television receiver, a large-scale display having a size of 50 inches or a small-sized display device which does not occupy a large area is increasingly demanded. In order to satisfy such a demand, recently, much attention has been paid to a flat type display device such as a liquid crystal display (LCD), a PDP, a flat-cathode ray tube or an electrioluminescent panel (ELP). However, it is not easy to fabricate a large-scale LCD and an ELP having a full-color display feature. The PDP having a thickness of approximately 3 cm for forming a picture image using luminescence due to a gas discharge is advantageous in terms of full- color and large-scale display and is applicable to wide fields including medium-, large- and superlarge-sized display devices. In particular, the PDP stands unchallenged in the field of a self-emission type large-scale HDTV displays. The PDP is classified into an alternating current (AC) type, a direct current (DC) type and an AC -DC hybrid type depending on its structural features and a difference between voltages applied thereto. Among these PDPs, since the AC-type PDP is completely digitized in terms of its driving characteristics, it is noted as a next-generation display in which a television and a personal computer are combined.

FIG. 1 shows a general AC-type color PDP-TV receiver. An audio/video portion 114 separates R.G.B analog signal and horizontal and vertical synchronization signals from a National Television System Committee (NTSC) composite video signal received through an antenna 112, obtains an average picture level (APL) corresponding to the average of brightness signals (Y) to then supply the obtained APL to an analog/digital converter 116. The received NTSC composite video signal based on an interlaced scanning method is composed of frames, each frame consisting of two fields, that is, an odd field and an even field. The analog/digital converter 116 receives the R.G.B analog signal and converts the same into R.G.B digital signal. An interlaced/non-interlaced scan converter 117 converts the R.G.B digital signal based on an interlaced scanning method into a video signal based on a non-interlaced scanning method to then output the converted R.G.B data to a memory unit 118. The memory unit 118 reconfigures one-field video data into a plurality of subfields for PDP gray-scale processing and then rearranges the same from the most significant bit (MSB) to the least significant bit (LSB), which will be described in more detail with reference to FIG. 2.

In FIG. 2, the memory unit 118 includes a data rearrangement portion 210, an address generator 220, a control clock generator (not shown), first and second frame memories 230 and 240, and a data selector 250. The data rearrangement portion 210 includes first and second shift registers 211 and 212, a D flip-flop & multiplexer 213, and first and second tri-state buffers 214 and 215, and rearranges the video data supplied in parallel, that is, from the MSB to the LSB, from the audio/video converter 116 so as to be stored as bits having the same weight in one address of the first and second frame memories 230 and 240. In other words, the first shift register 211 and the second shift register 212 alternately repeat a load operation and a shift operation to classify the sampled video data according to their weights. While the first shift register 211 loads 16 sampled video data, the second shift register 212 sequentially shifts 16 previously loaded video data and outputs the same. Also, while the first shift register 211 shifts the loaded video data according to their weights and outputs the same, the second shift register 212 loads 16 sampled video data again. Here, while the shifter register performing the load operation loads 16 video data, the shift register performing the shift operation shifts the video data 8 times. For better driving of the shift register, the input clock frequency is made to be double the output clock frequency. The D flip-flop & multiplexer 213 selects the data having the same weight output from either the first shift register 211 or the second shift register 212, whichever operating in a shift mode, and supplies the selected data to the first and second tri-state buffers 214 and 215. The first and second tri-state buffers 214 and 215 supply the rearranged video data supplied from the D flip-flop & multiplexer 213 to the first or second frame memory 230 or 240, whichever operating in a write mode. Generally, a PDP type TV receiver having an aspect ratio of 16:0, in which one- frame video data is approximately 10 Mbits, that is, 853 x 3 (R, G, B) x 480 x 8 (bits), alternately performs a write operation and a read operation in units of frames using the first and second frame memories 230 and 240 having a 10 Mbit memory capacity. The address generator 220 includes a write address generator 221 and a read address generator 222, generates addresses of data stored in the first or second frame memory 230 or 240 and supplies the generated addresses to the first or second frame memory 230 or 240. For PDP gray-scale processing, all of the video data constituting one frame are divided into subfields according to their weights. During the read operation, the video data corresponding to the respective frames are sequentially read to then be supplied to a data interface unit 120 (FIG. 1). Thus, the write address generator 221 and the read address generator 222 operate in a different manner.

The address selector 223 supplies the corresponding addresses to the first and second frame memories 230 and 240 according to the respective operation modes of the first and second frame memories 230 and 240, that is, a write mode or a read mode. The data selector 250 selects the video data output from the first or second frame memory 230 or 240, whichever operates in the read mode, and supplies the selected video data to the data interface unit 120. Referring back to FIG. 1, the data interface unit 120 temporarily stores the

R.G.B data supplied from the memory unit 118 and supplies the same to first and second address driver ICs 130 and 132 in conformity with a data format requested by the first and second address driver ICs 130 and 132. In other words, the R.G.B data output from the memory unit 118 are rearranged according to the R.G.B pixel arrangement principle of a PDP 134 to then be output to the first and second address driver ICs 130 and 132. The data interface unit 120 requires a space for temporarily storing data corresponding to 2 lines, that is, 640 lines x 3 (R, G, B) x 2 = 3840 (bits). Here, while the data corresponding to one line are input, the data corresponding to the other line are alternately output.

A high voltage driver circuit 126 combines DC voltages supplied from an AC/DC converter 124 according to logic control pulses output from a timing controller 122 and generates high voltage control pulses required by a scan/sustain driver IC 128 to then drive the PDP 134. Also, data streams supplied from the data interface unit 120 to the first and second address driver ICs 130 and 132 are turned to appropriately high voltage levels so as to be selectively written on the PDP 134. As described above, the method of storing a video signal in a memory for displaying a picture image on a PDP may vary according to kinds of memories. Here, the memories are classified into DRAMs, SRAMs, SDRAMs and so on. Accordingly, it is necessary to write and read a video signal on and from the RAM in a different manner depending on the kinds of the memories.

DISCLOSURE OF THE INVENTION

To solve the above problems, it is an object of the present invention to provide a method of writing and reading a video signal on and from a frame memory using a static random access memory (SRAM) in a PDP type TV receiver.

It is another object of the present invention to provide a read address generator for reading video signals for respective subfields according to their weight from an SRAM.

Accordingly, to achieve the first object, there is provided a method of writting interlaced video data in an SRAM used as a frame memory in a PDP type TV receiver, where one frame comprises N x M pixels, each of pixels being sampled with L bits, and then K samples are reordered by L number of weight data, comprising the steps of: a) dividing the SRAM into a first and a second field regions for storing odd field data and even field data, respectively; b) dividing the first and second field regions into L number of weight regions, respectively; c) writing the odd field data into the L number of weight regions in the first field region according to weights; d) writing the even field data into the L number of weight regions in the second field region according to weights; and e) performing repeatedly the step d) by N/K x M/2, wherein N is the number of horizontal pixels, M is the number of vertical lines, L is the number of subfields, and K is the number of bits of the weight data.

To achieve the first object, there is provided a method of reading interlaced video data in an SRAM having a first and a second field regions, each of field regions including L number of weight regions, respectively, used as a frame memory in a PDP type TV receiver, where one frame comprises N x M pixels, each of pixels being sampled with L bits, and then K samples are reordered by L number of weight data, comprising the steps of: a) reading the L number of weight data from the L number of weight region in the first field region, respectively so as to form L number of weight data for M/2 number of odd lines; and b) reading the L number of weight data from the L number of weight region in the second field region, respectively so as to form L number of weight data for M/2 number of even lines, wherein N is the number of horizontal pixels, M is the number of vertical lines, L is the number of subfields, and K is the number of bits of the weight data.

To achieve the second object, there is provided a read address generator for for reading video signals for respective subfields according to their weight from an SRAM used as a frame memory in a PDP type TV receiver, comprising: a first counter for receiving a subframe discrimination pulse between the respective subframes and outputting a counting signal; a decoder for receiving the subframe counting signal output from the first counter and outputting an upper read address indicative of each weight region of the frame memory; a read clock generator for receiving a horizontal synchronization signal, a vertical synchronization signal and a basic clock and generating a first read clock for reading video data corresponding to one line in a weight region in the case of a wide mode and a second read clock for reading video data corresponding to one line in the weight region in the case of a general screen mode; a second counter for receiving the first or the second read clock output from the read clock generator and the vertical synchronization signal and outputting a lower read address for defining the address in the weight region at which the video data to be read is positioned, for reading the video data corresponding to one frame from the weight region; and an adder for adding the upper read address output from the decoder and the lower read address output from the second counter and outputting a read address to then output the same to the frame memory.

The read clock generator comprises: a third counter for receiving a horizontal synchronization signal, a vertical synchronization signal and a basic clock and generating the first read clock for reading video data corresponding to one line in a weight region in the case of a wide mode; and a fourth counter for receiving the first read clock output from the third counter and a wide screen mode selection signal and outputting a blank pulse and the second read clock for reading video data corresponding to one line in the weight region in the case of a general screen mode.

BRIEF DESCRIPTION OF THE DRAWINGS

The above object and advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which: FIG. 1 is a block diagram of a general AC type color PDP-TV receiver;

FIG. 2 is a block diagram of a memory unit shown in FIG. 1;

FIG. 3 is a diagram showing a data format in a state in which sampled video data are sorted by a 8 -bit shift register;

FIG. 4 shows a memory map of a frame memory using an SRAM in which video data are stored in units of 8 bits according to a first embodiment of the present invention;

FIG. 5 shows a memory map of a frame memory using a SRAM in which video data are stored in units of 8 bits according to a first embodiment of the present invention; FIG. 6 shows a memory map of a frame memory using an SRAM in which video data are stored in units of 8 bits according to a second embodiment of the present invention;

FIG. 7a to 7e are timing diagrams of clocks used in FIG. 6;

FIG. 8 is a block diagram of a read address generator exclusively used in a 853 X 480 mode according to a first embodiment of the present invention; and

FIG. 9 is a block diagram of a read address generator compatibly used in a 853 x 480 mode and a 640 x 480 mode according to a second embodiment of the present invention.

MODES OF CARRYING OUT THE INVENTION

Hereinbelow, according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 3 is a diagram showing a data format in a state in which 8-bit sampled video data are sorted by a 8-bit shift register. DO to D7 represent MSB to LSB weight data of the first to 8th sampled video data, respectively, and D8 to Dl l represent MSB to M-3 weight data of the 9th to 16th sampled video data, respectively. A video signal corresponding to one frame is sorted, as shown in FIG. 6, and is stored in the first or second frame memory (230 or 240 of FIG. 2). The number of addressing operations depending on a video mode will now be described. In other words, in the case of a 640 x 480 mode, a memory capacity of 640 x 480 x 8 (= 2,457,600) bits, is required for a channel, e.g., an R channel, and 80 (= 640/8) addressing operations are necessary for 8-bit processing for each line. In the case of a wide mode, that is, a 853 x 480 mode, a memory capacity of 853 x 480 x 8 (= 3,275,520) bits, is required for a channel, and approximately 107 (s 853/8) addressing operations are necessary for 8-bit processing.

Next, FIGs. 4 and 5 illustrate a first embodiment of the present invention of a memory map for storing 8-bit video data sorted according to their weights from the data rearrangement section 210, in which FIG. 4 shows a method for writing the video data on an SRAM and FIG. 5 shows a method for reading the video data from the SRAM.

Referring to FIG. 4, an SRAM is divided into an odd field storing region and an even field storing region for storing video data input based on an interlaced scanning method. The odd field storing region and the even field storing region are divided into regions for the respective weights. In other words, each of the odd field storing region and the even field storing region is divided into the MSB, (M- 1),..., (M-6) and LSB. In the odd field storing region, the MSB weight of the sampled video data of the odd field are stored in the MSB region, the (M-l) to LSB weights of the sampled video data of the odd field are stored in the (M-1) to LSB regions, respectively. In the even field storing region, the MSB weight of the sampled video data of the even field are stored in the MSB region, the (M-1) to LSB weights of the sampled video data of the even field are stored in the (M-1) to LSB regions, respectively.

For 8-bit processing, 80 addressing operations are necessary for writing the MSB weights of one line and 19200 (= 80 x 240, which corresponds to the number of vertical lines for each field) addressing operations are necessary for writing one field for each weight. Thus, in order to write the sampled video data of the odd field on the SRAM, the MSB weights of the first to 8th sampled video data are stored in the MSB regions of the odd field. Next, the write operation is jumped to the (M- 1) region of the odd field and the (M-1) weights of the first to 8th sampled video data are stored in the (M-1) region. The same procedure is repeatedly performed until the write operation is jumped to the LSB region of the odd field and the LSB weights of the first to 8th sampled video data are stored in the LSB region. Thereafter, the write operation is jumped to the MSB region of the odd field and the (M-1) weights of the 9th to 16th sampled video data are stored in the MSB region. The same procedure is repeatedly performed until the write operation is jumped to the LSB region of the odd field and the LSB weights of the 9th to 16th sampled video data are stored in the LSB region. The above-described procedure is repeated 80 times to thus complete the storing operations for one line by weights. Also, the above- described procedure is repeated 19200 times to thus complete the storing operations for one odd field by weights.

After the storing operations for the odd field by weights are completed, the storing operation for the even field are performed by weights. By using the same method as that of storing the sampled video data of the odd field on the SRAM, the sampled video data of the even field are written on the SRAM. In other words, the MSB weights of the first to 8th sampled video data are stored in the MSB regions of the even field. Next, the write operation is jumped to the (M-1) region of the even field and the (M-1) weights of the first to 8th sampled video data are stored in the (M-1) region. The same procedure is repeatedly performed until the write operation is jumped to the LSB region of the even field and the LSB weights of the first to 8th sampled video data are stored in the LSB region. Thereafter, the write operation is jumped to the MSB region of the even field and the (M-1) weights of the 9th to 16th sampled video data are stored in the MSB region. The same procedure is repeatedly performed until the write operation is jumped to the LSB region of the even field and the LSB weights of the 9th to 16th sampled video data are stored in the LSB region. The above-described procedure is repeated 80 times to thus complete the storing operations for one line by weights. Also, the above-described procedure is repeated 19200 times to thus complete the storing operations for one even field by weights. FIG. 5 show a method of reading the video data stored in the SRAM. The process of reading and display MSB weights of one frame will be described with reference to FIG. 5.

The first to 80th sampled data are read from the MSB regions of the odd field, thereby reading the MSB weights of the first line. Next, the read operation is jumped to the MSB region of the even field and the first to 80th sampled data are read from the MSB regions, thereby reading the MSB weights of the second line. Next, the read operation is jumped to the MSB region of the odd field and the 81st to 160th sampled data are read, thereby reading the MSB weights of the third line. Then, the read operation is jumped to the MSB region of the even field and the 81st to 160th sampled data are read, thereby reading the MSB weights of the fourth line. The same procedure is repeatedly performed until the read operation is jumped to the MSB region of the odd field and the 19121th to 19200th sampled data are read, thereby reading the MSB weights of the 479th line, and the read operation is jumped to the MSB region of the even field and the 19121th to 19200th sampled data are read, thereby reading the MSB weights of the 480th line.

In other words, the MSB weight data of the first line are read from the MSB region of the odd field and then the MSB weight data of the second line are read from the MSB region of the even field. Then, the MSB weight data of the third line are read from the MSB region of the odd field and then the MSB weight data of the fourth line are read from the MSB region of the even field. The above-described procedure is repeatedly performed 240 times, thereby reading all the MSB weight data corresponding to one frame, that is, one screen. As described above, according to the present invention, there is provided a method of writing video data on a frame memory using an SRAM in which the addressing method is simple and reading the video data from the frame memory. Accordingly, the reliability and stability of a plasma display panel (PDP) can be achieved and high-speed driving of the same is allowed.

Next, FIG. 6 shows a memory map of a frame memory using an SRAM in which video data sorted from the data rearrangement section 210 according to their weights are stored in units of 8 bits according to a second embodiment of the present invention. In order to store video data converted based on the non-interlaced scanning method, the SRAM is divided into several sections according to their weights. In other words, the MSB region starts from the address 00001H, the (M-1) region starts from the address 10001H, the (M-6) region starts from the address 60001H, and the LSB region starts from the address 70001H.

Here, the MSB weights of the sampled video data are stored in the MSB region by 8 bits, the (M-1) weights of the sampled video data are stored in the (M-1) region by 8 bits, the (M-2) weights of the sampled video data are stored in the MSB region by 8 bits and the (M-6) weights of the sampled video data are stored in the (M-6) region by 8 bits. Finally, the LSB weights of the sampled video data are stored in the LSB region by 8 bits. In the case of a 853 x 480 mode, 107 addressing operations are necessary. Timing diagrams of clocks necessary for storing or reading the video data corresponding to one frame are shown in FIGs. 7A through 7E.

FIG. 7A shows a vertical synchronization signal, in which video data of one frame are addressed for one cycles of a vertical synchronization signal to then be sustaining-discharged on the PDP 134. FIG. 7B shows a subframe discrimination signal interposed between the respective subframes. The subframe is the video data corresponding to a weight when one frame is divided into weights. However, the sequence of subframes does not coincide with that of weights. Here, the first subframe is an MSB weight, the second subframe is a (M-2) weight, the third subframe is an LSB weight, the 6th subframe is a (M-5) weight, the 7th subframe is a (M-3) weight, and the 8th subframe is an LSB weight. Also, it is assumed that the frame is displayed in a sequence of the respective subframes. In other words, in order to display video data of one frame is displayed on the PDP 134, one frame is divided into 8 subframes and a subframe discrimination pulse is interleaved between the subframes to define the subframes, as shown in FIG. 7B.

In the case of a wide screen mode, one subframe consists of 480 vertical lines, and a line discrimination pulse is interleaved between the respective vertical lines, as shown in FIG. 7C, to define the respective vertical lines. For one vertical line period, 107 addressing operations are necessary in the case of a 853 x 480 mode, as shown in FIG. 7D, and 80 addressing operations are necessary in the case of a 640 x 480 mode, as shown in FIG. 7E. In other words, as described above, subframe discrimination pulses are interleaved between 8 subframes constituting one frame. The starting address of each subframe can be identified by counting the subframe discrimination pulses. Also, the exact address of video data in the pertinent subframe can be identified by counting all read clocks for addressing operations.

FIG. 8 shows a read address generator constituted by the above-described pulses according to the first embodiment of the present invention.

The read address generator includes a first counter 800, for example, a sub- frame counter for receiving a subframe discrimination pulse between the respective subframes and outputting a counting signal, a decoder 802 for receiving the subframe counting signal output from the first counter 800 and outputting an upper read address indicative of each weight region of a frame memory, a second counter 804, for example, a 107 counter for receiving a horizontal synchronization signal (line information), a vertical synchronization signal VSYNC and a basic clock CLK and generating a read clock r_clk for reading video data corresponding to one line in a weight region, a third counter 806, for example, a 51360 counter for receiving the read clock r_clk and outputting a lower read address for accurately defining the address in the weight region at which the video data to be read is positioned for read the video data corresponding to one frame, and an adder 808 for adding the upper read address output from the decoder 802 and the lower read address output from the third counter 806 and outputting the addition result to the frame memory. By the structure thus constructed, the read addresses using in a PDP system exclusively used for a 853 x 480 wide mode display can be generated. The operation and effects of the present invention will now be described.

The first counter 800 counts a subframe discrimination pulse SFsignal and is reset by a vertical synchronization signal VSYNC- In other words, the first counter 800 outputs a 3-bit subframe counting signal, that is, a BCD signal converted from '000' to '111 ' when it is reset by the vertical synchronization signal V_SYNC The decoder 802 receives the subframe counting signal output from the first counter 800 and outputs a starting address of the weight region corresponding to the subframe, which is demonstrated in the following table 1. In other words, only the upper read address representing the weight region among the read addresses is output from the decoder 802. Table 1

The second counter 804 for receiving a line discrimination pulse, that is, line information, a clock signal CLK and a vertical synchronization signal VSYNC, counts the clock signal when the line discrimination pulse (line information) and outputs 107 read clocks r_clk for each vertical line. The third counter 806 counts read clocks corresponding to 480 lines and outputs lower read addresses of 0001H to C8A0H which is converted into 51360 by decimal notation, for each frame. The adder 808 adds the upper read address output from the decoder 802 and the lower read address output from the third counter 806 and outputs a 19-bit read address [18,..., 0].

For example, if the output signal of the third counter 800 is 'Oi l', the decoder 802 output an address signal 60000H and the third counter 806 counts the read clock r_clk to output the addresses ranging from 0001H to C8A0H. Finally, the read addresses from 60001H to 6C8A0H are output. Thus, the (M-6) weights written in the (M-6) region of the frame memory are sequentially read to then be displayed on a PDP 134.

FIG. 9 shows a read address generator which can be used for a PDP 134 enabling a 853 x 480 wide mode or a 640 x 480 general mode display, according to the second embodiment of the present invention.

The read address generator includes a first counter 900, for example, a sub- frame counter for receiving a subframe discrimination pulse between the respective subframes and outputting a counting signal, a decoder 902 for receiving the subframe counting signal output from the first counter 900 and outputting an upper read address indicative of each weight region of a frame memory, a second counter 904, for example, a 107 counter for receiving a horizontal synchronization signal (line information), a vertical synchronization signal V_SYN_C and a basic clock CLK and generating a 107 read clocks CLK 107 for reading video data corresponding to one line in a weight region in the case of a wide mode, a third counter 906, for example, a 80 counter for receiving the 107 read clock CLK 107 output from the second counter 904 and a wide screen mode selection signal and outputting a blank pulse and a 80 read clock r_clk for reading video data corresponding to one line in the weight region in the case of a general screen mode, a fourth counter 908, for example, a 51360 counter for receiving the 107 read clock r_clk output from the third counter 906 and the vertical synchronization signal VSYNC and outputting a 16-bit lower read address for accurately defining the address in the weight region at which the video data to be read is positioned, for reading the video data corresponding to one frame from the weight region, and an adder 910 for adding the upper read address output from the decoder 902 and the lower read address output from the fourth counter 908 and outputting a 19-bit read address [18,..., 0] to then output the same to the frame memory. The operation and effects of the present invention will now be described.

The operation and effects of the first counter 900 and the decoder 902 are the same as those 800 and 802 shown in FIG. 8 and detailed explanation thereof will be omitted.

The second counter 907 receives the line information, the clock signal CLK and the vertical synchronization signal VSYNC- If the line information is input, the clock signal CLK is counted to output the 107 read clock CLK 107 for each vertical line. The 107 read clock CLK 107 and the wide screen mode selection signal are input to the third counter 906. If a general mode is selected, the third counter 906 is activated.

In other words, if the general mode is selected, the third counter 906 generates a 80 read clock r_clk necessary for reading the video data corresponding to one line from a weight region during a general driving mode and output the same to the fourth counter 908. If the wide mode is selected, the third counter 906 outputs the 107 read clock CLK 107 output from the second counter 904 and outputs the same to the fourth counter 908. The vertical synchronization signal VSYNC and the read clock r_clk output from the third counter 906 are input to the fourth counter 908. The fourth counter 908 is reset by the vertical synchronization signal VSYNC to thus count the read clock r_clk corresponding to 480 lines. In other words, if the PDP system is in a general mode, i.e., a 640 x 480 mode, the fourth counter 908 counts the addresses up to 38400 (= 80 x 480) and generates the lower read addresses of 000 IH to 96000H which is converted into 38400 by decimal notation. Also, if the PDP system is in a wide mode, i.e., 853 x 480 mode, the fourth counter 908 counts the addresses up to 51360 = 107 x 480) and generates the lower read addresses of 0001H to C8A0H which is converted into 51360 by decimal notation. The adder 910 adds the upper read address output from the decoder 902 and the lower read address output from the fourth counter 908 and outputs a 19-bit read address [18,..., 0].

The read addresses shown in FIGs. 8 and 9 are supplied to the frame memory comprised of an SRAM so that the video data written on the frame memory can be read for each subframe.

As described above, according the present invention, since read addresses can be generated using a simple circuit for reading video data for each subframe from the SRAM in which the video data are stored according to their weights, the reliability of the circuit can be improved and the fabrication cost can be reduced.

While this invention has been described in connection with what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiment, but, on the contrary, it is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

WHAT IS CLAIMED IS:

1. A method of writting interlaced video data in an SRAM used as a frame memory in a PDP type TV receiver, where one frame comprises N x M pixels, each of pixels being sampled with L bits, and then K samples are reordered by L number of weight data, comprising the steps of: a) dividing the SRAM into a first and a second field regions for storing odd field data and even field data, respectively; b) dividing the first and second field regions into L number of weight regions, respectively; c) writing the odd field data into the L number of weight regions in the first field region according to weights; d) writing the even field data into the L number of weight regions in the second field region according to weights; and e) performing repeatedly the step d) by N/K x M/2, wherein N is the number of horizontal pixels, M is the number of vertical lines, L is the number of subfields, and K is the number of bits of the weight data.

2. A method of reading interlaced video data in an SRAM having a first and a second field regions, each of field regions including L number of weight regions, respectively, used as a frame memory in a PDP type TV receiver, where one frame comprises N x M pixels, each of pixels being sampled with L bits, and then K samples are reordered by L number of weight data, comprising the steps of: a) reading the L number of weight data from the L number of weight region in the first field region, respectively so as to form L number of weight data for M/2 number of odd lines; and b) reading the L number of weight data from the L number of weight region in the second field region, respectively so as to form L number of weight data for M/2 number of even lines, wherein N is the number of horizontal pixels, M is the number of vertical lines, L is the number of subfields, and K is the number of bits of the weight data.

3. A read address generator for for reading video signals for respective subfields according to their weight from an SRAM used as a frame memory in a PDP type TV receiver, comprising: a first counter for receiving a subframe discrimination pulse between the respective subframes and outputting a counting signal; a decoder for receiving the subframe counting signal output from the first counter and outputting an upper read address indicative of each weight region of the frame memory; a second counter for receiving a horizontal synchronization signal, a vertical synchronization signal and a basic clock and generating a read clock for reading video data corresponding to one line in a weight region; a third counter for receiving the read clock and outputting a lower read address for defining the address in the weight region at which the video data to be read is positioned for read the video data corresponding to one frame; and an adder for adding the upper read address output from the decoder and the lower read address output from the third counter and outputting the addition result to the frame memory.

4. A read address generator for for reading video signals for respective subfields according to their weight from an SRAM used as a frame memory in a PDP type TV receiver, comprising: a first counter for receiving a subframe discrimination pulse between the respective subframes and outputting a counting signal; a decoder for receiving the subframe counting signal output from the first counter and outputting an upper read address indicative of each weight region of the frame memory; a read clock generator for receiving a horizontal synchronization signal, a vertical synchronization signal and a basic clock and generating a first read clock for reading video data corresponding to one line in a weight region in the case of a wide mode and a second read clock for reading video data corresponding to one line in the weight region in the case of a general screen mode; a second counter for receiving the first or the second read clock output from the read clock generator and the vertical synchronization signal and outputting a lower read address for defining the address in the weight region at which the video data to be read is positioned, for reading the video data corresponding to one frame from the weight region; and an adder for adding the upper read address output from the decoder and the lower read address output from the second counter and outputting a read address to then output the same to the frame memory.

5. The read address generator as claimed in claim 4, wherein said read clock generator comprises: a third counter for receiving a horizontal synchronization signal, a vertical synchronization signal and a basic clock and generating the first read clock for reading video data corresponding to one line in a weight region in the case of a wide mode; and a fourth counter for receiving the first read clock output from the third counter and a wide screen mode selection signal and outputting a blank pulse and the second read clock for reading video data corresponding to one line in the weight region in the case of a general screen mode.