WO2000000958A1

WO2000000958A1 - Method of processing video data in pdp type tv receiver

Info

Publication number: WO2000000958A1
Application number: PCT/KR1999/000010
Authority: WO
Inventors: Joon Seok Park
Original assignee: Daewoo Electronics Co., Ltd.
Priority date: 1998-06-30
Filing date: 1999-01-04
Publication date: 2000-01-06

Abstract

A method of writing video data rearranged according to their weights and reading the same, in/from a DRAM used as a frame memory in a PDP type TV receiver is described. In the writing method, the DRAM is divided into MSB to LSB row regions for storing MSB to LSB weight data, respectively. A first to 8th sampled video data of a first line are written in a first MSB to a first LSB rows of a first column according to their weights, respectively, and a 9th to 16th sampled video data of a first line are written in a second MSB to a second LSB rows in a first column according to their weights, respectively, so as to be written the video data of the first line according to their weights. The video data of an N-th line are written in an N-th MSB to an N-th LSB rows of an N-th column according to their weights, respectively by performing repeatedly the above process. According to the above method, the video data based on the interlaced/non-interlaced scanning method are written on a frame memory using the DRAM which is relatively cheap and the video data are read from the frame memory, the circuit reliability can be improved and the cost can be reduced.

Description

METHOD OF PROCESSING VIDEO DATA IN PDP TYPE TV RECEIVER

DESCRIPTION

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a method of processing video data in a plasma display panel (PDP) type TV receiver, and more particularly, to a method of rearranging video data sampled in 8 bits into units of 8 bits or 16 bits according to weight, recording the rearranged video data on a random access memory (DRAM) and reading the same.

BACKGROUND ART For attaining high-resolution vivid picture image in a display device for home-use, such as a television receiver, a large-scale display having a size of 50 inches or a small-sized display device which does not occupy a large area is increasingly demanded. In order to satisfy such a demand, recently, much attention has been paid to a flat type display device such as a liquid crystal display (LCD), a PDP, a flat-cathode ray tube or an electrioluminescent panel (ELP). However, it is not easy to fabricate a large-scale LCD and an ELP having a full-color display feature. The PDP having a thickness of approximately 3 cm for forming a picture image using luminescence due to a gas discharge is advantageous in terms of full- color and large-scale display and is applicable to wide fields including medium-, large- and superlarge-sized display devices. In particular, the PDP stands unchallenged in the field of a self-emission type large-scale HDTV displays. The PDP is classified into an alternating current (AC) type, a direct current (DC) type and an AC-DC hybrid type depending on its structural features and a difference between voltages applied thereto. Among these PDPs, since the AC-type PDP is completely digitized in terms of its driving characteristics, it is noted as a next-generation display in which a television and a personal computer are combined.

FIG. 1 shows a general AC-type color PDP-TV receiver. An audio/video portion 114 separates R.G.B analog signal and horizontal and vertical synchronization signals from a National Television System Committee (NTSC) composite video signal received through an antenna 112, obtains an average picture level (APL) corresponding to the average of brightness signals (Y) to then supply the obtained APL to an analog/digital converter 116. The received NTSC composite video signal based on an interlaced scanning method is composed of frames, each frame consisting of two fields, that is, an odd field and an even field. The analog/digital converter 116 receives the R.G.B analog signal and converts the same into R.G.B digital signal. An interlaced/non-interlaced scan converter 117 converts the R.G.B digital signal based on an interlaced scanning method into a video signal based on a non-interlaced scarining method to then output the converted R.G.B data to a memory unit 118. The memory unit 118 reconfigures one-field video data into a plurality of subfields for PDP gray-scale processing and then rearranges the same from the most significant bit (MSB) to the least significant bit (LSB), which will be described in more detail with reference to FIG. 2.

In FIG. 2, the memory unit 118 includes a data rearrangement portion 210, an address generator 220, a control clock generator (not shown), first and second frame memories 230 and 240, and a data selector 250. The data rearrangement portion 210 includes first and second shift registers 211 and 212, a D flip-flop & multiplexer 213, and first and second tri-state buffers 214 and 215, and rearranges the video data supplied in parallel, that is, from the MSB to the LSB, from the audio/video converter 116 so as to be stored as bits having the same weight in one address of the first and second frame memories 230 and 240. In other words, the first shift register 211 and the second shift register 212 alternately repeat a load operation and a shift operation to classify the sampled video data accordmg to their weights. While the first shift register 211 loads 16 sampled video data, the second shift register 212 sequentially shifts 16 previously loaded video data and outputs the same. Also, while the first shift register 211 shifts the loaded video data according to their weights and outputs the same, the second shift register 212 loads 16 sampled video data again. Here, while the shifter register performing the load operation loads 16 video data, the shift register performing the shift operation shifts the video data 8 times. For better driving of the shift register, the input clock frequency is made to be double the output clock frequency. The D flip-flop & multiplexer 213 selects the data having the same weight output from either the first shift register 211 or the second shift register 212, whichever operating in a shift mode, and supplies the selected data to the first and second tri-state buffers 214 and 215. The first and second tri-state buffers 214 and 215 supply the rearranged video data supplied from the D flip-flop & multiplexer 213 to the first or second frame memory 230 or 240, whichever operating in a write mode. Generally, a PDP type TV receiver having an aspect ratio of 16:0, in which one- frame video data is approximately 10 Mbits, that is, 853 x 3 (R, G, B) x 480 x 8 (bits), alternately performs a write operation and a read operation in units of frames using the first and second frame memories 230 and 240 having a 10 Mbit memory capacity. The address generator 220 includes a write address generator 221 and a read address generator 222, generates addresses of data stored in the first or second frame memory 230 or 240 and supplies the generated addresses to the first or second frame memory 230 or 240. For PDP gray-scale processing, all of the video data constituting one frame are divided into subfields according to their weights. During the read operation, the video data corresponding to the respective frames are sequentially read to then be supplied to a data interface unit 120 (FIG. 1). Thus, the write address generator 221 and the read address generator 222 operate in a different manner.

The address selector 223 supplies the corresponding addresses to the first and second frame memories 230 and 240 according to the respective operation modes of the first and second frame memories 230 and 240, that is, a write mode or a read mode. The data selector 250 selects the video data output from the first or second frame memory 230 or 240, whichever operates in the read mode, and supplies the selected video data to the data interface unit 120. Referring back to FIG. 1, the data interface unit 120 temporarily stores the

R.G.B data supplied from the memory unit 118 and supplies the same to first and second address driver ICs 130 and 132 in conformity with a data format requested by the first and second address driver ICs 130 and 132. In other words, the R.G.B data output from the memory unit 118 are rearranged according to the R.G.B pixel arrangement principle of a PDP 134 to then be output to the first and second address driver ICs 130 and 132. The data interface unit 120 requires a space for temporarily storing data corresponding to 2 lines, that is, 640 lines x 3 (R, G, B) x 2 = 3840 (bits). Here, while the data corresponding to one line are input, the data corresponding to the other line are alternately output.

A high voltage driver circuit 126 combines DC voltages supplied from an AC/DC converter 124 according to logic control pulses output from a timing controller 122 and generates high voltage control pulses required by a scan/sustain driver IC 128 to then drive the PDP 134. Also, data streams supplied from the data interface unit 120 to the first and second address driver ICs 130 and 132 are turned to appropriately high voltage levels so as to be selectively written on the PDP 134. As described above, the method of storing a video signal in a memory for displaying a picture image on a PDP may vary according to kinds of memories. Here, the memories are classified into DRAMs, SRAMs, SDRAMs and so on. Accordingly, it is necessary to write and read a video signal on and from the RAM in a different manner depending on the kinds of the memories.

DISCLOSURE OF THE INVENTION

To solve the above problems, it is an object of the present invention to provide a method of writing and reading a video signal on and from a frame memory using a dynamic random access memory (DRAM) in a PDP type TV receiver.

Accordingly, to achieve the above object according to a first embodiment, there is provided a method of writing video data rearranged according to their weights, in a DRAM used as a frame memory in a PDP type TV receiver, comprising the steps of: a) dividing the DRAM into MSB to LSB row regions for storing MSB to LSB weight data, respectively; b) storing a first to 8-th sampled video data of a first line in a first MSB to a first LSB rows in a first columns according to their weights, respectively; c) storing a 9-th to 16-th sampled video data of a first line in a second MSB to a second LSB rows in a first columns according to their weights, respectively; d) storing video data of the first line according to their weights by performing repeatedly the steps b) and c); and e) storing video data of an Nth line in an N-th MSB to an N-th LSB rows in an N-th columns according to their weights, respectively by performing repeatedly the step d), wherein N is an integer equal to or larger than 1. In addition, to achieve the above object according to the first embodiment, there is provided a method of of reading out video data corresponding to respective subframes from a DRAM having MSB to LSB row regions for storing MSB to LSB weight data according to their weights and vertical lines, respectively, comprising the steps of: a) reading out video data of the MSB row region of a first to N-th columns so as to form an MSB weight data of a first to N-th lines; and b) reading out video data of the M-l to LSB row region of a first to N-th column so as to form an M-l to LSB weight data of a first to Nth lines, wherein N is an integer equal to or larger than 1. To achieve the above object according to a second embodiment, there is provided a method of writing video data rearranged according to their weights, in a DRAM used as a frame memory in a PDP type TV receiver, comprising the steps of: a) dividing the DRAM into a first and a second column regions for storing odd and even field data, respectively; b) dividing the DRAM into MSB to LSB row regions for storing MSB to LSB weight data, respectively; c) writing a first to 8-th sampled video data of a first line among the odd field data in a first MSB to a first LSB rows in the first column region according to their weights, respectively; d) writing a 9-th to 16-th sampled video data of a first line among the odd field data in a second MSB to a second LSB rows in the first column region according to their weights, respectively; e) writing video data of the first line according to their weights by performing repeatedly the steps c) and d); f) writing video data of an M-th line in an M-th MSB to an M-th LSB rows in the first column region according to their weights, respectively by performing repeatedly the step e); g) writing a first to 8-th sampled video data of a first line among the even field data in a first MSB to a first LSB rows in the second column region according to their weights, respectively; h) writing a 9- th to 16-th sampled video data of a first line among the even field data in a second MSB to a second LSB rows in the second column region according to their weights, respectively; i) writing video data of the first line according to their weights by performing repeatedly the steps g) and h); and j) writing video data of an M-th line in an M-th MSB to an M-th LSB rows in the second column region according to their weights, respectively by performing repeatedly the step i), wherein M is an integer equal to or larger than 1. In addition, to achieve the above object according to a second embodiment, there is provided a method of reading out video data corresponding to respective subframes from a DRAM having a first and a second column regions for storing odd and even field data according to their weights and vertical lines, each of the column regions having MSB to LSB row regions for storing MSB to LSB weight data, respectively, comprising the steps of: a) reading out video data of the MSB row region of a first column from the first column region so as to form an MSB weight data of a first line; b) reading out video data of the MSB row region of a first column from the second column region so as to form an MSB weight data of a second line; c) reading out MSB weight data of odd lines corresponding to one frame from the MSB row region of the first column region and MSB weight data of even lines corresponding to one frame from the MSB row region of the second column region, by performing the steps a) and b); and d) reading out M-l to LSB weight data of odd lines corresponding to one frame from the M-l to LSB row region of the first column region and M-l to LSB weight data of even lines corresponding to one frame from the M-l to LSB row region of the second column region, by performing repeatedly the step c).

BRIEF DESCRIPTION OF THE DRAWINGS

The above object and advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which:

FIG. 1 is a block diagram of a general AC type color PDP-TV receiver; FIG. 2 is a block diagram of a memory unit shown in FIG. 1 ; FIG. 3 is a diagram showing a data format in a state in which sampled video data are sorted by a 8-bit shift register;

FIG. 4 shows a memory map of a frame memory using a DRAM in which video data are stored in units of 8 bits according to a first embodiment of the present invention; and

FIG. 5 shows a memory map of a frame memory using a DRAM in which video data are stored in units of 8 bits according to a second embodiment of the present invention. MODES OF CARRYING OUT THE INVENTION

Hereinbelow, according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 3 is a diagram showing a data format in a state in which 8-bit sampled video data are sorted by a 8-bit shift register. DO to D7 represent MSB to LSB weight data of the first to 8th sampled video data, respectively, and D8 to Dl l represent MSB to M-3 weight data of the 9th to 16th sampled video data, respectively. A video signal corresponding to one frame is sorted, as shown in FIG. 3, and is stored in the first or second frame memory (230 or 240 of FIG. 2). The number of addressing operations depending on a video mode will now be described. In other words, in the case of a 640 x 480 mode, a memory capacity of 640 x 480 x 8 (= 2,457,600) bits, is required for a channel, e.g., an R channel, and 80 (= 640/8) addressing operations are necessary for 8-bit processing for each line. In the case of a wide mode, that is, a 853 x 480 mode, a memory capacity of 853 x 480 x 8 (= 3,275,520) bits, is required for a channel, and approximately 107 (= 853/8) addressing operations are necessary for 8-bit processing.

Next, FIGs. 4 and 5 illustrate first and second embodiments of the present invention of a memory map of a frame memory using a DRAM in which the video data sorted from the data rearrangement portion 210 according to their weights are stored.

According to the first embodiment shown in FIG. 4, a DRAM is divided into 8 row regions. These 8 row regions include MSB to LSB row regions for storing- the MSB to LSB weight data, respectively. The NTSC video signals are generally input by an interlaced scanning method. Since the interlaced/non- interlaced scan converter (114 of FIG. 1) converts video signals based on the interlaced scanning method into those based on the non-interlaced scanning method, the video signals based on the non-interlaced scanning method are classified according to their weights and input to the memory unit (118 of FIG. 1).

A method of writing video data on a DRAM according to the respective weights will now be described with reference to FIG. 4.

Since 8-bit video data is written in one matrix address and 80 (= 640/8) addressing operations are necessary for each line in the case of a 640 x 480 mode, at least 80 rows are necessary for each row region. That is to say, each of the MSB, (M-l),..., (M-6) and LSB row regions consists of at least 80 rows. In the case of a 853 x 480 mode, 107 (= 853/8) addressing operations are necessary for each line and at least 107 rows are necessary for each of the MSB, (M-l),..., (M-6) and LSB row regions.

In both the 640 x 480 mode and the 853 x 480 mode, the DRAM is divided into 480 columns, due to 480 vertical lines, in the case of a non-interlaced scanning method. If the video data based on the non-interlaced scanning method are classified according to their weights and input, the first to 8-th sampled video data of the first line are stored in the first MSB, first (M-l),..., first (M-6) and first LSB rows in the first columns according to their weights, and the 9-th to 16-th sampled video data of the first line are stored in the second MSB, second (M-l), second (M-2),..., second (M-6) and second LSB rows in the first columns according to their weights, respectively. The above-described procedure is repeated 80 or 107 times in the case of the 640 x 480 mode or the 853 x 480 mode. By the repeated procedures, the video data of the first line can be stored in the MSB, (M-l), (M-2),... (M-6) and LSB row regions in the first column. Next, the above-described operations are repeatedly performed on the second to 480-th lines, thereby storing the video data of the second to 480-th lines of the odd field in the MSB, (M-l),..., (M-6) and LSB row regions in the second to 480-th columns according to their weights, respectively. Thus, the video data corresponding to one frame are classified according to their vertical lines or weights and stored. A method of reading the video data written in the DRAM in the above- described manner for each subfield will now be described with reference to FIG. 4.

First, if a data read signal is input, the data stored in the MSB row region of the first column are all read and the MSB weight data of the first line are all read, and the data stored in the MSB row region of the second to 480-th columns are all read and thus the MSB weight data of the second to 480-th lines are all read, thereby reading the MSB sub frames. Next, the read operation is jumped to the (M-l) row region of the first column and the (M-l) weight data of the first line are all read from the (M-l) row region of the first column. The same procedure is repeatedly performed until the (M-l) weight data of the 480-th line are all read from the (M-l) row region of the 480-th column. In such a manner, the (M-l) sub frames can be read.

Also, the above-described reading method is also applied to the (M-2) to LSB subframes. In other words, (M-2) subframes are read from the (M-2) row regions of the first to 480-th columns, and (M-3) subframes are read from the (M-3) row regions of the first to 480-th columns. The same procedure is repeatedly performed until the LSB subframes are read from the LSB row regions of the first to 480-th columns.

According to the first embodiment of the present invention, since the video data based on the interlaced/non-interlaced scanning method are written on a frame memory using the DRAM which is relatively cheap and the video data are read from the frame memory, the circuit reliability can be improved and the cost can be reduced.

According to the second embodiment of the present invention illustrated in

FIG. 5, a DRAM is largely divided into two column regions and 8 row regions.

Two column regions include a column region for storing odd field video data and another column region for storing even field video data. The 8 row regions include MSB to LSB row regions for storing MSB to LSB weight data, respectively.

The NTSC video signals are generally input by an interlaced scanning method. Odd field video signals are sampled and then classified according to their weights. The MSB weight data is stored in the MSB row region of the column region for storing the odd field video data. The (M-l) to (M-6) weight data are stored in the (M-l) to (M-6) row regions of the column region for storing the odd field video data, respectively. The LSB weight data is stored in the LSB row region of the column region for storing the odd field video data. Also, even field video signals are sampled and then classified according to their weights. The MSB weight data is stored in the MSB row region of the column region for storing the even field video data. The (M-l) to (M-6) weight data are stored in the (M-l) to (M-6) row regions of the column region for storing the even field video data, respectively. The LSB weight data is stored in the LSB row region of the column region for storing the even field video data.

A method of writing video data on a DRAM according to the respective weights will now be described with reference to FIG. 5.

Since 8-bit video data is written in one matrix address and 80 (= 640/8) addressing operations are necessary for each line in the case of a 640 x 480 mode, 80 rows are necessary for each row region. That is to say, each of the MSB to LSB row regions consists of at least 80 rows. In the case of a 853 x 480 mode, 107 (= 853/8) addressing operations are necessary for each line and at least 107 rows are necessary for each of the MSB, (M-l),..., (M-6) and LSB row regions. In both the 640 x 480 mode and the 853 x 480 mode, one frame is divided into an odd field and an even field in the case of an interlaced scanning method. Both the odd field and the even field have 240 (= 480/2) vertical lines, respectively. Thus, the column region for storing the odd field data and the column region for storing the even odd both have 240 columns for writing the odd and even fields on a DRAM for each line.

If odd field video data are input, the first to 8-th sampled video data of the first line of the odd field are stored in the first MSB, first (M-l),..., first (M-6) and first LSB rows in the first columns of the column region for storing the odd field data according to their weights, and the 9-th to 16-th sampled video data of the first line are stored in the second MSB, second (M-l), second (M-2),..., second (M-6) and second LSB rows in the first columns according to their weights, respectively. The above-described procedure is repeated 80 or 107 times in the case of the 640 x 480 mode_^or the 853 x 480 mode. Then, the video data of the first line can be stored in the MSB, (M-l), (M-2),... (M-6) and LSB row regions in the first column of the column region for storing the odd field data according to their weights, respectively. Next, the above-described operations are performed on the second to 240-th lines of the odd field, thereby storing the video data of the second to 240-th lines of the odd field in the MSB, (M-l),..., (M-6) and LSB row regions in the first column of the column region for storing the odd field data according to their weights, respectively. Next, If even field video data are input, the first to 8-th sampled video data of the first line of the even field are stored in the first MSB, first (M-l),..., first (M-6) and first LSB rows in the first columns of the column region for storing the even field data according to their weights, and the 9-th to 16-th sampled video data of the first line are stored in the second MSB, second (M-l), second (M-2),..., second (M-6) and second LSB rows in the first columns according to their weights, respectively. Here, if the above-described procedure is repeated 80 or 107 times, the video data of the first line of the even field are stored in the MSB, (M-l), (M-2),... (M-6) and LSB row regions in the first column of the column region for storing the even field data according to their weights, respectively. Next, the above-described operations are performed on the second to 240-th lines of the even field, thereby storing the video data of the second to 240-th lines of the even field in the MSB, (M-l),..., (M-6) and LSB row regions in the first column of the column region for storing the even field data according to their weights, respectively.

A method of reading the video data written in the DRAM in the above- described manner will now be described with reference to FIG. 5. First, if a data read signal is input, the data stored in the MSB row region of the first column in the column region for storing the odd field data are sequentially read and the MSB weight data of the first line are all read. The read operation is jumped to the column region for storing the even field data, the data stored in the MSB row region of the first column are sequentially read and thus the MSB weight data of the second line are all read. Next, the read operation is again jumped to the column region for the odd field data, the MSB weight data of the third line are all read from the MSB row region of the second column. Then, the read operation is again jumped to the column region for storing the even field data and the MSB weight data of the fourth line are all read from the MSB row region of the second column.

As described above, while the column region for storing the odd field data and the column region for storing the even field data are alternately jumped, the MSB weight data of the odd lines, that is, the first, third,..., 477-th and 479-th lines, of one frame are read from the MSB row regions of the column region for storing the odd field data and the MSB weight data of the even lines, that is, the second, fourth,..., 478-th and 480-th lines, of one frame are read from the MSB row regions of the column region for storing the even field data, thereby obtaining all the MSB subframes of one frame.

Also, the above-described reading method is also applied to the (M-l), (M- 2),..., (M-6) and LSB weight data. In other words, the operations of reading the (M- 1) weight data of the odd lines corresponding to one frame from the (M-l) row regions in the column region for storing the odd field data and reading the (M-l) weight data of the even lines corresponding to one frame from the (M-l) row regions in the column region for storing the even field data are alternately performed 240 times, thereby obtaining (M-l) subframes corresponding to one frame. The operations of reading the LSB weight data of the odd lines corresponding to one frame from the LSB row regions in the column region for storing the odd field data and reading the LSB weight data of the even lines corresponding to one frame from the LSB row regions in the column region for storing the even field data are alternately performed 240 times, thereby obtaining LSB subframes corresponding to one frame. According to the second embodiment of the present invention, since the video data based on the non-interlaced scanning method are written on a frame memory using the DRAM which is relatively cheap and the video data are read from the frame memory, the circuit reliability can be improved and the cost can be reduced.

While this invention has been described in connection with what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiment, but, on the contrary, it is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

WHAT IS CLAIMED IS:

1. A method of writing video data rearranged according to their weights, in a DRAM used as a frame memory in a PDP type TV receiver, comprising the steps of: a) dividing the DRAM into MSB to LSB row regions for storing MSB to

LSB weight data, respectively; b) writing a first to 8-th sampled video data of a first line in a first MSB to a first LSB rows in a first columns according to their weights, respectively; c) writing a 9-th to 16-th sampled video data of a first line in a second MSB to a second LSB rows in a first columns according to their weights, respectively; d) writing video data of the first line according to their weights by performing repeatedly said steps b) and c); and e) writing video data of an N-th line in an N-th MSB to an N-th LSB rows in an N-th columns according to their weights, respectively by performing repeatedly said step d), wherein N is an integer equal to or larger than 1.

2. A method of reading out video data corresponding to respective subframes from a DRAM having MSB to LSB row regions for storing MSB to LSB weight data according to their weights and vertical lines, respectively, comprising the steps of: a) reading out video data of the MSB row region of a first to N-th columns so as to form an MSB weight data of a first to N-th lines; and b) reading out video data of the M-l to LSB row region of a first to N-th column so as to form an M-l to LSB weight data of a first to N-th lines, wherein N is an integer equal to or larger than 1.

3. A method of writing video data rearranged according to their weights, in a DRAM used as a frame memory in a PDP type TV receiver, comprising the steps of: a) dividing the DRAM into a first and a second column regions for storing odd and even field data, respectively; b) dividing the DRAM into MSB to LSB row regions for storing MSB to

LSB weight data, respectively; c) writing a first to 8-th sampled video data of a first line among the odd field data in a first MSB to a first LSB rows in the first column region according to their weights, respectively; d) writing a 9-th to 16-th sampled video data of a first line among the odd field data in a second MSB to a second LSB rows in the first column region according to their weights, respectively; e) writing video data of the first line according to their weights by performing repeatedly said steps c) and d); f) writing video data of an M-th line in an M-th MSB to an M-th LSB rows in the first column region according to their weights, respectively by performing repeatedly said step e); g) writing a first to 8-th sampled video data of a first line among the even field data in a first MSB to a first LSB rows in the second column region according to their weights, respectively; h) writing a 9-th to 16-th sampled video data of a first line among the even field data in a second MSB to a second LSB rows in the second column region according to their weights, respectively; i) writing video data of the first line according to their weights by performing repeatedly said steps g) and h); and j) writing video data of an M-th line in an M-th MSB to an M-th LSB rows in the second column region according to their weights, respectively by performing repeatedly said step i), wherein M is an integer equal to or larger than 1.

4. A method of reading out video data corresponding to respective subframes from a DRAM having a first and a second column regions for storing odd and even field data according to their weights and vertical lines, each of the column regions having MSB to LSB row regions for storing MSB to LSB weight data, respectively, comprising the steps of: a) reading out video data of the MSB row region of a first column from the first column region so as to form an MSB weight data of a first line; b) reading out video data of the MSB row region of a first column from the second column region so as to form an MSB weight data of a second line; c) reading out MSB weight data of odd lines corresponding to one frame from the MSB row region of the first column region and MSB weight data of even lines corresponding to one frame from the MSB row region of the second column region, by performing said steps a) and b); and d) reading out M-l to LSB weight data of odd lines corresponding to one frame from the M-l to LSB row region of the first column region and M-l to LSB weight data of even lines corresponding to one frame from the M-l to LSB row region of the second column region, by performing repeatedly said step c).